JP4254430B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4254430B2 JP4254430B2 JP2003305926A JP2003305926A JP4254430B2 JP 4254430 B2 JP4254430 B2 JP 4254430B2 JP 2003305926 A JP2003305926 A JP 2003305926A JP 2003305926 A JP2003305926 A JP 2003305926A JP 4254430 B2 JP4254430 B2 JP 4254430B2
- Authority
- JP
- Japan
- Prior art keywords
- hydrogen
- insulating film
- interlayer insulating
- film
- element isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/3003—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0151—Manufacturing their isolation regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Description
図1、図2は第1実施形態を示す断面工程図であり、以下これらの図に基づいて本発明の第1実施形態を説明する。
図5、図6は第2実施形態を示す断面工程図であり、以下これらの図に基づいて本発明の第2実施形態を説明する。
図7は第3実施形態を示す断面工程図であり、以下これらの図に基づいて本発明の第3実施形態を説明する。
図8は第4実施形態を示す断面工程図であり、以下これらの図に基づいて本発明の第4実施形態を説明する。
Claims (4)
- 絶縁性の素子分離領域で分離された半導体基板の表面領域にトランジスタを形成する工程と、
前記トランジスタが形成された半導体基板上に層間絶縁膜を形成すると共に、前記層間絶縁膜における接続孔に前記トランジスタに接続されたプラグを形成し、前記層間絶縁膜における配線溝に前記プラグに接続される配線をパターン形成する工程と、
前記配線を形成した後、前記層間絶縁膜に前記素子分離領域に達する孔を形成し、次いで前記孔内に水素含有材料からなる水素含有絶縁膜を埋め込んで水素供給路を形成する工程と、
前記水素供給路が形成された層間絶縁膜上にカバー膜を形成した状態で、熱処理を行うことにより前記水素供給路から前記素子分離領域を介して前記半導体基板に水素を供給する工程とを有する
ことを特徴とする半導体装置の製造方法。 - 前記半導体基板の深さ方向には酸化膜層が設けられ、前記素子分離領域が前記酸化膜層に達しており、
前記水素を供給する工程では、前記水素供給路から前記素子分離領域を介して前記酸化膜層に水素を供給し、前記酸化膜層から前記半導体基板の表面側に水素を供給する
請求項1記載の半導体装置の製造方法。 - 前記孔内に水素含有材料からなる水素含有絶縁膜を埋め込む工程は、前記孔内を埋め込むように、水素含有材料からなる水素含有絶縁膜を前記層間絶縁膜上に形成する
請求項1または2に記載の半導体装置の製造方法。 - 前記層間絶縁膜を形成する工程では、水素の拡散を防止するバリア膜と他の膜とを積層形成する
請求項1〜3の何れか1項に記載の半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003305926A JP4254430B2 (ja) | 2003-08-07 | 2003-08-29 | 半導体装置の製造方法 |
US10/910,992 US20050032320A1 (en) | 2003-08-07 | 2004-08-04 | Method for manufacturing a semiconductor device and a semiconductor device manufactured thereby |
TW093123732A TWI268559B (en) | 2003-08-07 | 2004-08-06 | A method for manufacturing a semiconductor device and a semiconductor device manufactured thereby by forming an inter-layer insulation film with a hydrogen-supplying path |
KR1020040062062A KR20050016206A (ko) | 2003-08-07 | 2004-08-06 | 반도체 디바이스의 제조 방법 및 이에 의해 제조된 반도체디바이스 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003288417 | 2003-08-07 | ||
JP2003305926A JP4254430B2 (ja) | 2003-08-07 | 2003-08-29 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005072541A JP2005072541A (ja) | 2005-03-17 |
JP4254430B2 true JP4254430B2 (ja) | 2009-04-15 |
Family
ID=34117969
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003305926A Expired - Fee Related JP4254430B2 (ja) | 2003-08-07 | 2003-08-29 | 半導体装置の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20050032320A1 (ja) |
JP (1) | JP4254430B2 (ja) |
KR (1) | KR20050016206A (ja) |
TW (1) | TWI268559B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200029261A (ko) * | 2018-09-10 | 2020-03-18 | 삼성전자주식회사 | 메모리 소자의 제조 방법 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008182063A (ja) * | 2007-01-25 | 2008-08-07 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP4137161B1 (ja) * | 2007-02-23 | 2008-08-20 | キヤノン株式会社 | 光電変換装置の製造方法 |
JP5220361B2 (ja) * | 2007-07-31 | 2013-06-26 | ルネサスエレクトロニクス株式会社 | 半導体ウエハおよび半導体装置の製造方法 |
US9136463B2 (en) | 2007-11-20 | 2015-09-15 | Qualcomm Incorporated | Method of forming a magnetic tunnel junction structure |
US8049297B2 (en) * | 2007-12-11 | 2011-11-01 | Hvvi Semiconductors, Inc. | Semiconductor structure |
WO2009101704A1 (ja) * | 2008-02-15 | 2009-08-20 | Unisantis Electronics (Japan) Ltd. | 半導体装置の製造方法 |
US8669644B2 (en) * | 2009-10-07 | 2014-03-11 | Texas Instruments Incorporated | Hydrogen passivation of integrated circuits |
US20110079878A1 (en) * | 2009-10-07 | 2011-04-07 | Texas Instruments Incorporated | Ferroelectric capacitor encapsulated with a hydrogen barrier |
US8946091B2 (en) * | 2011-04-28 | 2015-02-03 | Lam Research Corporation | Prevention of line bending and tilting for etch with tri-layer mask |
JP6346488B2 (ja) * | 2014-04-21 | 2018-06-20 | キヤノン株式会社 | 半導体装置、固体撮像装置、それらの製造方法およびカメラ |
CN116190413A (zh) * | 2021-12-24 | 2023-05-30 | 北京超弦存储器研究院 | 半导体结构的制作方法及半导体结构 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3579391A (en) * | 1967-01-05 | 1971-05-18 | Trw Inc | Method of producing dielectric isolation for monolithic circuit |
FR2728399B1 (fr) * | 1994-12-20 | 1997-03-14 | Bouadma Nouredine | Composant laser a reflecteur de bragg en materiau organique et procede pour sa realisation |
US5534462A (en) * | 1995-02-24 | 1996-07-09 | Motorola, Inc. | Method for forming a plug and semiconductor device having the same |
US5866946A (en) * | 1996-05-23 | 1999-02-02 | Kabushiki Kaisha Toshiba | Semiconductor device having a plug for diffusing hydrogen into a semiconductor substrate |
US5872045A (en) * | 1997-07-14 | 1999-02-16 | Industrial Technology Research Institute | Method for making an improved global planarization surface by using a gradient-doped polysilicon trench--fill in shallow trench isolation |
US6143634A (en) * | 1997-07-28 | 2000-11-07 | Texas Instruments Incorporated | Semiconductor process with deuterium predominance at high temperature |
JP3098474B2 (ja) * | 1997-10-31 | 2000-10-16 | 日本電気株式会社 | 半導体装置の製造方法 |
US6140691A (en) * | 1997-12-19 | 2000-10-31 | Advanced Micro Devices, Inc. | Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate |
JP3125781B2 (ja) * | 1999-03-03 | 2001-01-22 | ヤマハ株式会社 | 半導体装置の製法 |
US6521977B1 (en) * | 2000-01-21 | 2003-02-18 | International Business Machines Corporation | Deuterium reservoirs and ingress paths |
US6596576B2 (en) * | 2001-04-10 | 2003-07-22 | Applied Materials, Inc. | Limiting hydrogen ion diffusion using multiple layers of SiO2 and Si3N4 |
JP2003188383A (ja) * | 2001-12-14 | 2003-07-04 | Hitachi Ltd | 半導体集積回路装置及びその製造方法 |
JP3723173B2 (ja) * | 2002-11-06 | 2005-12-07 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法 |
TWI328837B (en) * | 2003-02-28 | 2010-08-11 | Semiconductor Energy Lab | Semiconductor device and method of manufacturing the same |
JP2005093910A (ja) * | 2003-09-19 | 2005-04-07 | Toshiba Corp | 半導体記憶装置とその製造方法 |
-
2003
- 2003-08-29 JP JP2003305926A patent/JP4254430B2/ja not_active Expired - Fee Related
-
2004
- 2004-08-04 US US10/910,992 patent/US20050032320A1/en not_active Abandoned
- 2004-08-06 KR KR1020040062062A patent/KR20050016206A/ko not_active Application Discontinuation
- 2004-08-06 TW TW093123732A patent/TWI268559B/zh active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200029261A (ko) * | 2018-09-10 | 2020-03-18 | 삼성전자주식회사 | 메모리 소자의 제조 방법 |
KR102563922B1 (ko) | 2018-09-10 | 2023-08-04 | 삼성전자 주식회사 | 메모리 소자의 제조 방법 |
Also Published As
Publication number | Publication date |
---|---|
JP2005072541A (ja) | 2005-03-17 |
TWI268559B (en) | 2006-12-11 |
KR20050016206A (ko) | 2005-02-21 |
US20050032320A1 (en) | 2005-02-10 |
TW200511447A (en) | 2005-03-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100441682B1 (ko) | 엘디디형 소오스/드레인 영역을 갖는 반도체 장치 및 그제조 방법 | |
US8357600B2 (en) | Method for fabricating buried gate using pre landing plugs | |
KR101129919B1 (ko) | 반도체 소자 및 그의 형성 방법 | |
CN101154629B (zh) | 半导体器件及其制造方法 | |
JP4254430B2 (ja) | 半導体装置の製造方法 | |
JP4658486B2 (ja) | 半導体装置とその製造方法 | |
JP2010050202A (ja) | 半導体装置およびその製造方法 | |
JP4940533B2 (ja) | 半導体集積回路装置の製造方法 | |
JP2002141482A (ja) | 半導体装置およびその製造方法 | |
US8258059B2 (en) | High voltage-resistant semiconductor device and method of manufacturing high voltage-resistant semiconductor device | |
JP2008047630A (ja) | 半導体装置およびその製造方法 | |
KR20010051026A (ko) | 반도체 장치 및 그 제조 방법 | |
JP2009016828A (ja) | 半導体装置の製造方法 | |
JPH11288935A (ja) | 半導体装置およびその製造方法 | |
JP3651369B2 (ja) | 半導体装置の製造方法 | |
JP2006339558A (ja) | 半導体装置の製造方法 | |
JP2004363255A (ja) | 半導体装置及びその製造方法 | |
JP2001093992A (ja) | 半導体装置およびその製造方法 | |
KR101021176B1 (ko) | 반도체 소자의 금속배선 형성방법 | |
KR101005737B1 (ko) | 반도체 소자의 금속배선 형성방법 | |
JPH0661445A (ja) | 半導体記憶装置およびその製造方法 | |
JP5288734B2 (ja) | 半導体装置およびその製造方法 | |
JP2006080129A (ja) | 半導体装置の製造方法 | |
JP3173597B2 (ja) | 半導体装置及びその製造方法 | |
JP4561060B2 (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050218 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20070903 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080722 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080919 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20081021 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20081205 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090106 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090119 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120206 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120206 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |