JP4224434B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Description
以下、本発明の第1の実施形態に係る半導体装置及び半導体装置の製造方法について、図1(a)及び(b)並びに図2(a)〜(c)を参照しながら説明する。
以下、本発明の第2の実施形態に係る半導体装置及び半導体装置の製造方法について、図3(a)及び(b)並びに図4(a)〜(c)を参照しながら説明する。なお、第2の実施形態では、第1の実施形態と共通する部分は同様であるので、その説明は繰り返さないことにして、以下では、第1の実施形態と異なる点を中心に説明する。
2 第1の絶縁膜
3 第1のバリアメタル膜
4 第1の銅配線
5 拡散防止膜
6 第2の絶縁膜
6a ビアホール
6b 配線溝
6c 凹部
7 金属酸化物膜
7a 第1の金属酸化物膜
7b 第2の金属酸化物膜
8 金属化合物膜
9 金属膜
10 第2の銅配線
A1、A2 第2のバリアメタル膜
101 シリコン基板
102 第1の絶縁膜
103 第1のバリアメタル膜
104 第1の銅配線
105 拡散防止膜
106 第2の絶縁膜
106a ビアホール
106b 配線溝
106c 凹部
107、108 第2のバリアメタル膜
109 第3のバリアメタル膜
Claims (14)
- 基板上に形成された絶縁膜と、前記絶縁膜中に形成された埋め込み金属配線と、前記絶縁膜と前記金属配線との間に形成されたバリアメタル膜とを有する半導体装置において、
前記バリアメタル膜は、前記絶縁膜が存在している側から前記金属配線が存在している側へ向かって順に積層されている金属酸化物膜、金属化合物膜及び金属膜よりなり、
前記金属化合物膜の弾性率は、金属酸化物膜の弾性率よりも大きいことを特徴とする半導体装置。 - 前記絶縁膜と前記金属酸化物膜とは接合して形成されていると共に、
前記金属膜と前記金属配線とは接合して形成されていることを特徴とする請求項1に記載の半導体装置。 - 前記金属酸化物膜は、導電性を有することを特徴とする請求項1に記載の半導体装置。
- 基板上に形成された絶縁膜と、前記絶縁膜中に形成された埋め込み金属配線と、前記絶縁膜と前記金属配線との間に形成されたバリアメタル膜とを有する半導体装置において、
前記バリアメタル膜は、前記絶縁膜が存在している側から前記金属配線が存在している側に向かって順に積層されている第1の金属酸化物膜、金属化合物膜、第2の金属酸化物膜及び金属膜よりなり、
前記金属化合物膜の弾性率は、前記第1の金属酸化物膜の弾性率及び前記第2の金属酸化物膜の弾性率のそれぞれよりも大きいことを特徴とする半導体装置。 - 前記絶縁膜と前記第1の金属酸化物膜とは接合して形成されていると共に、
前記金属膜と前記金属配線とは接合して形成されていることを特徴とする請求項4に記載の半導体装置。 - 前記第1の金属酸化物膜及び前記第2の金属酸化物膜のうちの少なくとも一方は、導電性を有することを特徴とする請求項4に記載の半導体装置。
- 前記金属化合物膜を構成する金属は、高融点金属であることを特徴とする請求項1又は4に記載の半導体装置。
- 前記金属膜を構成する金属は、酸化されても導電性を失わない金属であることを特徴とする請求項1又は4に記載の半導体装置。
- 前記金属化合物膜は、金属窒化物膜よりなることを特徴とする請求項1又は4に記載の半導体装置。
- 前記金属化合物膜は、金属炭化物膜よりなることを特徴とする請求項1又は4に記載の半導体装置。
- 前記金属化合物膜は、金属ケイ化物膜よりなることを特徴とする請求項1又は4に記載の半導体装置。
- 基板上の絶縁膜に凹部を形成する工程と、
前記凹部の壁面に沿うように、金属酸化物膜、金属化合物膜、及び金属膜がこの順に形成されてなるバリアメタル膜を形成する工程と、
前記凹部を埋め込むように、前記バリアメタル膜の上に埋め込み金属配線を形成する工程とを備え、
前記バリアメタル膜を形成する工程は、
前記金属酸化物膜の弾性率よりも大きい弾性率を有する前記金属化合物膜を形成する工程を含むことを特徴とする半導体装置の製造方法。 - 基板上の絶縁膜に凹部を形成する工程と、
前記凹部の壁面に沿うように、第1の金属酸化物膜、金属化合物膜、第2の金属酸化物膜、及び金属膜がこの順に形成されてなるバリアメタル膜を形成する工程と、
前記凹部を埋め込むように、前記バリアメタル膜の上に埋め込み金属配線を形成する工程とを備え、
前記バリアメタル膜を形成する工程は、
前記第1の金属酸化物膜の弾性率及び前記第2の金属酸化物膜の弾性率のそれぞれよりも大きい弾性率を有する前記金属化合物膜を形成する工程を含むことを特徴とする半導体装置の製造方法。 - 前記バリアメタル膜を形成する工程よりも後であって前記埋め込み金属配線を形成する工程よりも前に、前記バリアメタル膜の上にシード層を形成する工程をさらに備え、
前記埋め込み金属配線を形成する工程は、前記凹部を埋め込むように、前記シード層の上に前記埋め込み金属配線を形成する工程を含むことを特徴とする請求項12又は13に記載の半導体装置の製造方法。
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JP2004192653A JP4224434B2 (ja) | 2004-06-30 | 2004-06-30 | 半導体装置及びその製造方法 |
EP05741631A EP1780788A1 (en) | 2004-06-30 | 2005-05-20 | Semiconductor device and method for manufacturing same |
CNB2005800212409A CN100447979C (zh) | 2004-06-30 | 2005-05-20 | 半导体装置及其制造方法 |
KR1020077001622A KR20070028574A (ko) | 2004-06-30 | 2005-05-20 | 반도체장치 및 그 제조방법 |
PCT/JP2005/009270 WO2006003760A1 (ja) | 2004-06-30 | 2005-05-20 | 半導体装置及びその製造方法 |
US11/630,799 US7663239B2 (en) | 2004-06-30 | 2005-05-20 | Semiconductor device and method for fabricating the same |
TW094122204A TW200601410A (en) | 2004-06-30 | 2005-06-30 | Semiconductor device and method for manufacturing same |
US12/649,002 US7893535B2 (en) | 2004-06-30 | 2009-12-29 | Semiconductor device and method for fabricating the same |
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JP4224434B2 true JP4224434B2 (ja) | 2009-02-12 |
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KR (1) | KR20070028574A (ja) |
CN (1) | CN100447979C (ja) |
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Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007251135A (ja) * | 2006-02-18 | 2007-09-27 | Seiko Instruments Inc | 半導体装置およびその製造方法 |
US7579274B2 (en) * | 2006-02-21 | 2009-08-25 | Alchimer | Method and compositions for direct copper plating and filing to form interconnects in the fabrication of semiconductor devices |
JP2007258390A (ja) * | 2006-03-23 | 2007-10-04 | Sony Corp | 半導体装置、および半導体装置の製造方法 |
JP4634977B2 (ja) * | 2006-08-15 | 2011-02-16 | Okiセミコンダクタ株式会社 | 半導体装置及び半導体装置の製造方法 |
US20080096381A1 (en) * | 2006-10-12 | 2008-04-24 | Han Joseph H | Atomic layer deposition process for iridium barrier layers |
JP5154789B2 (ja) | 2006-12-21 | 2013-02-27 | ルネサスエレクトロニクス株式会社 | 半導体装置並びに半導体装置の製造方法 |
JP2010192467A (ja) * | 2007-06-28 | 2010-09-02 | Tokyo Electron Ltd | 被処理体の成膜方法及び処理システム |
JP4836092B2 (ja) * | 2008-03-19 | 2011-12-14 | 国立大学法人東北大学 | 半導体装置の形成方法 |
US8679970B2 (en) * | 2008-05-21 | 2014-03-25 | International Business Machines Corporation | Structure and process for conductive contact integration |
US7928569B2 (en) * | 2008-08-14 | 2011-04-19 | International Business Machines Corporation | Redundant barrier structure for interconnect and wiring applications, design structure and method of manufacture |
US8242600B2 (en) | 2009-05-19 | 2012-08-14 | International Business Machines Corporation | Redundant metal barrier structure for interconnect applications |
EP2259307B1 (en) | 2009-06-02 | 2019-07-03 | Napra Co., Ltd. | Electronic device |
JP5190415B2 (ja) * | 2009-06-04 | 2013-04-24 | パナソニック株式会社 | 半導体装置 |
KR101656444B1 (ko) * | 2010-01-25 | 2016-09-09 | 삼성전자주식회사 | 상보형 mos 트랜지스터, 상기 상보형 mos 트랜지스터를 포함하는 반도체 장치, 및 상기 반도체 장치를 포함하는 반도체 모듈 |
US8461683B2 (en) * | 2011-04-01 | 2013-06-11 | Intel Corporation | Self-forming, self-aligned barriers for back-end interconnects and methods of making same |
US8610280B2 (en) * | 2011-09-16 | 2013-12-17 | Micron Technology, Inc. | Platinum-containing constructions, and methods of forming platinum-containing constructions |
US8592985B2 (en) | 2012-04-10 | 2013-11-26 | Micron Technology, Inc. | Methods of forming conductive structures and methods of forming DRAM cells |
US20130328098A1 (en) * | 2012-05-15 | 2013-12-12 | High Power Opto. Inc. | Buffer layer structure for light-emitting diode |
JP6061610B2 (ja) * | 2012-10-18 | 2017-01-18 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US20140273436A1 (en) * | 2013-03-15 | 2014-09-18 | Globalfoundries Inc. | Methods of forming barrier layers for conductive copper structures |
US9349636B2 (en) | 2013-09-26 | 2016-05-24 | Intel Corporation | Interconnect wires including relatively low resistivity cores |
US9418889B2 (en) * | 2014-06-30 | 2016-08-16 | Lam Research Corporation | Selective formation of dielectric barriers for metal interconnects in semiconductor devices |
JP2016219660A (ja) * | 2015-05-22 | 2016-12-22 | ソニー株式会社 | 半導体装置、製造方法、固体撮像素子、および電子機器 |
US10446439B2 (en) * | 2015-12-26 | 2019-10-15 | Intel Corporation | Low resistance interconnect |
US10504821B2 (en) * | 2016-01-29 | 2019-12-10 | United Microelectronics Corp. | Through-silicon via structure |
CN105895579B (zh) * | 2016-06-08 | 2017-12-05 | 无锡微奥科技有限公司 | 一种基于soi衬底的tsv圆片的加工方法 |
US10741442B2 (en) * | 2018-05-31 | 2020-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier layer formation for conductive feature |
JP2022029308A (ja) * | 2020-08-04 | 2022-02-17 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
US20220246534A1 (en) * | 2021-01-29 | 2022-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-resistance copper interconnects |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3337876B2 (ja) | 1994-06-21 | 2002-10-28 | 株式会社東芝 | 半導体装置の製造方法 |
JP3409831B2 (ja) | 1997-02-14 | 2003-05-26 | 日本電信電話株式会社 | 半導体装置の配線構造の製造方法 |
US6069068A (en) * | 1997-05-30 | 2000-05-30 | International Business Machines Corporation | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity |
JPH11223755A (ja) | 1998-02-09 | 1999-08-17 | Asahi Optical Co Ltd | レンズ保持構造 |
JP3149846B2 (ja) * | 1998-04-17 | 2001-03-26 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JP2000049116A (ja) * | 1998-07-30 | 2000-02-18 | Toshiba Corp | 半導体装置及びその製造方法 |
JP3528665B2 (ja) | 1998-10-20 | 2004-05-17 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP2000208443A (ja) | 1999-01-13 | 2000-07-28 | Sony Corp | 電子装置の製造方法および製造装置 |
JP4377040B2 (ja) | 2000-07-24 | 2009-12-02 | Necエレクトロニクス株式会社 | 半導体の製造方法 |
JP2002075994A (ja) | 2000-08-24 | 2002-03-15 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
CN1248294C (zh) * | 2000-11-22 | 2006-03-29 | 联华电子股份有限公司 | 形成阻挡层的方法及形成的结构 |
US6462417B1 (en) * | 2000-12-18 | 2002-10-08 | Advanced Micro Devices, Inc. | Coherent alloy diffusion barrier for integrated circuit interconnects |
US6433379B1 (en) * | 2001-02-06 | 2002-08-13 | Advanced Micro Devices, Inc. | Tantalum anodization for in-laid copper metallization capacitor |
JP2002343859A (ja) * | 2001-05-15 | 2002-11-29 | Mitsubishi Electric Corp | 配線間の接続構造及びその製造方法 |
JP3540302B2 (ja) * | 2001-10-19 | 2004-07-07 | Necエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US6713373B1 (en) * | 2002-02-05 | 2004-03-30 | Novellus Systems, Inc. | Method for obtaining adhesion for device manufacture |
JP2003332426A (ja) | 2002-05-17 | 2003-11-21 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
JP2004031497A (ja) * | 2002-06-24 | 2004-01-29 | Nec Corp | 半導体装置およびその製造方法 |
JP2004031866A (ja) * | 2002-06-28 | 2004-01-29 | Trecenti Technologies Inc | 半導体集積回路装置 |
US7279423B2 (en) * | 2002-10-31 | 2007-10-09 | Intel Corporation | Forming a copper diffusion barrier |
US7045071B2 (en) * | 2002-12-30 | 2006-05-16 | Hynix Semiconductor Inc. | Method for fabricating ferroelectric random access memory device |
JP2004040128A (ja) * | 2003-08-29 | 2004-02-05 | Ulvac Japan Ltd | 化学蒸着法による銅薄膜の形成方法 |
US20050206000A1 (en) * | 2004-03-19 | 2005-09-22 | Sanjeev Aggarwal | Barrier for copper integrated circuits |
FR2879064B1 (fr) * | 2004-12-03 | 2007-06-01 | Eastman Kodak Co | Procede de diffusion de donnees multimedia vers un equipement pourvu d'un capteur d'images |
KR100613388B1 (ko) * | 2004-12-23 | 2006-08-17 | 동부일렉트로닉스 주식회사 | 다마신법을 이용한 구리 배선층을 갖는 반도체 소자 및 그형성 방법 |
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Publication number | Publication date |
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CN1973367A (zh) | 2007-05-30 |
EP1780788A1 (en) | 2007-05-02 |
CN100447979C (zh) | 2008-12-31 |
US7893535B2 (en) | 2011-02-22 |
US20080054464A1 (en) | 2008-03-06 |
WO2006003760A1 (ja) | 2006-01-12 |
KR20070028574A (ko) | 2007-03-12 |
JP2006019325A (ja) | 2006-01-19 |
TW200601410A (en) | 2006-01-01 |
US7663239B2 (en) | 2010-02-16 |
US20100102449A1 (en) | 2010-04-29 |
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