JP4065550B2 - Image input / output control device, image processing device, image processing method in image input / output control device, and image processing method in image processing device - Google Patents

Description

  The present invention relates to an image processing apparatus and an image processing method.

  There is known a digital multi-function peripheral having various functions such as a scanner function, a printer function, a copying function, and a network function. The functional operation in the digital multifunction peripheral is usually controlled by an image input / output control device called a controller.

  In recent years, with the improvement in performance of digital multifunction peripherals, an image input / output control apparatus capable of efficiently processing a large amount of data is desired, and a single semiconductor as disclosed in Japanese Patent Application Laid-Open No. 11-45225 is desired. A controller of a composite device configured on a substrate has been proposed. There has also been proposed a controller for a composite device in which a plurality of image processing units are connected to a single shared bus represented by a PCI bus.

  However, if the processing capability is insufficient, even if the processing function is added or changed, the controller of the above-described composite device has an image processing unit, a system control unit, and the like on a single semiconductor substrate. There arises a problem that the configuration cannot be easily changed.

  Also, even a controller with a PCI bus is configured to pass image data through a shared bus, so even if the number of processing units is added to increase processing capacity, a single bus limits system performance. There is a problem of end up.

  Further, an advanced bus control function may be provided so that the performance of the system is not limited. However, in this case, there is a problem that the number of components increases and the price of the device increases.

  For example, when the scanning operation and the printing operation are performed at the same time, even if the apparatus has a plurality of image processing units, the processing is concentrated on one image processing unit, and contention of the image processing units may occur. The problem that there is.

  SUMMARY An advantage of some aspects of the invention is that it provides an image processing apparatus and an image processing method capable of easily controlling image processing in an image processing unit.

  It is another object of the present invention to provide an image input / output control apparatus capable of executing an image input / output operation using an image memory without causing contention between an image processing unit and a bus.

  In order to achieve the above object, an image processing apparatus according to the present invention comprises: divided image data generating means for dividing the input image data to generate divided image data; and compression means for compressing the divided image data. Packet data generating means for generating packet data by adding processing information relating to image processing to be performed on the divided image data compressed by the compression means to the compressed divided image data; and the packet data And an image processing unit that performs image processing on the divided image data expanded by the expansion unit based on the processing information added to the packet data. And a processing means.

  In order to achieve the above object, an image processing method according to the present invention includes a divided image data generation step for generating divided image data by dividing the input image data, and a compression for compressing the divided image data. A packet data generating step for generating packet data by adding processing information relating to image processing to be performed on the divided image data compressed by the compression step to the compressed divided image data; and the packet data A decompression step for decompressing the compressed divided image data included in the image, and an image for performing image processing on the divided image data decompressed by the decompression step based on the processing information added to the packet data And a processing step.

  As described above, according to the present invention, it is possible to provide an image processing apparatus and an image processing method capable of easily controlling image processing in the image processing unit.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 shows a digital multi-function peripheral according to the first embodiment. Reference numeral 2000 denotes a controller (controller unit) to which the image input / output control apparatus and image processing apparatus of the present invention can be applied.

  Here, reference numeral 2150 denotes a system control unit that controls the entire digital multi-function peripheral. Reference numerals 2149 and 2151 denote image processing units that perform predetermined image processing on the input image data, and details thereof will be described later. An image ring 2008 connects the system processing unit 2150, the image processing unit 2149, and the image processing unit 2151 in a ring shape.

  An operation unit 2012 is used to perform various settings and operation instruction operations. Reference numeral 2002 denotes a RAM, and reference numeral 2003 denotes a ROM. 2143 is a general-purpose PCI bus, 2004 is an external storage device, and 2144 is a disk controller. Reference numeral 2050 denotes a modem for connecting to a public line, and 2146 denotes a PHY / PMD, which is connected to the LAN 2011. The digital multi-function peripheral can communicate with an external device via the modem 2050 and the PHY / PMD. A printer 2095 and image memories 1 and 2 (2123) are connected to the image processing unit 1 (2149). A scanner 2070 and second image memories 1 and 2 are connected to the image processing unit 2 (2151).

  Here, the configuration of the controller 2000 from the viewpoint of hardware will be described.

  Conventionally, a controller in an image input / output device such as a digital copying machine is configured as a system LSI on a semiconductor substrate. In particular, in recent years, according to this embodiment, circuits for realizing the functions of the system control unit 2150, the image processing unit 1 (2149), the image processing unit 2 (2151), and the like are configured on one semiconductor substrate. A controller has been proposed.

  However, unlike the prior art, in this embodiment, circuits for realizing each function are configured on different units, that is, semiconductor substrates, so as to cope with a change in the function of the apparatus.

  More specifically, the system control unit 2150 is configured on one semiconductor substrate, and the image processing unit 1 (2149) and the image processing unit 2 (2151) are each configured on one semiconductor substrate.

  The semiconductor substrate described here can be called an IC chip. That is, in this embodiment, the controller 2000 is one printed circuit board, and the system control unit 2150, the image processing unit 1 (2149), and the image processing unit 2 (2151) are mounted on the printed circuit board as IC chips. Yes.

  The present invention is not limited to this. For example, the system control unit 2150, the image processing unit 1 (2149), and the image processing unit 2 (2151) are mounted as IC chips on separate printed circuit boards. Also good.

  Next, FIG. 2 shows a detailed overall configuration for explaining the internal configurations of the system control unit 2150 and the image processing unit 1 (2149). 2 shows only the internal configuration of the image processing unit 1 (2149), the image processing unit 2 (2151) is assumed to have the same configuration as the image processing unit 1 (2149). The description will be made using the same reference numerals unless otherwise specified.

  The controller 2000 is connected to a scanner 2070 that is an image input device and a printer 2095 that is an image output device. On the other hand, the controller 2000 is connected to a LAN 2011 or a public line WAN 2051 to input / output image information and device information and develop an image of PDL data. It is a controller for performing.

  A CPU 2001 is a processor that controls the entire system. In this embodiment, an example using two CPUs is shown. These two CPUs are connected to a common CPU bus 2126 and further connected to a system bus bridge 2007.

  The system bus bridge 2007 is a bus switch, and includes a CPU bus 2126, a RAM controller 2124, a ROM controller 2125, an IO bus 1 (2127), an IO bus 2 (2129), an image ring interface 1 (2147), and an image ring interface 2 ( 2148) is connected.

  A RAM 2002 is a system work memory for operating the CPU 2001, and is also an image memory for temporarily storing image data. The RAM 2002 is controlled by the RAM controller 2124.

  A ROM 2003 is a boot ROM, and stores a system boot program. It is controlled by the ROM controller 2125.

  The IO bus 1 (2127) is a kind of internal IO bus, and is connected to a standard USB bus controller, a USB interface 2138, a general-purpose serial port 2139, an interrupt controller 2140, and a GPIO interface 2141. The IO bus 1 (2127) includes a bus arbiter (not shown).

  An operation unit I / F 2006 is an interface unit with the operation unit UI 2012 and outputs image data to be displayed on the operation unit 2016 to the operation unit 2012. Also, it plays a role of transmitting information input by the user of the system from the operation unit 2012 to the CPU 2001.

  The IO bus 2 (2129) is a kind of internal IO bus, to which the general-purpose bus interfaces 1 and 2 (2142) and the LAN controller 2010 are connected. The IO bus 2 (2142) includes a bus arbiter (not shown).

  General-purpose bus interfaces 1 and 2 (2142) are bus bridges that are composed of two identical bus interfaces and support a standard IO bus. In the present embodiment, an example in which the PCI bus (2143) is employed has been described.

  An HDD 2004 is a hard disk drive that stores system software and image data. It is connected to one PCI bus 2143 via the disk controller 2144.

  The LAN controller 2010 is connected to the LAN 2011 via the MAC circuit 2145 and the PHY / PMD circuit 2146 to input / output information. A Modem 2050 is connected to the public line 2051 and inputs / outputs information.

  The image ring interface 1 (2147) and the image ring interface 2 (2148), which are packet transfer means, connect the system bus bridge 2007 and the image ring 2008 that transfers image data at high speed, and the tiled data is transferred to the RAM 2002 and the image. It is a DMA controller that transfers data between processing units 2149.

  The image ring 2008, which is also a packet transfer means, is configured by a combination of a series of unidirectional connection paths. The image ring 2008 is connected to the command processing unit 2104, the status processing unit 2105, and the tile bus 2127 through the image ring interface 3 (2101) and the image ring interface 4 (2102) in the image processing unit 1 (2149). The

  The command processing unit 2104 is connected to the register setting bus 2109 in addition to the connection to the image ring interface. The command processing unit 2104 receives a register setting request issued from the CPU 2001 input via the image ring, and the corresponding block connected to the register setting bus 2109. Write to.

  Also, based on the register read request issued by the CPU 2001, information is read from the corresponding register via the register setting bus and transferred to the image ring interface 4 (2102).

  The status processing unit 2105 monitors information of each image processing unit, generates an interrupt bucket for issuing an interrupt to the CPU 2001, and outputs it to the image ring interface 4 (2102).

  In addition to the above blocks, the tile bus 2107 is connected to functional blocks such as an image input interface 2112, an image output interface 2113, and a plurality of rectangular image processing units 2116 to 2119, 2030.

  In this embodiment, a multi-value conversion unit 2119, a binarization unit 2118, a color space conversion unit 2117, an image rotation unit 2030, and a resolution conversion unit 2116 are mounted as rectangular image processing units.

  In FIG. 1, the scanner 2070 that should be in the image processing unit 2 (2151) is described here as being connected to the image processing unit 1 (2149) in order to simplify the drawing.

  An image input interface 2112 in the image processing unit 2 (2151) receives raster image data corrected by a scanner 2170, which will be described later, as input, and converts it into rectangular data by a predetermined method set via a register setting bus. The structure conversion and clock synchronization are performed, and output to the tile bus 2107 is performed.

  The image output interface (2113) in the image processing unit 1 (2149) receives rectangular data from the tile bus 2107, converts the structure into a raster image, changes the clock rate, and outputs the raster image to the printer 2095. To do.

  The image input interface of the image processing unit 1 (2149) and the image output interface of the image processing unit 2 (2151) are not used in this embodiment.

  The image rotation unit 2030 rotates image data. A resolution conversion unit 2116 changes the resolution of the image. A color space conversion unit 2117 performs color space conversion of color and grayscale images. A binarization unit 2118 binarizes the multi-value color and gray scale image. A multi-value conversion unit 2119 converts a binary image into multi-value data.

  The memory control unit 2122 is connected to the memory bus 2108, and writes and reads image data to and from the image memory 1 and the image memory 2 (2123) by address division set in advance according to the request of each image processing unit. An operation such as refresh is performed as necessary. In the present embodiment, an SDRAM is used as the image memory.

  Next, FIG. 3 shows a configuration diagram of the entire network system including the digital multifunction peripheral according to the present embodiment.

  Reference numeral 1001 denotes a digital multi-function peripheral according to the above-described embodiment, which is controlled by a controller to which the image output control apparatus and the image processing apparatus of the present invention can be applied.

  The digital multi-function peripheral 1001 includes a scanner and a printer. The digital multifunction peripheral 1001 can flow an image read from the scanner to a local area network 1010 (hereinafter referred to as LAN), and can print out an image received from the LAN by a printer.

  Further, the image read from the scanner can be transmitted to the PSTN or ISDN 1030 by a FAX transmission means (not shown), and the image received from the PSTN or ISDN can be printed out by the printer. Reference numeral 1002 denotes a database server that manages binary images and multi-valued images read by the digital multifunction peripheral 1001 as a database.

  Reference numeral 1003 denotes a database client of the database server 1002 that can browse / search image data stored in the database 1002.

  An e-mail server 1004 can receive an image read by the digital multifunction peripheral 1001 as an e-mail attachment. Reference numeral 1005 denotes an e-mail client which can receive and browse mail received by the e-mail server 1004 and transmit e-mail.

  Reference numeral 1006 denotes a WWW server that provides an HTML document to the LAN, and the digital multifunction peripheral 1001 can print out the HTML document provided by the WWW server.

  Reference numeral 1011 denotes a router that connects the LAN 1010 to the Internet / intranet 1012. Devices similar to the database server 1002, WWW server 1006, e-mail server 1004, and digital multifunction peripheral 1001 described above are connected to the Internet / intranet as 1020, 1021, 1022, and 1023, respectively. On the other hand, the digital multifunction peripheral 1001 can transmit and receive with the FAX apparatus 1031 via the PSTN or ISDN 1030.

  A printer 1040 is also connected on the LAN, and is configured to print out an image read by the digital multifunction peripheral 1001.

  Next, a packet format of packet data processed in the controller 2000 to which the image input / output control device and the image processing device of the present invention can be applied will be described.

  In the controller 2000 in the present embodiment, image data, commands from the CPU 2001, interrupt information issued from each block, and the like are transferred in a packetized form. In the present embodiment, three different types of packets are used: a data packet shown in FIG. 4, a command packet shown in FIG. 6, and an interrupt packet shown in FIG.

  First, the data packet will be described with reference to FIG. In the present embodiment, an example is shown in which image data is divided into image data (ImageData + padding) 3002 in units of tiles (Tile) of 32 pixels x 32 pixels.

  Necessary header information (header) 3001 and additional image information (Zdata + padding) 3003 are added to the tile unit image to form a data packet (DataPacket). Information included in the header information 3001 will be described below.

  The packet type is distinguished by a packet type (PcktType) 3004 in the header information 3001. A chip ID (ChipID) 3005 indicates the ID of a target chip that transmits a packet. A data type (DataType) 3006 indicates the type of data. A page ID (PageID) 3007 indicates a page, and a job ID (JobID) 3008 stores an ID for management by software.

  The tile number is a combination of a tile coordinate 3009 in the Y direction and a tile coordinate 3010 in the X direction, and is represented by YnXn. Data packets may be compressed or uncompressed. In this embodiment, the case of non-compression is shown. A distinction between the case of compression and the case of non-compression is indicated by a compression flag (CompressFlag) 3017.

  A process instruction (Process Instruction) 3011 is left-justified and set in processing order, and each processing unit (the above-described rectangular image processing unit or the like) shifts the processed process instruction 3011 to the left by 8 bits. The process instruction 3011 stores eight sets of a unit ID (Unit ID) 3019 and a mode (Mode) 3020. A unit ID 3019 designates each processing unit, and a mode 3020 designates an operation mode in each processing unit. Thereby, one packet can be processed continuously by eight units.

  A packet length (PacketByteLength) 3012 indicates the total number of bytes of the packet. An image data length (ImageDataByteLength) 3015 represents the number of bytes of image data, a Z data length (ZdataByteLength) 3016 represents the number of bytes of image additional information, and an image data offset (ImageDataOffset) 3013 and a Z data offset (ZdataOffset) 3014 It represents the offset from the beginning of the data packet.

  Next, the packet table (Packet Table) will be described with reference to FIG. Each packet is managed by a packet table 6001. The components of the packet table 6001 are as follows. When 0 bits are added to the table value, 5 bits are added to the packet start address (PacketAddressPointer) 6002 and the packet length (ByteLength) 6005. Further, here, the following relationship holds: Packet Address Pointer 27 bits + 5b00000 = packet head address, Packet Length 11 bits + 5b00000 = packet length. The packet table 6001 and the chain table (ChainTable) 6010 are not divided.

  The packet table 6001 is always arranged in the scanning direction, and Yn / Xn = 000 / 000,000 / 001,000 / 002,. . . . It is lined up in this order. The E entry of the packet table 6001 uniquely indicates one tile. The entry next to Yn / Xmax is Yn + 1 / X0.

  When the packet is exactly the same data as the previous packet, the packet is not written in the memory, and the same start address (PacketAddressPointer) and packet length (PacketLength) as the first entry are stored in the packet table entry. . One packet data is indicated by two table entries. In this case, the repeat flag (RepeatFlag) 6003 of the second table entry is set.

  When a packet is divided into a plurality of parts by chain DMA, a division flag (DivideFlag) 6004 is set, and a chain table number (ChainTableNo) 6006 of a chain block containing the head portion of the packet is set.

  An entry of the chain table 6010 is composed of a chain block address (ChainBlock Address) 6011 and a chain block length (ChainBlock Length) 6012, and 0 is stored in both the address and data length in the last entry of the table.

  Next, a command packet (Command Packet) will be described with reference to FIG.

  The command packet is for accessing the register setting bus 2109. By using a command packet, the CPU 2001 can also access the image memory 2123.

  A chip ID (ChipID) 4004 stores an ID representing an image processing unit that is a transmission destination of the command packet. A page ID (Page ID) 4007 and a job ID (Job ID) 4008 store a page ID and a job ID for management by software.

  A packet ID (PacketID) 4009 is represented in one dimension. Accordingly, only the X coordinate (X-coordinate) 4009 of the data packet (Data Packet) is used. The packet length (Packet Byte Length) 4010 is fixed to 128 bytes.

  The packet data part (Command) 4002 can store a maximum of 12 commands, with a set of an address (Address) 4011 and data (Data) 4012 as one command. The command type (write or read) is indicated by a command type (CmdType) 4005, and the number of commands is indicated by a command number (Cmdnum) 4006.

  Finally, an interrupt packet will be described with reference to FIG.

  The interrupt packet is for notifying an interruption from the image processing unit to the CPU 2001. When the status processing unit 2105 transmits an interrupt packet, the status processing unit 2105 must not transmit the interrupt packet until the next transmission is permitted.

  The packet length (PacketByteLength) 5006 is fixed to 128 bytes. The packet data part (IntData) 5002 stores status information (Module Status) 5007 of each internal module (each rectangular image processing part, input / output interface, etc.) of the image processing part. The status processing unit 2105 can collect status information of each module in the image processing unit and send it to the system control unit 2150 in a batch.

  The chip ID (ChipID) 5004 stores an ID that represents the system control unit 2150 that is the destination of the interrupt packet, and the interrupt chip ID (IntChipID) 5005 stores an ID that represents the image processing unit that is the source of the interrupt. The

  Hereinafter, as a typical process performed by the controller 2000, a process when a user instructs a copy job from the operation unit 2012 will be described with reference to flowcharts illustrated in FIGS.

  First, processing from when the controller 2000 receives a copy job until the scanning operation using the scanner 2070 starts and ends will be described with reference to FIG.

  The CPU 2001 receives information transmitted from the operation unit interface 2006, and programs necessary information such as the number of transfer packets and an image storage address on the RAM 2002 into the image ring interface 2 (2148) based on information such as the paper size (S801). ).

  The CPU 2001 programs a command packet generation register in the image ring interface 1 (2147) via the register access ring 2137, and sets a necessary information such as paper size and color space information to the image input interface 2112. Generate a packet. In this case, the chip ID 4004 of the command packet is set to “2” indicating the image processing unit 2 (2151) (S802).

  Thereafter, the image ring interface 1 (2147) transfers the command packet to the image processing unit 1 (2149) via the image ring 2008 (S803).

  The image ring interface 3 (2101) of the image processing unit 1 (2149) inspects the chip ID of the command packet. Here, since the chip ID is not “1” which is the ID of the own chip, the command packet is transferred to the image ring interface 4 (2102) (S804).

  The image ring interface 4 (2102) again transfers the command packet to the image processing unit 2 (2151) via the image ring 2008 (S805).

  For the command packet that has reached the image processing unit 2 (2151), the chip ID of the command packet is inspected by the image ring interface 3 (2101) in the image processing unit 2. Here, the chip ID of the command packet and the ID of the own chip match with “2”. In this case, the command processing unit (2104) programs the image input interface 2112 via the register setting bus (2109) based on the command data and header information of the command packet (S806).

  Subsequently, similarly, the CPU 2001 uses the command packet to program the scanner communication interface in the image input interface 2112 and instructs the scanner 2070 to start scanning (S807).

  The image information input from the scanner 2070 is temporarily stored in the image memory 2123 controlled by the memory control unit 2122 via the image input interface 2112 and the memory bus 2108 (S808).

  The stored image data is read again every 32 × 32 pixels by the image input interface 2112, and includes packet type (PcktType) 3004, chip ID (ChipID) 3005, data type (DataType) 3006, and page ID (PageID). 3007, job ID (Job ID) 3008, tile coordinates in the Y direction (PacketIDYcoordinate) 3009, tile coordinates in the X direction (PacketIDXcoordinate) 3010, compression flag (Compression Flag) 3017, process instruction (Process Instruction) 3011, packet data length (Processing Instruction) 3011 Header information such as (PacketBy length) 3012 is added to the image data to To generate a Tsu door, and outputs the generated data packet to the tile bus 2107 (S809).

  The data packets are sequentially generated and transferred to the image ring interface 2 (2148) via the image ring interface 4 (2102), the image ring 2008, and the image ring interface 2 (2148) based on the chip ID, similarly to the command packet. . Based on the information programmed in the image ring interface 2 (2148), it is sequentially stored in the RAM 2002. At the same time, the image ring interface 2 (2148) creates the packet table 6001 on the RAM 2002 (S810).

  When the scanning operation for one page is completed, the completion is transmitted to the image input interface using the scanner communication means. The image input interface 2112 notifies an interrupt to the status processing unit 2105 using an interrupt signal (not shown) (S811).

  The status processing unit 2105 in the image processing unit 2 (2151) creates an interrupt packet (FIG. 7) and transfers it to the image ring interface 2 (2148) (S812).

  The image ring interface 2148 interprets the interrupt packet and transmits the interrupt to the interrupt controller 2140 by an interrupt signal (not shown). The interrupt is transmitted from the interrupt controller 2140 to the CPU 2001, and the CPU 2001 detects the end of the scanning operation (S813).

  When the scanning operation is finished, a printing operation using the printer 2095 is started. Processing of the controller 2000 in the printing operation will be described with reference to FIG.

  The CPU 2001 creates a command packet having the chip ID “1” via the register access ring 2137 (S901).

  Then, the created command packet is transferred from the image ring interface 1 (2147) to the image processing unit 1 (2149) via the image ring 2008 (S902).

  The image ring interface 3 (2101) of the image processing unit 1 (2149) inspects the input command packet. Here, since the chip ID is “1”, an image is sent to the image output interface (2113) in the image processing unit 1 (2149) via the command processing unit 2104 and the register setting bus 2109 based on the command data of the command packet. Necessary information for output processing is set (S903).

  Similarly, the CPU 2001 uses the command packet to instruct the printer 2095 to wait for printing by the printer communication means provided in the image output interface 2113 in the image processing unit 1 (S904).

  Subsequently, the CPU 2001 programs a memory address or the like where the packet table exists in the DMA means provided in the image ring interface 1 (2147) (S905).

  Based on the programmed information, the DMA in the image ring interface 1 (2147) reads the data packet from the RAM 2002 and generates a data packet with the chip ID “1” added to the header (S906).

  Then, the DMA in the image ring interface 1 (2147) transfers the generated data packet to the image processing unit 1 (2149) via the image ring 2008 (S907).

  The image ring interface 3 (2101) of the image processing unit 1 (2149) inspects the input data packet. Here, since the chip ID is “1”, the chip ID is sequentially transferred to the image output interface 2113 via the image ring interface 3 (2101) and the tile bus (2107) (S908).

  The image output interface 2113 extracts an image portion from the received data packet and stores the image data in the image memory 2123 (S909).

  When the image data for the necessary pixels is accumulated in the image memory 2123, the image output interface 2113 sequentially reads the image data from the image memory 2123 and outputs it to the printer 2095 (S910).

  As a result, the user obtains an image print that is a copy result. When the required number of pixels have been output, an end interrupt is transmitted to the CPU 2001 by an interrupt packet as in the case of the scan operation (S911).

  In the foregoing, the scanning operation using the scanner 2070 and the image processing unit 2 (2151) and the copying operation combining the printing operation using the printer 2095 and the image processing unit 1 (2095) have been described.

  As is clear from this description, in the case of multi-page copying, a print operation and a scan operation occur simultaneously, but in the image ring 2008, the scan data packet and the print data packet do not pass through the same bus.

  The image ring 2008 is constituted by a combination of unidirectional connection paths, and can constitute a low-cost transfer means without causing a reduction in processing speed due to bus contention or the like.

  In addition, the rectangular image processing units such as the resolution conversion unit 2116 and the image rotation 2030 are used in the scanning operation and the printing operation, and the processing of the image data in the scanning operation and the processing of the image data in the printing operation conflict. There is.

  However, by adopting the configuration of the controller in the present embodiment, the resolution conversion unit and the image rotation unit of each of the image processing unit 1 and the image processing unit 2 can be used even in the case of contention, and speed reduction due to contention does not occur.

  As described above, according to the present embodiment, in the controller of the digital multi-function peripheral, the semiconductor substrate that constitutes the system control unit, the semiconductor substrate that constitutes the image processing unit 1, and the image processing unit 2 are configured. The semiconductor substrates were separated from each other, and each was connected by an image ring to perform data transfer by packet data.

  Thereby, even when a change or addition of a function occurs, the configuration of the controller can be easily changed. In addition, since unidirectional data transfer is performed by the image ring, it is possible to reduce a decrease in processing speed due to bus contention without increasing the number of parts for bus control or the like.

  In addition, in the exchange of commands between the above-mentioned system control unit connected in a ring shape and each image processing unit, image processing and image input / output processing in each image processing unit, operation processing setting of the connected external device A command packet in which a header including a chip ID for identifying which image processing unit performs processing setting is added to command data for performing the above and the like is used.

  As a result, the system control unit can easily perform separate processing settings for each image processing unit, and thus avoids contention of the image processing unit in parallel processing or the like without increasing the load on the system control unit. be able to.

  The image processing unit 2 transmits the image data input by the scanner to the system control unit based on the setting by the command packet, and the system control unit stores the image data received from the image processing unit 2 in the RAM. After the image data for the page is stored in the RAM, the image data in the RAM is transmitted to the image processing unit 1, and the image processing unit 1 outputs the image data received from the system control unit to the printer based on the setting by the command packet. I tried to do it.

  By performing this data transfer process using an image ring that is a unidirectional bus, copy processing can be performed without causing a decrease in processing speed due to competition between the image processing unit and the bus.

  Similarly, in the exchange of image data between the above-described system controller connected in a ring shape and each image processing unit, in which image processing unit the image data divided into rectangular units having a predetermined size is used. A command packet to which a header including a chip ID for identifying whether to perform processing setting is added is used.

  As a result, it is possible to specify an image processing unit that performs image processing in units of rectangular image data, and to avoid contention for image processing using the rectangular image processing unit in the image processing unit when performing a multi-function operation. Can do.

(Second Embodiment)
In the present embodiment, another image processing unit is added to the controller described in the first embodiment. FIG. 10 shows a digital multifunction peripheral according to this embodiment.

  As shown in FIG. 10, in this embodiment, an image processing unit 3 (2152) is newly added. Here, as in the first embodiment, the system control unit 2150 is configured on one semiconductor substrate, and the image processing unit 1 (2149), the image processing unit 2 (2151), and the image processing unit 3 (2152). Are configured on one semiconductor substrate.

  In the digital multi-function peripheral shown in FIG. 10, reference numeral 2000 denotes a controller (controller unit) to which the image input / output control device and the image processing device of the present invention can be applied. Here, reference numeral 2150 denotes a system control unit that controls the entire digital multi-function peripheral.

  Reference numerals 2149, 2151, and 2152 denote image processing units that perform predetermined image processing on input image data, and details thereof will be described later. An image ring 2008 connects the system processing unit 2150 and the image processing units 2149, 2151 and 2152 in a ring shape.

  Next, FIG. 11 shows a detailed overall configuration for explaining the internal configuration of the image processing unit 1 (2149).

  The image ring 2008 which is a packet transfer means is configured by a combination of a series of unidirectional connection paths. The image ring 2008 is connected to the command processing unit 2104, the status processing unit 2105, and the tile bus 2107 through the image ring interface 3 (2101) and the image ring interface 4 (2102) in the image processing unit 2149.

  In addition to the above blocks, an image output interface 2113 is connected to the tile bus 2107.

  An image output interface 2113 in the image processing unit 1 (2149) receives rectangular data from the tile bus 2107, converts the structure into a raster image and changes the clock rate, and outputs the raster image to the printer 2195. The memory control unit 2122 is connected to the memory bus 2108, and performs operations such as writing and reading image data to the image memory 1 (2113) and refreshing as necessary according to a request from the image output interface 2113. In this embodiment, an example in which an SDRAM is used as the image memory has been described.

  Next, FIG. 12 shows a detailed overall configuration for explaining the internal configuration of the image processing unit 2 (2151).

  The image ring 2008 which is a packet transfer means is configured by a combination of a series of unidirectional connection paths. The image ring 2008 is connected to the command processing unit 2104, the status processing unit 2105, and the tile bus 2107 via the image ring interface 3 (2101) and the image ring interface 4 (2102) in the image processing unit 2 (2151). The This configuration is equivalent to the image processing unit 1 (2149).

  In addition to the above blocks, an image input interface 2112 is connected to the tile bus 2107.

  An image input interface 2112 in the image processing unit 2 (2151) receives raster data from the scanner 2070 as input, converts the structure into a rectangular image, changes the clock rate, and outputs the rectangular image to the tile bus 2107.

  The memory control unit 2122 is connected to the memory bus 2108, and performs operations such as writing and reading image data to the image memory 1 (2123) and refreshing as necessary according to a request from the image input interface 2112. In this embodiment, an example in which an SDRAM is used as the image memory has been described.

  Next, a detailed overall configuration for explaining the internal configuration of the image processing unit 3 (2152) is shown in FIG.

  The image ring 2008 which is a packet transfer means is configured by a combination of a series of unidirectional connection paths. The image ring 2008 is connected to the command processing unit 2104, the status processing unit 2105, and the tile bus 2107 through the image ring interface 3 (2101) and the image ring interface 4 (2102) in the image processing unit 3 (2152). The This configuration is equivalent to the image processing units 1 and 2.

  In addition to the above blocks, a resolution converter 2116 is connected to the tile bus 2107.

  The resolution conversion unit 2116 receives the image packet data input from the image ring 2008 via the tile bus 2107, converts the rectangular data into raster data using the image memory 2123 via the memory bus 2108, performs resolution conversion, The generated image data is converted into rectangular data again using the memory bus 2108 and the image memory 2123. Thereafter, the rectangular data is output to the image ring interface 4 (2102) via the tile bus 2107. The image ring interface 4 (2102) sends the rectangular data to the image ring 2008 as image packet data.

  Hereinafter, a typical process performed by the controller 2000 will be described with reference to flowcharts shown in FIGS. 14, 15, and 16 by taking, as an example, a process performed when a user instructs a scaling copy job from the operation unit 2012.

  First, the process until the controller 2000 receives a copy job, starts a scanning operation using the scanner 2070, converts the resolution of the scanned image, and stores the resolution-converted scanned image in the RAM 2002 is shown in FIGS. It explains using.

  The CPU 2001 receives information transmitted from the operation unit interface 2006, and programs necessary information such as the number of transfer packets and an image storage address on the RAM 2002 in the image ring interface 2 (2148) based on information such as the paper size (S1401). ).

  The CPU 2001 programs the command packet generation register in the image ring interface 1 (2147) via the register access ring 2137, and sets the necessary information such as paper size and color space information in the image input interface 2112. Generate a packet. In this case, the chip ID 4004 of the command packet is set to “2” indicating the image processing unit 2 (2151) (S1402).

  Thereafter, the image ring interface 1 (2147) transfers the command packet to the image processing unit 1 (2149) via the image ring 2008 (S1403).

  The image ring interface 3 (2101) of the image processing unit 1 (2149) inspects the chip ID of the command packet, and since it is not “1” which is the ID of its own chip, it sends the command packet to the image ring interface 4 (2102). Transfer (S1404).

  Since the chip ID also differs in the image ring interface 4 (2102), the image ring interface 4 (2102) again transfers the command packet to the image processing unit 2 (2151) via the image ring 2008 (S1405).

  For the command packet that has reached the image processing unit 2 (2151), the chip ID of the command packet is inspected by the image ring interface 3 (2101) in the image processing unit 2. Here, the chip ID of the command packet and the ID of the own chip match with “2”. In this case, the command processing unit 2104 programs the image input interface 2112 via the register setting bus 2109 based on the command data and header information of the command packet (S1406).

  Subsequently, the CPU 2001 receives information from the operation unit interface 2006, calculates the scaling resolution, and programs resolution conversion information such as conversion resolution in the image ring interface 2 (2148) (S1407).

  The CPU 2001 programs a command packet generation register in the image ring interface 1 (2147) via the register access ring 2137, and sets a conversion resolution in the resolution conversion unit 2116 of the image processing unit 3 (2151). Is generated. In this case, the chip ID 4004 of the command packet is set to “3” indicating the image processing unit 3 (2151) (S1408).

  Thereafter, the image ring interface 1 (2147) transfers the command packet to the image processing unit 1 (2149) via the image ring 2008 (S1409).

  The image ring interface 3 (2101) of the image processing unit 1 (2149) inspects the chip ID of the command packet, and since it is not “1” which is the ID of its own chip, it sends the command packet to the image ring interface 4 (2102). Transfer (S1410).

  Since the chip ID is also different in the image ring interface 4 (2102) of the image processing unit 1 (2149), the image ring interface 4 (2102) again sends a command packet to the image processing unit 2 (2151) via the image ring 2008. (S1411).

  The image ring interface 3 (2101) of the image processing unit 2 (2149) inspects the chip ID of the command packet, and since it is not “2” which is the ID of its own chip, the command packet is sent to the image ring interface 4 (2102). Transfer (S1412). Since the chip ID is also different in the image ring interface 4 (2102) of the image processing unit 2 (2151), the image ring interface 4 (2102) again sends a command packet to the image processing unit 3 (2152) via the image ring 2008. (S1413).

  The command packet that has reached the image processing unit 3 (2152) is inspected for the chip ID of the command packet by the image ring interface 3 (2101) in the image processing unit 3. Here, the chip ID of the command packet and the ID of the own chip match with “3”. In this case, the command processing unit (2104) programs the resolution conversion unit 2116 via the register setting bus (2109) based on the command data and header information of the command packet (S1414).

  Subsequently, similarly, the CPU 2001 uses the command packet to program the scanner communication interface in the image input interface 2112 and instructs the scanner 2070 to start scanning (S1415).

  The image information input from the scanner 2070 is temporarily stored in the image memory 2123 controlled by the memory control unit 2122 via the image input interface 2112 and the memory bus 2108 (S1416).

  The stored image data is read again every 32 × 32 pixels by the image input interface 2112, and includes packet type (PcktType) 3004, chip ID (ChipID) 3005, data type (DataType) 3006, and page ID (PageID). 3007, job ID (Job ID) 3008, tile coordinates in the Y direction (PacketIDYcoordinate) 3009, tile coordinates in the X direction (PacketIDXcoordinate) 3010, compression flag (Compression Flag) 3017, process instruction (Process Instruction) 3011, packet data length (Processing Instruction) 3011 Packet header length) 3012 or the like is added to the image data to add packet data. It generates data, and outputs the generated packet data to the tile bus 2017 (S1417). At this time, the chip ID is set to “3”, and a value indicating resolution conversion is set as the process instruction.

  The packet data is sequentially generated and transferred to the image ring interface 3 (2101) of the image processing unit 3 via the image ring interface 4 (2102) and the image ring 2008 based on the chip ID, similarly to the command packet.

  In the image ring interface 3 (2101) of the image processing unit 3, the header of the packet is inspected, the chip ID is “3”, and the process instruction indicates resolution conversion. Therefore, the packet data is the resolution conversion in the image processing unit 3. Transferred to the unit 2116. As described above, the resolution conversion unit 2116 sequentially stores the input packets in the image memory, converts them into raster images, converts the resolution by a known method, and converts the generated image with the new resolution. It is cut out into a rectangle and sent again to the image ring as packet data (S1418).

  Based on the information programmed in the image ring interface 2 (2148), it is sequentially stored in the RAM 2002. At the same time, the image ring interface 2 (2148) creates the packet table 6001 on the RAM 2002 (S1419).

  When the scanning operation for one page is completed, the completion is transmitted to the image input interface using the scanner communication means. The image input interface 2112 of the image processing unit 2 (2151) notifies the interrupt to the status processing unit 2105 of the image processing unit 2 (2151) using an interrupt signal (not shown) (S1420).

  The status processing unit 2105 in the image processing unit 2 (2151) creates an interrupt packet (FIG. 5000) and transfers it to the image ring interface 2 (2148) (S1421).

  The image ring interface 2 (2148) interprets the interrupt packet, and transmits the interrupt to the interrupt controller 2140 by an interrupt signal (not shown). The interrupt is transmitted from the interrupt controller 2140 to the CPU 2001, and the CPU 2001 detects the end of the scanning operation (S1422).

  When the scanning operation is finished, a printing operation using the printer 2095 is started. Processing of the controller 2000 in the printing operation will be described with reference to FIG.

  The CPU 2001 creates a command packet having the chip ID “1” via the register access ring 2137 (S1601).

  The created command packet is transferred from the image ring interface 1 (2147) to the image processing unit 1 (2149) via the image ring 2008 (S1602).

  The image ring interface 3 (2101) of the image processing unit 1 (2149) inspects the input command packet. Here, since the chip ID is “1”, the image output process is performed to the image output interface 2113 in the image processing unit 1 (2149) via the command processing unit 2104 and the register setting bus 2109 based on the command data of the command packet. Necessary information for setting is set (S1603).

  Similarly, the CPU 2001 uses the command packet to instruct the printer 2095 to wait for printing by the printer communication means provided in the image output interface 2113 in the image processing unit 1 (2149) (S1604).

  Subsequently, the CPU 2001 programs a memory address or the like where the packet table exists in the DMA means provided in the image ring interface 1 (2147) (S1605).

  Based on the programmed information, the DMA in the image ring interface 1 (2147) reads the data packet from the RAM 2002 and generates a data packet with the chip ID “1” added to the header (S1606).

  Then, the DMA in the image ring interface 1 (2147) transfers the generated data packet to the image processing unit 1 (2149) via the image ring 2008 (S1607).

  The image ring interface 3 (2101) of the image processing unit 1 (2149) inspects the input data packet. Since the chip ID is “1”, the image ID is sequentially transferred to the image output interface 2113 via the image ring interface 3 (2101) and the tile bus 2107 (S1608).

  The image output interface 2113 extracts an image portion from the received data packet, and stores the image data in the image memory 2123 (S1609).

  When the image data for the necessary pixels is accumulated in the image memory 2123, the image output interface 2113 sequentially reads the image data from the image memory 2133 and outputs it to the printer 2095 (S1610).

  As a result, the user obtains an image print that is a copy result. When the required number of pixels have been output, an end interrupt is transmitted to the CPU 2001 by an interrupt packet as in the scan operation (S1611).

  As described above, in this embodiment, an image ring is connected between the system control unit and the image processing unit 1, the image processing unit 1 and the image processing unit 2, the image processing unit 2 and the image processing unit 3, and the image processing unit 3 and the system control unit. Connection was made in 2008, and command packets and data packets were transferred in one direction.

  The image processing unit 2 transmits the image data input by the scanner to the image processing unit 3 based on the setting information based on the command packet. The image processing unit 3 receives the image data from the image processing unit 2 based on the setting information based on the command packet. A scaling scan operation for performing resolution conversion processing on the received image data, transmitting the image data subjected to the resolution conversion processing to the system control unit, and storing the image data received from the image processing unit 3 in the RAM in the system control unit Was done.

  Then, after storing one page of image data in the RAM in the system control unit, the image data in the RAM is transmitted to the image processing unit 1, and the image processing unit 1 receives the setting information from the command packet from the system control unit. A printing operation was performed to output the received image data to a printer. A variable magnification copy process was realized by combining this variable magnification scan operation and printing operation.

  By performing this data transfer process using an image ring that is a unidirectional bus, similarly to the first embodiment, the scaling copy process is performed without causing a decrease in processing speed due to competition between the image processing unit and the bus. It can be performed.

  In addition, since the system control unit and each image processing unit are configured on separate semiconductor substrates, and the image processing unit 3 for image conversion processing is provided independently, only the image conversion function is changed or added. Even when this occurs, the configuration of the controller can be easily changed.

  For example, even when the resolution conversion unit of the image processing unit 3 is changed to a rotation processing unit, an image synthesis unit, or the like, the configuration can be easily changed. Even when another printer is connected, it is only necessary to connect an image processing unit having the same configuration as that of the image processing unit 1 between the image processing unit 1 and the image processing unit 2. The image processing unit can be supplied at low cost.

(Third embodiment)
A controller 2000 in this embodiment is shown in FIG. In the controller 2000 of this embodiment, the image processing unit is only the image processing unit 1 (2149), and the image ring interface 4 (2101) of the image processing unit 1 (2149) is replaced with the image ring interface 2 of the system control unit 2150. It is connected. Both the printer 2095 and the scanner 2070 are connected to the image processing unit 1 (2149). Further, in the image processing unit 1 (2149), a tile expansion unit 2103 and a tile compression unit 2106 are added. That is, the image ring 2008 includes a command processing unit 2104, a status processing unit 2105, a tile expansion unit (2103), and an image ring interface 3 (2101) and an image ring interface 4 (2102) in the image processing unit 2149. Connected to the tile compression unit (2106).

  The tile expansion unit (2103) is connected to the tile bus (2107) in addition to the connection to the image ring interface, and expands the compressed image data input from the image ring and transfers the compressed image data to the tile bus (2107). It is a bridge. In the present embodiment, an example is shown in which JPEG is used for multi-value data and Pac Bits is used as the decompression algorithm for binary data.

  The tile compression unit (2106) is connected to the tile bus (2107) in addition to the connection to the image ring interface, compresses the uncompressed image data input from the tile bus, and transfers the compressed image data to the image ring (2008). It is a bridge. In the present embodiment, an example is shown in which JPEG is used for multi-value data and Pac Bits is used as a compression algorithm for binary data.

  As described above, the image processing unit 1 (2149) has the function of compressing and expanding the data packet, thereby reducing the data capacity of the RAM 2002 necessary for storing the image data.

  When transmitting the compressed data packet from the image processing unit 1 (2149) to the system control unit 2150, the tile compression unit 2106 describes the information of the compressed image data length in the header, and the image ring interface. 4 (2102) transmits a data packet including image data length information in the header.

  However, when transmitting after compressing a data packet, the image data length is not fixed unless the compression is completed, so the image ring interface 4 (2102) must transmit the packet after the compression is completed. That is, a buffer for holding a data packet before transmission in the tile compression unit 2106 or the like is necessary.

  In general, it is difficult to predict the data capacity after compression, and some data may be larger than the original data. In this case, the buffer capacity must be secured with a margin, and in the case of a packet having a large maximum data packet capacity, a very large buffer capacity may be required.

  In this embodiment, a controller 2000 will be described in which a large buffer for temporarily storing packet image data after compression is not necessary.

  First, FIG. 18 shows tile image data in the present embodiment. This tile image data can also be used as tile image data in the first and second embodiments.

  As shown in FIG. 18, a one-page document 1800 input as raster image data from a scanner 2070 or the like is divided into a plurality of rectangular areas (Tile). Each rectangular area has a size of 32 pixels vertically and 32 pixels horizontally, and tile image data is generated for each area. Here, assuming that an A4 size document is read by a scanner 2070 at a resolution of 600 × 600 dpi, and divided by 32 × 32 pixel tiles, 34320 tile image data are generated from an A4 size document.

  In tile image generation, the tile image can be made to have a shape and the number of pixels that are easy to handle by making settings according to the reading resolution and the convenience of image processing.

  The unit of the tile does not have to be 32 × 32 pixels, and may be, for example, 64 × 64 pixels, or may be a rectangle instead of a square. When compressing image data, one page of data is not compressed together, but only image data is compressed for each tile (packet).

  FIG. 19 is a diagram in which blocks related to processing in the present invention are extracted from the system shown in FIG. The flow of image data in the present embodiment will be described with reference to FIG.

  When an uncompressed data packet is input from the tile bus 2107, the tile compression unit 2106 compresses the image data of the packet and sends the compressed data packet to the image ring interface 4 (2102). Further, the image ring interface 4 (2102) sets the chip ID 3005 to “0” and outputs the data packet to the image ring 2008.

  The image ring interface 2 (2148) inspects the chip ID 3005 of the data packet input from the image ring 2008. Here, since the chip ID is “0”, the image ring interface 2 (2148) stores the data packet in the RAM 2002 via the system bus bridge 2007 and the RAM controller 2124.

  When outputting the data packet stored in the RAM 2002, the image ring interface 1 (2147) reads the data packet from the RAM 2002 via the system bus bridge 2007. The image ring interface 1 (2147) sets the chip ID 3005 of the read data packet to “1” and outputs the data packet to the image ring 2008.

  The image ring interface 3 (2103) inspects the chip ID 3005 of the data packet input from the image ring 2008. Here, since the chip ID is “1”, the image ring interface 2 (2148) sends the data packet to the tile decompression unit 2103. The tile decompression unit 2103 decompresses the image data of the compressed data packet and sends the decompressed data packet to the tile bus 2107.

  In the processing described above, the tile compression unit 2106 compresses the tile image data of the data packet, and the image ring interface 4 (2102) sends the compressed data packet to the image ring interface 2 via the image ring 2008. Will be described in detail.

  Here, in order to clarify the explanation of the present invention, it is assumed that the format of the data packet in the present embodiment is the data packet shown in FIG. 4 excluding the Z data 3003.

  FIG. 20 is a block diagram of the inside of the tile compression unit 2106. A packet input interface 2201 receives an input data packet and divides the received data packet into a header 3001 and image data 3002. The packet input interface 2201 sends the header 3001 to the packet output interface 403, while sending the image data 3002 to the compression unit 2202.

  The compression unit 2202 compresses the input image data 3002 and sequentially sends the compressed image data 3002 to the packet output interface 2203.

  The packet output interface 2203 combines the header 3001 received from the packet input interface 2201 and the image data 3002 received from the compression unit 2202 again to form a data packet, and transmits the data packet to the image ring interface 4 (2102).

  FIG. 21 shows a signal waveform when a data packet is transmitted from the image ring interface 4 (2102) to the image ring interface 2 (2148).

  packetdata [31: 0] is a signal to which packet data is transmitted in the image ring 2008, and both the header 3001 and the image data 3002 are transmitted using this signal.

  Signals clk, dataen, sop, eod, and eop are signals issued by the image ring interface 4 (2102).

  The dataen signal is asserted in the cycle for transmitting the packet, and the packet is transmitted in the asserted cycle.

  The sop signal indicates the start of data packet transmission. The header 3001 is included in packetdata [31: 0] of the cycle in which the sop signal is asserted.

  The image ring interface 4 (2102) first transmits a header 3001. At this time, the packet length (PacketByteLength) 3012 and the image data length (ImageDataByteLength) 3015 included in the header 3001 are not determined until all the compression is completed, and therefore may remain undefined. For example, it may be transmitted as 0 length. This header information is later rewritten by the footer.

  Next, the image ring interface 4 (2102) receives the compressed image data 3002 from the tile compression unit 2106, and sequentially transmits the image data 3002 as soon as it is ready for transmission. FIG. 21 shows an example in which one image data 3002 is divided into five data blocks and transmitted.

  When the last image data 3002 is transmitted, the eod signal is asserted and transmitted. As a result, the end of the image data 3002 is notified to the image ring interface 2 (2148). Thereafter, the image ring interface 4 (2102) asserts the eop signal, and transmits a header 3001 including the determined packet length (PacketByteLength) 3012 and the image data length (ImageDataByteLength) 3015 as a footer.

  The image ring interface 2 (2148) stores the data packet received via the image ring 2008 at a preset address in the RAM 2002. At this time, the address storing the header 3001 is stored in an internal register or the like. At this time, uncertain values are written in the packet length (PacketByteLength) 3012 and the image data length (ImageDataByteLength) 3015 of the header 3001.

  When the footer is received at the end of the data packet, the content of the footer is overwritten on the address storing the header 3001. As a result, a fixed packet having a packet length (PacketByteLength) 3012 and an image data length (ImageDataByteLength) 3015 according to the packet format shown in FIG.

  Next, consider a case where the data packet is stored in the RAM 2002 without compressing the image data 3002.

  The tile compression unit 2106 has two types of modes, a mode for performing compression and a mode for not performing compression. This mode is set in advance by the CPU 2001 or the like.

  When the compression mode is set, as described above, the image ring interface 4 (2102) transfers information for transmitting a footer to the system control unit 2150 on the receiving side, and transmits a data packet. Thereafter, the footer including information for updating the header information transferred to the system control unit 2150 is transferred.

  When compression is not performed, the packet input interface 2201 does not send the received data packet to the compression unit 2202, but directly sends it to the packet output interface 2203. Further, the packet output interface 2203 sends to the image ring interface 4 (2102). Send data packets.

  The image ring interface 4 (2102) transmits the header 3001 and the image data 3002 as it is to the image ring interface 2 (2148) via the image ring 2008. At this time, since compression is not performed, the packet length (PacketByteLength) 3012 and the image data length (ImageDataByteLength) 3015 remain unchanged from the original.

  The packet length (PacketByteLength) 3012 and the image data length (ImageDataByteLength) 3015 of the header 3001 are determined at that time, and can be transmitted to the image ring interface 2 (2148).

  FIG. 22 shows signal waveforms when a data packet is transmitted from the image ring interface 4 (2102) to the image ring interface 2 (2148) in this case. The transmission of the header 3001 and the transmission of the image data 3002 are the same as the case where the compression is performed until the final image data 3002 is transmitted.

  When compression is not performed, when the last image data 3002 is transmitted, both the sod signal and the sop signal are asserted, and the footer is not transmitted. The image ring interface 2 (2148) knows that the footer is not transmitted when both the sod signal and the sop signal are asserted, and the header 3001 is not updated. Even in this case, as a result, a data packet according to the packet format shown in FIG.

  There are several parameters other than length that cannot be determined until compression is complete. For example, a DC component indicating the average value of the image data 3002, which is convenient when used to create a thumbnail. Further, when a plurality of image data are included, an offset or the like also corresponds. Even when these parameters are included in the packet header, they can be handled in the same manner as in the present invention. In the case of the present embodiment, in the packet format of FIG. 4, the DC component parameter may be transmitted as thumbnailData 3018 and the information regarding the offset may be transmitted as ImageDataOffset 3013.

  As described above, in this embodiment, the image ring interface 4 transmits a data packet to the image ring interface 2 and then transmits a footer including the same information as the header of the transmitted data packet. The header information is updated based on the received footer.

  Therefore, even if the information included in the header includes information that has not been determined until the compression of the packet image data is completed, the header can be transmitted first, and the packet image data can also be transmitted sequentially. Thereby, it is not necessary to wait for the transmission of the header until the compression of the packet image data is completed, and the necessity of a large buffer for temporarily holding the compressed packet image data can be eliminated.

  Further, it is not necessary to wait for the header transmission until the encoding of the data packet is completed, and the parallel processing of the compression processing in the tile compression unit and the storage control to the RAM by the image ring interface 2 can be performed. Can be made more efficient and faster.

(Other embodiments)
In the above embodiment, the case where the present invention is applied to a digital multi-function peripheral has been described. However, an apparatus to which the present invention can be applied is not limited thereto. For example, the controller unit 2000 may be configured as an external controller of a digital multifunction peripheral.

  In the first embodiment, a controller having two image processing units, a controller having three image processing units in the second embodiment, and a controller having one image processing unit in the third embodiment are taken as examples. The present invention has been described. However, the number of image processing units is not limited, and it goes without saying that the present invention can be applied even when there are three or more image processing units.

  In the first and second embodiments, the present invention has been described by taking copy processing as an example. However, processing to which the present invention can be applied is not limited to this. For example, it can be applied to other image input processes such as electronic filing that stores image data read by a scanner in an external storage device, and other image output processes such as FAX output that outputs facsimile data input via a public line to a printer. It is. At this time, the image input process can be realized by the same process as in FIG. 8, or FIG. 14 and FIG. 15, and the image output process can be realized by the same process as in FIG. 9 or FIG.

  In the third embodiment, the footer transmission according to the present invention is described in the controller shown in FIG. 17, but the present invention is not limited to this. For example, a transmission-side digital multifunction device having the function of the image processing unit 1 and a reception-side digital multifunction device having the function of the system control unit may be provided, and data packets may be transferred via a network or the like.

1 is a diagram illustrating a digital multifunction peripheral according to a first embodiment. FIG. It is a detailed whole block diagram for demonstrating the internal structure of the system control part 2150 in 1st Embodiment, and the image process part 1 (2149). 1 is a configuration diagram of an entire network system including a digital multi-function peripheral according to a first embodiment. 3 is a diagram for explaining a data packet used in a controller 2000. FIG. 6 is a diagram illustrating a packet table used in controller 2000. FIG. 5 is a diagram for explaining a command packet used in a controller 2000. FIG. 5 is a diagram for explaining an interrupt packet used in a controller 2000. FIG. FIG. 6 is a diagram illustrating a scanning operation when a copy job instruction is issued in the digital multi-function peripheral according to the first embodiment. FIG. 6 is a diagram illustrating a printing operation when a copy job instruction is issued in the digital multi-function peripheral according to the first embodiment. It is a figure explaining the digital multifunctional device in 2nd Embodiment. It is a figure which shows the detailed whole structure for demonstrating the internal structure of the image process part 1 in 2nd Embodiment. It is a figure which shows the detailed whole structure for demonstrating the internal structure of the image process part 2 in 2nd Embodiment. It is a figure which shows the detailed whole structure for demonstrating the internal structure of the image process part 3 in 2nd Embodiment. FIG. 10 is a diagram illustrating a scanning operation when a copy job instruction is issued in the digital multi-function peripheral according to the second embodiment. FIG. 10 is a diagram illustrating a scanning operation when a copy job instruction is issued in the digital multi-function peripheral according to the second embodiment. FIG. 10 is a diagram for explaining a printing operation when a copy job instruction is issued in the digital multifunction peripheral according to the second embodiment. It is a detailed whole block diagram for demonstrating the internal structure of the system control part 2150 in 3rd Embodiment, and the image process part 1 (2149). It is a figure which shows the tile image data in 3rd Embodiment. It is the figure which extracted the block relevant to the process in this invention from the system shown in FIG. It is a block diagram inside a tile compression part. It is a figure which shows the signal waveform at the time of transmitting a data packet. It is a figure which shows the signal waveform at the time of transmitting a data packet, without performing compression.

Explanation of symbols

2000 Controller 2001 CPU
2008 Image ring 2070 Scanner 2095 Printer 2101 Image ring interface 3
2102 Image ring interface 4
2147 Image Ring Interface 1
2148 Image Ring Interface 2
2149 Image processing unit 1
2150 System control unit 2151 Image processing unit 2
2152 Image processing unit 3
2103 Tile decompression unit 2106 Tile compression unit

Claims (9)

An image processing apparatus having image processing means for performing image processing on input image data,
Divided image data generating means for dividing the input image data into a plurality of rectangular areas of a predetermined size to generate a plurality of divided image data;
Compression means for compressing the divided image data;
Packet data generation means for generating packet data by adding processing information relating to image processing to be performed on the divided image data compressed by the compression means to the compressed divided image data;
Decompression means for decompressing the compressed divided image data included in the packet data;
An image processing apparatus comprising: image processing means for performing the image processing on the divided image data expanded by the expansion means based on the processing information added to the packet data.   2. The image processing according to claim 1, wherein the divided image data generation unit generates the divided image data by dividing image data input in units of pages into rectangular regions of the predetermined size. apparatus.   The image processing apparatus according to claim 1, further comprising a transfer unit configured to transfer the plurality of packet data generated by the packet data generation unit to the image processing unit. Storage means for storing the divided image data;
The image processing apparatus according to claim 3, wherein the transfer unit transfers a plurality of the divided image data subjected to the image processing by the image processing unit to the storage unit. Image forming means for forming an image on a sheet based on image data input in units of pages;
5. The image transfer unit according to claim 4, wherein the transfer unit transfers, to the image forming unit, image data in units of pages composed of the plurality of divided image data subjected to the image processing by the image processing unit. The image processing apparatus described.   The image processing apparatus according to claim 1, wherein the image processing is rotation processing of image data.   The image processing apparatus according to claim 1, wherein the image processing is resolution conversion processing of image data.   The packet data generation means can add a plurality of pieces of processing information corresponding to the number of image processing means included in the image processing apparatus as additional information to the packet data, and the additional information corresponds to the number of image processing means. The image processing apparatus according to claim 1, wherein the information is fixed-length information. An image processing method for performing image processing on input image data,
A divided image data generation step of generating a plurality of divided image data by dividing the input image data into a plurality of rectangular regions of a predetermined size;
A compression step of compressing the divided image data;
A packet data generating step of generating packet data by adding processing information related to image processing to be performed on the divided image data compressed by the compression step to the compressed divided image data;
A decompression step of decompressing the compressed divided image data included in the packet data;
An image processing method comprising: an image processing step of performing the image processing on the divided image data expanded by the expansion step based on the processing information added to the packet data.

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