JP3873158B2

JP3873158B2 - Display panel and manufacturing method thereof

Info

Publication number: JP3873158B2
Application number: JP17799398A
Authority: JP
Inventors: 栄一尾中; 建史神谷
Original assignee: Casio Computer Co Ltd
Current assignee: Casio Computer Co Ltd
Priority date: 1998-06-11
Filing date: 1998-06-11
Publication date: 2007-01-24
Anticipated expiration: 2018-06-11
Also published as: JPH11354810A

Description

【０００１】
【発明の属する技術分野】
この発明は、液晶表示パネル等の表示パネル及びその製造方法に関する。
【０００２】
【従来の技術】
図２５（Ａ）は従来の液晶表示パネルの一例の一部の平面図を示し、図２５（Ｂ）はそのＢ−Ｂ線に沿う断面図を示したものである。この液晶表示パネルを製造する場合には、まず、図２６に示すように、ガラス基板１の上面の所定の個所にＡｌまたはＡｌ合金からなるゲート電極２及びゲートライン（走査線）３（図２５（Ａ）参照）を形成し、その上面に窒化シリコンからなるゲート絶縁膜４を成膜し、その上面に中性アモルファスシリコンからなる半導体膜５を成膜し、その上面であってゲート電極２上の所定の個所に窒化シリコンからなるチャネル保護膜６を形成する。次に、フッ化アンモニウム溶液による表面処理により、チャネル保護膜６下以外の領域における半導体膜５の表面の自然酸化膜（図示せず）を除去する。次に、図２７に示すように、上面全体にＮ型アモルファスシリコンからなるＮ型半導体膜７を成膜する。次に、図２８に示すように、フォトリソグラフィ法により、Ｎ型半導体膜７及び半導体膜５の不要な部分を除去する。この状態では、ゲート絶縁膜４の上面の所定の箇所でゲート電極２に対応する部分つまりデバイスエリアに半導体膜５Ａが形成されている。また、チャネル保護膜６の上面両側及びその両側における半導体膜５Ａの上面にＮ型半導体膜７Ｄ、７Ｓが形成されている。次に、図２５（Ａ）、（Ｂ）に示すように、ソース側のＮ型半導体膜７Ｓの上面及びゲート絶縁膜４の上面の所定の箇所にＩＴＯからなるソース電極８及び画素電極９を形成する。次に、ドレイン側のＮ型半導体膜７Ｄの上面及びゲート絶縁膜４の上面の他の所定の箇所にＡｌからなるドレイン電極１０及びドレインライン（信号線）１１を形成する。この場合、ゲート電極２、ゲート絶縁膜４、半導体膜５Ａ、Ｎ型半導体膜７Ｓ、７Ｄ、ソース電極８、ドレイン電極１０により、スイッチング素子としての薄膜トランジスタが構成されている。
【０００３】
【発明が解決しようとする課題】
しかしながら、従来のこのような液晶表示パネルの製造方法では、Ｎ型半導体膜７を成膜する工程とドレイン電極１０及びドレインライン１１を形成するためのＡｌ系金属膜を成膜する工程との間に、フォトリソグラフィ法によりＮ型半導体膜７Ｄ、７Ｓ及び半導体膜５Ａを形成する工程、ＩＴＯ膜を成膜してフォトリソグラフィ法によりソース電極８及び画素電極９を形成する工程が存在するので、Ｎ型半導体膜７Ｄ、７Ｓの表面が酸化・汚染されやすく、Ｎ型半導体膜７Ｄ、７Ｓとソース電極８及びドレイン電極１０との間のコンタクト抵抗が高くなり、薄膜トランジスタのオン電流が減少するという問題があった。
この発明の課題は、ソース側及びドレイン側のＮ型半導体膜とその各上に形成されるソース電極及びドレイン電極との間のコンタクト抵抗を小さくすることである。
【０００４】
【課題を解決するための手段】
請求項１記載の発明に係る表示パネルは、薄膜トランジスタ及び該薄膜トランジスタのソース電極に接続された画素電極を備えた表示パネルにおいて、前記薄膜トランジスタを、ゲート電極と、該ゲート電極上に設けられたゲート絶縁膜と、該ゲート絶縁膜上のデバイスエリアに設けられた半導体膜と、該半導体膜上のドレイン側に設けられたＮ型半導体膜と、該Ｎ型半導体膜上に設けられたシリサイド膜と、該シリサイド膜上に形成されたシリサイド化可能な金属膜及び該金属膜上に形成されたＡｌ系金属膜からなるドレイン電極と、前記半導体膜上のソース側に設けられたＮ型半導体膜と、該Ｎ型半導体膜上に設けられたシリサイド膜と、該シリサイド膜上に形成され前記画素電極が接続されたシリサイド化可能な金属膜及び前記金属膜上に形成されたＡｌ系金属膜からなるソース電極と、によって構成し、前記ソース電極のＡｌ系金属膜によって前記ソース側の前記Ｎ型半導体膜、前記シリサイド膜及び前記シリサイド化可能な金属膜の端面を覆ったものである。請求項２記載の発明に係る表示パネルは、薄膜トランジスタ及び該薄膜トランジスタのソース電極に接続された画素電極を備えた表示パネルにおいて、前記薄膜トランジスタを、ゲート電極と、該ゲート電極上に設けられたゲート絶縁膜と、該ゲート絶縁膜上のデバイスエリアに設けられた半導体膜と、前記ゲート絶縁膜上であって前記半導体膜の両側に設けられたドレイン側及びソース側のＮ型半導体膜と、前記ドレイン側のＮ型半導体膜上に設けられたシリサイド膜と、該シリサイド膜上に形成されたシリサイド化可能な金属膜及び該金属膜上に形成されたＡｌ系金属膜からなるドレイン電極と、前記ソース側のＮ型半導体膜上に設けられたシリサイド膜と、該シリサイド膜上に形成され前記画素電極が接続されたシリサイド化可能な金属膜及び該金属膜上に形成されたＡｌ系金属膜からなるソース電極と、によって構成し、前記ソース電極のＡｌ系金属膜によって前記ソース側の前記シリサイド膜及び前記シリサイド化可能な金属膜の端面を覆ったものである。請求項３記載の発明に係る表示パネルは、薄膜トランジスタ及び該薄膜トランジスタのソース電極に接続された画素電極を備えた表示パネルにおいて、前記薄膜トランジスタは、ゲート電極と、該ゲート電極上に設けられたゲート絶縁膜と、該ゲート絶縁膜上のデバイスエリアに設けられた半導体膜と、該半導体膜上のドレイン側に設けられたＮ型半導体膜と、該Ｎ型半導体膜上に設けられたシリサイド膜と、該シリサイド膜上に形成されたシリサイド化可能な金属膜及び該金属膜上に形成されたＡｌ系金属膜からなるドレイン電極と、前記半導体膜上のソース側に設けられたＮ型半導体膜と、該Ｎ型半導体膜上に設けられたシリサイド膜と、該シリサイド膜上に形成されたシリサイド化可能な金属膜及び前記金属膜上に形成された前記画素電極に接続され、該画素電極と同一の導電材料からなるソース電極と、によって構成され、前記ソース電極の前記導電材料によって前記ソース側の前記Ｎ型半導体膜、前記シリサイド膜及び前記シリサイド化可能な金属膜の端面を覆ったものである。請求項４記載の発明に係る表示パネルの製造方法は、基板上にゲート電極、ゲート絶縁膜、半導体膜、Ｎ型半導体膜及びシリサイド化可能な金属膜をこの順で形成して前記Ｎ型半導体膜と前記金属膜との界面にシリサイド膜を形成する工程と、前記シリサイド膜を残して前記シリサイド化可能な高融点金属膜を剥離する工程と、前記半導体膜上のドレイン側及びソース側に前記Ｎ型半導体膜及び前記シリサイド膜を残存させる工程と、前記ソース側のシリサイド膜に接続されるＩＴＯからなる画素電極を形成する工程と、上面全体にＡｌ系金属膜からなるソース・ドレイン電極形成用金属膜及びウェットエッチング時に前記Ａｌ系金属膜と前記画素電極とが電池反応を起こさないようにするためのＣrからなる保護用金属膜をこの順で成膜し、これらの金属膜をウェットエッチングによりパターニングすることにより、前記ドレイン側のシリサイド膜上にドレイン電極を形成するとともにその上に前記保護用金属膜を残存させ、且つ前記ソース側のシリサイド膜上にソース電極を形成するとともにその上に前記保護用金属膜を残存させ、この後残存する前記保護用金属膜を剥離する工程と、を具備したものである。請求項５記載の発明に係る表示パネルの製造方法は、基板上にゲート電極、ゲート絶縁膜及び半導体膜をこの順で形成する工程と、前記半導体膜上の所定の箇所にチャネル保護膜を形成し、該チャネル保護膜をマスクとして前記半導体膜にＮ型イオンを打ち込むことにより、前記チャネル保護膜下以外の領域における前記半導体膜をＮ型半導体膜とする工程と、前記Ｎ型半導体膜上にシリサイド化可能な金属膜を成膜して前記Ｎ型半導体膜と前記金属膜との界面にシリサイド膜を形成する工程と、前記シリサイド膜を残して前記シリサイド化可能な高融点金属膜を剥離する工程と、前記ソース側のシリサイド膜に接続されるＩＴＯからなる画素電極を形成する工程と、上面全体にＡｌ系金属膜からなるソース・ドレイン電極形成用金属膜及びウェットエッチング時に前記Ａｌ系金属膜と前記画素電極とが電池反応を起こさないようにするためのＣrからなる保護用金属膜をこの順で成膜し、これらの金属膜をウェットエッチングによりパターニングすることにより、前記ドレイン側のシリサイド膜上にドレイン電極を形成するとともにその上に前記保護用金属膜を残存させ、且つ前記ソース側のシリサイド膜上にソース電極を形成するとともにその上に前記保護用金属膜を残存させ、この後残存する前記保護用金属膜を剥離する工程と、を具備したものである。請求項６記載の発明に係る表示パネルの製造方法は、基板上にゲート電極、ゲート絶縁膜及び半導体膜をこの順で形成する工程と、前記半導体膜上のドレイン側及びソース側にＮ型半導体膜を形成する工程と、前記Ｎ型半導体膜上にシリサイド化可能な金属膜を成膜して前記Ｎ型半導体膜と前記金属膜との界面にシリサイド膜を形成する工程と、前記ソース側の金属膜に接続されるＩＴＯからなる画素電極を形成する工程と、上面全体にＡｌ系金属膜からなるソース・ドレイン電極形成用金属膜及びウェットエッチング時に前記Ａｌ系金属膜と前記画素電極とが電池反応を起こさないようにするためのＣ r からなる保護用金属膜をこの順で成膜する工程と、これらの金属膜をウェットエッチングして、前記Ａｌ系金属膜からなるソース電極形成用金属膜が前記ソース側の前記Ｎ型半導体膜、前記シリサイド膜及び前記シリサイド化可能な金属膜の端面を覆うようにパターニングすることにより、前記ドレイン側の金属膜上にＡｌ系金属膜からなるドレイン電極を形成するとともに、前記ソース側の前記Ｎ型半導体膜、前記シリサイド膜及び前記シリサイド化可能な金属膜の端面を覆うＡｌ系金属膜からなるソース電極を形成する工程と、を具備したものである。請求項７記載の発明に係る表示パネルの製造方法は、基板上にゲート電極、ゲート絶縁膜及び半導体膜をこの順で形成する工程と、前記半導体膜上の所定の箇所にチャネル保護膜を形成し、該チャネル保護膜をマスクとして前記半導体膜にＮ型イオンを打ち込むことにより、前記チャネル保護膜下以外のドレイン及びソース領域における前記半導体膜をＮ型半導体膜とする工程と、前記Ｎ型半導体膜上にシリサイド化可能な金属膜を成膜して前記Ｎ型半導体膜と前記金属膜との界面にシリサイド膜を形成する工程と、前記ソース側の金属膜に接続されるＩＴＯからなる画素電極を形成する工程と、上面全体にＡｌ系金属膜からなるソース・ドレイン電極形成用金属膜及びウェットエッチング時に前記Ａｌ系金属膜と前記画素電極とが電池反応を起こさないようにするためのＣ r からなる保護用金属膜をこの順で成膜する工程と、これらの金属膜をウェットエッチングして、前記Ａｌ系金属膜からなるソース電極形成用金属膜が前記ソース側の前記Ｎ型半導体膜、前記シリサイド膜及び前記シリサイド化可能な金属膜の端面を覆うようにパターニングすることにより、前記ドレイン側の金属膜上にＡｌ系金属膜からなるドレイン電極を形成するとともに、前記ソース側の前記シリサイド膜及び前記シリサイド化可能な金属膜の端面を覆うＡｌ系金属膜からなるソース電極を形成する工程と、を具備したものである。請求項８記載の発明に係る表示パネルの製造方法は、基板上にゲート電極、ゲート絶縁膜及び半導体膜をこの順で形成する工程と、前記半導体膜上のドレイン側及びソース側にＮ型半導体膜を形成する工程と、前記Ｎ型半導体膜上にシリサイド化可能な金属膜を成膜して前記Ｎ型半導体膜と前記金属膜との界面にシリサイド膜を形成する工程と、前記ソース側の金属膜に接続されるＩＴＯからなる画素電極を形成するとともに、該画素電極と同一の導電材料によって前記ソース側の前記Ｎ型半導体膜、前記シリサイド膜及び前記シリサイド化可能な金属膜の端面を覆うソース電極を形成する工程と、上面全体にＡｌ系金属膜からなるソース・ドレイン電極形成用金属膜及びウェットエッチング時に前記Ａｌ系金属膜と前記画素電極とが電池反応を起こさないようにするためのＣ r からなる保護用金属膜をこの順で成膜する工程と、これらの金属膜をウェットエッチングによりパターニングし、不要な部分を除去することにより、前記ドレイン側の前記金属膜上にＡｌ系金属膜からなるドレイン電極を形成する工程と、を具備したものである。請求項９記載の発明に係る表示パネルの製造方法は、基板上にゲート電極、ゲート絶縁膜及び半導体膜をこの順で形成する工程と、前記半導体膜上の所定の箇所にチャネル保護膜を形成し、該チャネル保護膜をマスクとして前記半導体膜にＮ型イオンを打ち込むことにより、前記チャネル保護膜下以外のソース及びドレイン領域における前記半導体膜をＮ型半導体膜とする工程と、前記Ｎ型半導体膜上にシリサイド化可能な金属膜を成膜して前記Ｎ型半導体膜と前記金属膜との界面にシリサイド膜を形成する工程と、前記ソース側の金属膜に接続されるＩＴＯからなる画素電極を形成するとともに、該画素電極と同一の導電材料によって前記ソース側の前記シリサイド膜及び前記シリサイド化可能な金属膜の端面を覆うソース電極を形成する工程と、上面全体にＡｌ系金属膜からなるソース・ドレイン電極形成用金属膜及びウェットエッチング時に前記Ａｌ系金属膜と前記画素電極とが電池反応を起こさないようにするためのＣ r からなる保護用金属膜をこの順で成膜する工程と、これらの金属膜をウェットエッチングによりパターニングし、不要な部分を除去することにより、前記ドレイン側の前記金属膜上にＡｌ系金属膜からなるドレイン電極を形成する工程と、を具備したものである。そして、以上の発明によれば、ドレイン側及びソース側のＮ型半導体膜とその各上に形成されたドレイン電極及びソース電極との間に良質のシリサイド膜を形成しているので、ドレイン側及びソース側のＮ型半導体膜とその各上に形成されたドレイン電極及びソース電極との間のコンタクト抵抗を小さくすることができる。
【０００５】
【発明の実施の形態】
（第１実施形態）
図１（Ａ）はこの発明の第１実施形態における液晶表示パネルの要部の平面図を示し、図１（Ｂ）はそのＢ−Ｂ線に沿う断面図を示したものである。この液晶表示パネルを製造する場合には、まず、図２に示すように、ガラス基板２１の上面の所定の箇所に、スパッタ法により成膜したＡｌまたはＡｌ合金からなるＡｌ系金属膜をフォトリソグラフィ法（以下、ＰＬ法という。）により所定のパターンに加工することにより、ゲート電極２２及びゲートライン（走査線）２３（図１（Ａ）参照）を形成する。次に、上面全体に、ＣＶＤ法により、窒化シリコンからなるゲート絶縁膜２４、中性アモルファスシリコンからなる半導体膜２５及び窒化シリコンからなるチャネル保護膜形成用膜２６を連続して成膜する。次に、チャネル保護膜形成用膜２６をＰＬ法により所定のパターンに加工することにより、半導体膜２５の上面であってゲート電極２２上の所定の個所にチャネル保護膜２６Ａを形成する。次に、フッ化アンモニウム溶液による表面処理により、チャネル保護膜２６Ａ下以外の領域における半導体膜２５の表面の自然酸化膜（図示せず）を除去する。
【０００６】
次に、図３に示すように、上面全体にＣＶＤ法によりＮ型アモルファスシリコンからなるＮ型半導体膜２７を成膜する。次に、フッ化アンモニウム溶液による表面処理により、Ｎ型半導体膜２７の表面の自然酸化膜（図示せず）を除去する。次に、Ｎ型半導体膜２７の上面にスパッタ法によりＣｒ膜２８を成膜する。すると、Ｎ型半導体膜２７とＣｒ膜２８との界面が清浄であるので、Ｎ型半導体膜２７とＣｒ膜２８との界面に良質なＣｒシリサイド膜２９が形成される。次に、図４に示すように、ＰＬ法により、Ｃｒ膜２８、Ｃｒシリサイド膜２９、Ｎ型半導体膜２７及び半導体膜２５の不要な部分を除去する。この状態では、ゲート絶縁膜２４の上面の所定の箇所でゲート電極２２に対応する部分つまりデバイスエリアに半導体膜２５Ａが形成されている。また、チャネル保護膜２６Ａの上面両側及びその両側における半導体膜２５Ａの上面にＮ型半導体膜２９Ｄ、２９Ｓ、Ｃｒシリサイド膜２９Ｄ、２９Ｓ及びＣｒ膜２８Ｄ、２８Ｓが形成されている。
【０００７】
次に、図５に示すように、スパッタ法により成膜した透明なＩＴＯ（インジウム−錫酸化物）等からなる透明金属膜膜をＰＬ法により所定のパターンに加工することにより、ソース側のＣｒ膜２８Ｓの上面の所定の箇所及びゲート絶縁膜２４の上面の所定の箇所に画素電極３０を形成する。次に、図６に示すように、上面全体にスパッタ法によりＡｌ系金属膜３１及び保護用Ｃｒ膜３２を連続して成膜する。次に、保護用Ｃｒ膜３２の上面の所定の箇所に、ドレイン電極、ドレインライン（信号線）及びソース電極を形成するためのレジスト膜３３Ｄ、３３Ｓを形成する。この場合、レジスト膜３３ＤのＣｒ膜２８Ｄ上におけるサイズは同Ｃｒ膜２８Ｄのサイズと同じなっているが、レジスト膜３３ＳのサイズはＣｒ膜２８Ｓのサイズよりも所定の大きさだけ大きくなっている。また、保護用Ｃｒ膜３２は、レジスト現像時にＩＴＯからなる画素電極３０とＡｌ系金属膜３１とが電池反応により腐食しないようにするためのものである。
【０００８】
次に、図７に示すように、レジスト膜３３Ｄ、３３Ｓをマスクとしてウェットエッチングを行うことにより、保護用Ｃｒ膜３２及びＡｌ系金属膜３１の不要な部分を除去する。次に、レジスト膜３３Ｄ、３３Ｓを剥離する。次に、保護用Ｃｒ膜３２をウェットエッチングにより剥離する。すると、図１（Ａ）、（Ｂ）に示すように、Ｃｒ膜２８Ｄの上面及びゲート絶縁膜２４の上面の所定の箇所にＡｌ系金属膜３１からなるドレイン電極３４及びドレインライン３５が形成される。また、Ｃｒ膜２８Ｓの上面及びその周囲の所定の箇所にＡｌ系金属膜３１からなるソース電極３６が形成される。この場合、Ｃｒ膜２８Ｓ、Ｃｒシリサイド膜２９Ｓ及びＮ型半導体膜２７Ｓの端面はソース電極３６によって覆われている。このようにした理由については後で説明する。そして、ゲート電極２２、半導体膜２５Ａ、Ｎ型半導体膜２７Ｄ、２７Ｓ、Ｃｒシリサイド膜２９Ｄ、２９Ｓ、Ｃｒ膜２８Ｄ、２８Ｓ、ドレイン電極３４、ソース電極３６により、スイッチング素子としての薄膜トランジスタが構成されている。
【０００９】
ここで、ソース側のＣｒ膜２８Ｓ、Ｃｒシリサイド膜２９Ｓ及びＮ型半導体膜２７Ｓの端面をソース電極３６で覆った理由について説明する。まず、図８（Ａ）、（Ｂ）に示すように、レジスト膜３３Ｓの所定の３つの端面ａ、ｂ、ｃがＣｒ膜２８Ｓの所定の３つの端面と一致する場合には、レジスト膜３３Ｓをマスクとしてウェットエッチングを行うことにより、保護用Ｃｒ膜３２及びＡｌ系金属膜３１の不要な部分を除去すると、Ｃｒ膜２８Ｄの所定の３つの端面が露出されることになる。この状態で、レジスト膜３３Ｄ、３３Ｓを剥離した後に、保護用Ｃｒ膜３２をウェットエッチングにより剥離すると、ＩＴＯからなる画素電極３０とＣｒ膜２８Ｄとが接続されているので、Ｃｒエッチャント中におけるＩＴＯ−Ｃｒ系の電池反応により、図９（Ａ）、（Ｂ）に示すように、Ｃｒ膜２８Ｓのサイドエッチングが激しく進行し、１０秒程度で１／３程度に減少してしまう。このような場合には、ソース側におけるコンタクト特性が劣化してしまい、好ましくない。そこで、図７に示すように、ソース側のＣｒ膜２８Ｓ、Ｃｒシリサイド膜２９Ｓ及びＮ型半導体膜２７Ｓの端面をソース電極３６で覆うと、Ｃｒ膜２８Ｓのサイドエッチングが防止されることになる。
【００１０】
そして、以上のようにして製造された液晶表示パネルでは、Ｎ型半導体膜２７Ｄ、２７Ｓとその各上に形成されたドレイン電極３４及びソース電極３６との間に良質のＣｒシリサイド膜２９Ｄ、２９Ｓ及びＣｒ膜２８Ｄ、２８Ｓを形成しているので、Ｎ型半導体膜２７Ｄ、２７Ｓとその各上に形成されたドレイン電極３４及びソース電極３６との間のコンタクト抵抗を小さくすることができ、ひいては寄生抵抗によるオン電流の低下を少なくすることができる。
【００１１】
（第２実施形態）
図１０（Ａ）はこの発明の第２実施形態における液晶表示パネルの要部の平面図を示し、図１０（Ｂ）はそのＢ−Ｂ線に沿う断面図を示したものである。この液晶表示パネルを製造する場合、図２〜図４に示すまでの工程は上記第１実施形態の場合と同じであるので、その後の工程から説明する。図１１に示すように、ソース側のＣｒ膜２８Ｓの上面及びその周囲の所定の箇所とゲート絶縁膜２４の上面の所定の箇所に、スパッタ法により成膜したＩＴＯ膜をＰＬ法により所定のパターンに加工することにより、ソース電極３６及び画素電極３０を形成する。この場合、Ｃｒ膜２８Ｓ、Ｃｒシリサイド膜２９Ｓ及びＮ型半導体膜２７Ｓの所定の３つの端面はソース電極３６によって覆われ、残りの１つの端面は画素電極３０によって覆われている。次に、図１２に示すように、上面全体にスパッタ法によりＡｌ系金属膜３１及び保護用Ｃｒ膜３２を連続して成膜する。次に、保護用Ｃｒ膜３２の上面の所定の箇所に、ドレイン電極及びドレインラインを形成するためのレジスト膜３３Ｄを形成する。この場合、レジスト膜３３ＤのＣｒ膜２８Ｄ上におけるサイズは同Ｃｒ膜２８Ｄのサイズと同じなっている。また、保護用Ｃｒ膜３２は、レジスト現像時にＩＴＯからなる画素電極３０とＡｌ系金属膜３１とが電池反応により腐食しないようにするためのものである。
【００１２】
次に、図１３に示すように、レジスト膜３３Ｄをマスクとしてウェットエッチングを行うことにより、保護用Ｃｒ膜３２及びＡｌ系金属膜３１の不要な部分を除去する。次に、レジスト膜３３Ｄを剥離する。次に、保護用Ｃｒ膜３２をウェットエッチングにより剥離する。すると、図１０（Ａ）、（Ｂ）に示すように、Ｃｒ膜２８Ｄの上面及びゲート絶縁膜２４の上面の所定の箇所にＡｌ系金属膜３１からなるドレイン電極３４及びドレインライン３５が形成される。この場合、Ｃｒ膜２８Ｓ、Ｃｒシリサイド膜２９Ｓ及びＮ型半導体膜２７Ｓの端面はＩＴＯからなるソース電極３６によって覆われているので、Ｃｒ膜２８Ｓのサイドエッチングが防止される。
【００１３】
そして、以上のようにして製造された液晶表示パネルでも、Ｎ型半導体膜２７Ｄ、２７Ｓとその各上に形成されたドレイン電極３４及びソース電極３６との間に良質のＣｒシリサイド膜２９Ｄ、２９Ｓ及びＣｒ膜２８Ｄ、２８Ｓを形成しているので、Ｎ型半導体膜２７Ｄ、２７Ｓとその各上に形成されたドレイン電極３４及びソース電極３６との間のコンタクト抵抗を小さくすることができ、ひいては寄生抵抗によるオン電流の低下を少なくすることができる。
【００１４】
（第３実施形態）
図１４（Ａ）はこの発明の第３実施形態における液晶表示パネルの要部の平面図を示し、図１４（Ｂ）はそのＢ−Ｂ線に沿う断面図を示したものである。この液晶表示パネルを製造する場合、図２〜図３に示すまでの工程は上記第１実施形態の場合と同じであるので、その後の工程から説明する。図１５に示すように、図３に示すＣｒ膜２８をウェッチエッチングにより剥離する。次に、図１６に示すように、ＰＬ法により、Ｃｒシリサイド膜２９、Ｎ型半導体膜２７及び半導体膜２５の不要な部分を除去する。この状態では、ゲート絶縁膜２４の上面の所定の箇所でゲート電極２２に対応する部分つまりデバイスエリアに半導体膜２５Ａが形成されている。また、チャネル保護膜２６Ａの上面両側及びその両側における半導体膜２５Ａの上面にＮ型半導体膜２７Ｄ、２７Ｓ及びＣｒシリサイド膜２９Ｄ、２９Ｓが形成されている。
【００１５】
次に、図１７に示すように、スパッタ法により成膜したＩＴＯ膜をＰＬ法により所定のパターンに加工することにより、ソース側のＣｒシリサイド膜２９Ｓの上面の所定の箇所及びゲート絶縁膜２４の上面の所定の箇所に画素電極３０を形成する。次に、上面全体にスパッタ法によりＡｌ系金属膜３１及び保護用Ｃｒ膜３２を連続して成膜する。次に、保護用Ｃｒ膜３２の上面の所定の箇所に、ドレイン電極、ドレインライン（信号線）及びソース電極を形成するためのレジスト膜３３Ｄ、３３Ｓを形成する。この場合、レジスト膜３３ＤのＣｒシリサイド膜２９Ｄ上におけるサイズは同Ｃｒシリサイド膜２９Ｄのサイズと同じなっており、またレジスト膜３３ＳのＣｒシリサイド膜２９Ｓ上におけるサイズも同Ｃｒシリサイド膜２９Ｓのサイズと同じとなっている。また、保護用Ｃｒ膜３２は、レジスト現像時にＩＴＯからなる画素電極３０とＡｌ系金属膜３１とが電池反応により腐食しないようにするためのものである。
【００１６】
次に、図１８に示すように、レジスト膜３３Ｄ、３３Ｓをマスクとしてウェットエッチングを行うことにより、保護用Ｃｒ膜３２及びＡｌ系金属膜３１の不要な部分を除去する。次に、レジスト膜３３Ｄ、３３Ｓを剥離する。次に、保護用Ｃｒ膜３２をウェットエッチングにより剥離する。すると、図１４（Ａ）、（Ｂ）に示すように、Ｃｒシリサイド膜２９Ｄの上面及びゲート絶縁膜２４の上面の所定の箇所にＡｌ系金属膜３１からなるドレイン電極３４及びドレインライン３５が形成される。また、Ｃｒシリサイド膜２９Ｓの上面及び画素電極３０の上面の所定の箇所にＡｌ系金属膜３１からなるソース電極３６が形成される。そして、ゲート電極２２、半導体膜２５Ａ、Ｎ型半導体膜２７Ｄ、２７Ｓ、Ｃｒシリサイド膜２９Ｄ、２９Ｓ、ドレイン電極３４、ソース電極３６により、スイッチング素子としての薄膜トランジスタが構成されている。
【００１７】
そして、以上のようにして製造された液晶表示パネルでは、Ｎ型半導体膜２７Ｄ、２７Ｓとその各上に形成されたドレイン電極３４及びソース電極３６との間に良質のＣｒシリサイド膜２９Ｄ、２９Ｓを形成しているので、Ｎ型半導体膜２７Ｄ、２７Ｓとその各上に形成されたドレイン電極３４及びソース電極３６との間のコンタクト抵抗を小さくすることができ、ひいては寄生抵抗によるオン電流の低下を少なくすることができる。
【００１８】
（参考実施形態）
図１９（Ａ）はこの発明の第４実施形態における液晶表示パネルの要部の平面図を示し、図１９（Ｂ）はそのＢ−Ｂ線に沿う断面図を示したものである。この液晶表示パネルを製造する場合、図２に示すまでの工程は上記第１実施形態の場合と同じであるので、その後の工程から説明する。図２０に示すように、上面全体にスパッタ法によりＣｒ膜２８を成膜する。すると、チャネル保護膜２６Ａ下以外の領域における半導体膜２５とＣｒ膜２８との界面が清浄であるので、チャネル保護膜２６Ａ下以外の領域における半導体膜２５とＣｒ膜２８との界面に良質なＣｒシリサイド膜２９が形成される。次に、図２１に示すように、チャネル保護膜２６Ａをマスクとしてリンイオン等のＮ型イオンを打ち込む。打ち込まれたＮ型イオンは、Ｃｒ膜２８に注入されるとともに、Ｃｒ膜２８及びＣｒシリサイド膜２９を貫通してチャネル保護膜２６Ａ下以外の領域における半導体膜２５に注入される。この結果、Ｃｒ膜２８の膜質はＮ型イオンの注入により改善される。また、チャネル保護膜２６Ａ下に中性アモルファスシリコンからなる半導体膜２５Ａが形成され、Ｃｒシリサイド膜２９下にＮ型アモルファスシリコンからなるＮ型半導体膜２７が形成される。
【００１９】
次に、図２２に示すように、ＰＬ法により、Ｃｒ膜２８、Ｃｒシリサイド膜２９、Ｎ型半導体膜２７の不要な部分を除去する。この状態では、ゲート絶縁膜２４の上面の所定の箇所でゲート電極２２に対応する部分つまりデバイスエリアに半導体膜２５Ａ及びＮ型半導体膜２７Ｄ、２７Ｓが形成されている。また、Ｎ型半導体膜２７Ｄ、２７Ｓの上面にＣｒシリサイド膜２９Ｄ、２９Ｓが形成されている。さらに、チャネル保護膜２６Ａの上面両側及びＣｒシリサイド膜２９Ｄ、２９Ｓの上面にＣｒ膜２８Ｄ、２８Ｓが形成されている。
【００２０】
次に、図２３に示すように、スパッタ法により成膜したＩＴＯ膜をＰＬ法により所定のパターンに加工することにより、ソース側のＣｒ膜２８Ｓの上面の所定の箇所及びゲート絶縁膜２４の上面の所定の箇所に画素電極３０を形成する。次に、上面全体にスパッタ法によりＡｌ系金属膜３１及び保護用Ｃｒ膜３２を連続して成膜する。次に、保護用Ｃｒ膜３２の上面の所定の箇所に、ドレイン電極、ドレインライン（信号線）及びソース電極を形成するためのレジスト膜３３Ｄ、３３Ｓを形成する。この場合、レジスト膜３３ＤのＣｒ膜２８Ｄ上におけるサイズは同Ｃｒ膜２８Ｄのサイズと同じなっており、レジスト膜３３ＳのＣｒ膜２８Ｓ上におけるサイズは同Ｃｒ膜２８Ｓのサイズと同じとなっている。また、保護用Ｃｒ膜３２は、レジスト現像時にＩＴＯからなる画素電極３０とＡｌ系金属膜３１とが電池反応により腐食しないようにするためのものである。
【００２１】
次に、図２４に示すように、レジスト膜３３Ｄ、３３Ｓをマスクとしてウェットエッチングを行うことにより、保護用Ｃｒ膜３２及びＡｌ系金属膜３１の不要な部分を除去する。次に、レジスト膜３３Ｄ、３３Ｓを剥離する。次に、保護用Ｃｒ膜３２をウェットエッチングにより剥離する。すると、図１９（Ａ）、（Ｂ）に示すように、Ｃｒ膜２８Ｄの上面及びゲート絶縁膜２４の上面の所定の箇所にＡｌ系金属膜３１からなるドレイン電極３４及びドレインライン３５が形成される。また、Ｃｒ膜２８Ｓの上面及び画素電極３０の上面の所定の箇所にＡｌ系金属膜３１からなるソース電極３６が形成される。この場合、Ｃｒ膜２８Ｓの端面はソース電極３６によって覆われていないが、Ｃｒ膜２８の膜質がＮ型イオンの注入により改質されているので、Ｃｒ膜２８Ｓのサイドエッチングが防止される。そして、ゲート電極２２、半導体膜２５Ａ、Ｎ型半導体膜２７Ｄ、２７Ｓ、Ｃｒシリサイド膜２９Ｄ、２９Ｓ、Ｃｒ膜２８Ｄ、２８Ｓ、ドレイン電極３４、ソース電極３６により、スイッチング素子としての薄膜トランジスタが構成されている。
【００２２】
そして、以上のようにして製造された液晶表示パネルでも、Ｎ型半導体膜２７Ｄ、２７Ｓとその各上に形成されたドレイン電極３４及びソース電極３６との間に良質のＣｒシリサイド膜２９Ｄ、２９Ｓ及びＣｒ膜２８Ｄ、２８Ｓを形成しているので、Ｎ型半導体膜２７Ｄ、２７Ｓとその各上に形成されたドレイン電極３４及びソース電極３６との間のコンタクト抵抗を小さくすることができ、ひいては寄生抵抗によるオン電流の低下を少なくすることができる。
【００２３】
なお、上記第１〜第３実施形態では、半導体膜２５Ａの上面両側にＮ型半導体膜２７Ｄ、２７Ｓを形成した場合について説明したが、これに限定されるものではない。例えば、図２において、チャネル保護膜２６Ａをマスクとして半導体膜２５にリンイオン等のＮ型イオンを打ち込み、チャネル保護膜２６Ａ下以外の領域にＮ型半導体膜を形成するようにしてもよい。また、上記第１〜第３実施形態では、チャネル保護膜２６Ａを設けた場合について説明したが、これに限らず、チャネル保護膜２６Ａを省略してもよい。さらに、上記第１〜第４実施形態では、アモルファスシリコンを用いて薄膜トランジスタを形成した場合について説明したが、これに限らず、ポリシリコンを用いて薄膜トランジスタを形成するようにしてもよい。
【００２４】
【発明の効果】
以上説明したように、この発明によれば、ドレイン側及びソース側のＮ型半導体膜とその各上に形成されたドレイン電極及びソース電極との間に良質のシリサイド膜を形成しているので、ドレイン側及びソース側のＮ型半導体膜とその各上に形成されたドレイン電極及びソース電極との間のコンタクト抵抗を小さくすることができ、ひいては寄生抵抗によるオン電流の低下を少なくすることができる。
【図面の簡単な説明】
【図１】（Ａ）はこの発明の第１実施形態における液晶表示パネルの要部の平面図、（Ｂ）はそのＢ−Ｂ線に沿う断面図。
【図２】図１に示す液晶表示パネルの製造に際し、当初の工程を示す断面図。
【図３】図２に続く工程を示す断面図。
【図４】図３に続く工程を示す断面図。
【図５】図４に続く工程を示す断面図。
【図６】図５に続く工程を示す断面図。
【図７】図６に続く工程を示す断面図。
【図８】図７に示す工程においてソース側のＣｒ膜、Ｃｒシリサイド膜及びＮ型半導体膜の端面をソース電極で覆わない場合を説明するために示すものであって、（Ａ）は平面図、（Ｂ）はそのＢ−Ｂ線に沿う断面図。
【図９】図８に示す場合の不都合を説明するために示すものであって、（Ａ）は平面図、（Ｂ）はそのＢ−Ｂ線に沿う断面図。
【図１０】（Ａ）はこの発明の第２実施形態における液晶表示パネルの要部の平面図、（Ｂ）はそのＢ−Ｂ線に沿う断面図。
【図１１】図１０に示す液晶表示パネルの製造に際し、所定の工程を示す断面図。
【図１２】図１１に続く工程を示す断面図。
【図１３】図１２に続く工程を示す断面図。
【図１４】（Ａ）はこの発明の第３実施形態における液晶表示パネルの要部の平面図、（Ｂ）はそのＢ−Ｂ線に沿う断面図。
【図１５】図１４に示す液晶表示パネルの製造に際し、所定の工程を示す断面図。
【図１６】図１５に続く工程を示す断面図。
【図１７】図１６に続く工程を示す断面図。
【図１８】図１７に続く工程を示す断面図。
【図１９】（Ａ）はこの発明の第４実施形態における液晶表示パネルの要部の平面図、（Ｂ）はそのＢ−Ｂ線に沿う断面図。
【図２０】図１９に示す液晶表示パネルの製造に際し、所定の工程を示す断面図。
【図２１】図２０に続く工程を示す断面図。
【図２２】図２１に続く工程を示す断面図。
【図２３】図２２に続く工程を示す断面図。
【図２４】図２３に続く工程を示す断面図。
【図２５】（Ａ）は従来の液晶表示パネルの一例の一部の平面図、（Ｂ）はそのＢ−Ｂ線に沿う断面図。
【図２６】図２５に示す液晶表示パネルの製造に際し、当初の工程を示す断面図。
【図２７】図２６に続く工程を示す断面図。
【図２８】図２７に続く工程を示す断面図。
【符号の説明】
２１ガラス基板
２２ゲート電極
２４ゲート絶縁膜
２５Ａ半導体膜
２６Ａチャネル保護膜
２７Ｄ、２７ＳＮ型半導体膜
２８Ｄ、２８ＳＣｒ膜
２９Ｄ、２９ＳＣｒシリサイド膜
３０画素電極
３４ドレイン電極
３６ソース電極[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display panel such as a liquid crystal display panel and a manufacturing method thereof.
[0002]
[Prior art]
FIG. 25A shows a plan view of a part of an example of a conventional liquid crystal display panel, and FIG. 25B shows a cross-sectional view along the line BB. When manufacturing this liquid crystal display panel, first, as shown in FIG. 26, a gate electrode 2 and a gate line (scanning line) 3 (FIG. 25) made of Al or an Al alloy at predetermined locations on the upper surface of the glass substrate 1. (See (A)), a gate insulating film 4 made of silicon nitride is formed on the upper surface, a semiconductor film 5 made of neutral amorphous silicon is formed on the upper surface, and the gate electrode 2 is formed on the upper surface. A channel protective film 6 made of silicon nitride is formed at a predetermined location above. Next, a natural oxide film (not shown) on the surface of the semiconductor film 5 in a region other than under the channel protective film 6 is removed by surface treatment with an ammonium fluoride solution. Next, as shown in FIG. 27, an N-type semiconductor film 7 made of N-type amorphous silicon is formed on the entire upper surface. Next, as shown in FIG. 28, unnecessary portions of the N-type semiconductor film 7 and the semiconductor film 5 are removed by photolithography. In this state, the semiconductor film 5 A is formed in a portion corresponding to the gate electrode 2, that is, a device area at a predetermined position on the upper surface of the gate insulating film 4. Further, N-type semiconductor films 7D and 7S are formed on both sides of the upper surface of the channel protective film 6 and on the upper surface of the semiconductor film 5A on both sides thereof. Next, as shown in FIGS. 25A and 25B, the source electrode 8 and the pixel electrode 9 made of ITO are formed at predetermined positions on the upper surface of the N-type semiconductor film 7S on the source side and the upper surface of the gate insulating film 4, respectively. Form. Next, a drain electrode 10 and a drain line (signal line) 11 made of Al are formed at other predetermined locations on the upper surface of the drain-side N-type semiconductor film 7D and the upper surface of the gate insulating film 4. In this case, the gate electrode 2, the gate insulating film 4, the semiconductor film 5A, the N-type semiconductor films 7S and 7D, the source electrode 8, and the drain electrode 10 constitute a thin film transistor as a switching element.
[0003]
[Problems to be solved by the invention]
However, in such a conventional method for manufacturing a liquid crystal display panel, between the step of forming the N-type semiconductor film 7 and the step of forming the Al-based metal film for forming the drain electrode 10 and the drain line 11. In addition, there are a step of forming the N-type semiconductor films 7D and 7S and the semiconductor film 5A by photolithography, and a step of forming the ITO film and forming the source electrode 8 and the pixel electrode 9 by photolithography. The surfaces of the type semiconductor films 7D and 7S are easily oxidized and contaminated, the contact resistance between the N type semiconductor films 7D and 7S and the source electrode 8 and the drain electrode 10 is increased, and the on-current of the thin film transistor is reduced. there were.
An object of the present invention is to reduce the contact resistance between the source-side and drain-side N-type semiconductor films and the source electrode and the drain electrode formed thereon.
[0004]
[Means for Solving the Problems]
 The display panel according to claim 1 is a display panel including a thin film transistor and a pixel electrode connected to a source electrode of the thin film transistor. The display panel includes a gate electrode and gate insulation provided on the gate electrode. A film, a semiconductor film provided in a device area on the gate insulating film, an N-type semiconductor film provided on a drain side on the semiconductor film, a silicide film provided on the N-type semiconductor film, A silicidable metal film formed on the silicide film, a drain electrode made of an Al-based metal film formed on the metal film, an N-type semiconductor film provided on the source side of the semiconductor film, A silicide film provided on the N-type semiconductor film, a metal film that can be silicided and is formed on the silicide film and connected to the pixel electrode, and the metal film And an end surface of the N-type semiconductor film on the source side, the silicide film, and the metal film that can be silicidized by the Al-based metal film of the source electrode. It is something that covers. According to a second aspect of the present invention, there is provided a display panel including a thin film transistor and a pixel electrode connected to a source electrode of the thin film transistor. The display panel includes a gate electrode and a gate insulation provided on the gate electrode. A film, a semiconductor film provided in a device area on the gate insulating film, a drain-side and source-side N-type semiconductor film provided on both sides of the semiconductor film on the gate insulating film, and the drain A silicide film provided on the N-type semiconductor film on the side, a silicideable metal film formed on the silicide film, an Al-based metal film formed on the metal film, and the source A silicide film provided on the N-type semiconductor film on the side, and a silicidable gold formed on the silicide film and connected to the pixel electrode And an end surface of the silicide film on the source side and the metal film that can be silicided by the Al-based metal film of the source electrode. It is something that covers. The display panel according to claim 3 is a display panel including a thin film transistor and a pixel electrode connected to a source electrode of the thin film transistor. The thin film transistor includes a gate electrode and gate insulation provided on the gate electrode. A film, a semiconductor film provided in a device area on the gate insulating film, an N-type semiconductor film provided on a drain side on the semiconductor film, a silicide film provided on the N-type semiconductor film, A silicidable metal film formed on the silicide film, a drain electrode made of an Al-based metal film formed on the metal film, an N-type semiconductor film provided on the source side of the semiconductor film, A silicide film provided on the N-type semiconductor film, a metal film capable of silicidation formed on the silicide film, and the pixel formed on the metal film And the source electrode made of the same conductive material as the pixel electrode, and the N-type semiconductor film on the source side, the silicide film, and the silicide can be made by the conductive material of the source electrode The end face of the metal film is covered. According to a fourth aspect of the present invention, there is provided a display panel manufacturing method comprising: forming a gate electrode, a gate insulating film, a semiconductor film, an N-type semiconductor film, and a metal film capable of silicidation in this order on a substrate; Forming a silicide film at the interface between the film and the metal film; peeling the refractory metal film capable of silicidation leaving the silicide film; and the drain side and the source side on the semiconductor film A step of leaving the N-type semiconductor film and the silicide film, a step of forming a pixel electrode made of ITO connected to the silicide film on the source side, and a source / drain electrode formed of an Al-based metal film on the entire upper surface A protective metal film made of Cr for preventing the battery reaction between the metal film and the Al-based metal film and the pixel electrode during wet etching is formed in this order, By patterning these metal films by wet etching, a drain electrode is formed on the drain-side silicide film, the protective metal film is left on the drain electrode, and the source electrode is formed on the source-side silicide film. Forming the protective metal film thereon, and then removing the remaining protective metal film. According to a fifth aspect of the present invention, there is provided a display panel manufacturing method comprising: forming a gate electrode, a gate insulating film, and a semiconductor film on a substrate in this order; and forming a channel protective film at a predetermined location on the semiconductor film. Then, by implanting N-type ions into the semiconductor film using the channel protective film as a mask, the semiconductor film in a region other than under the channel protective film is made an N-type semiconductor film, and on the N-type semiconductor film Forming a silicide-capable metal film to form a silicide film at an interface between the N-type semiconductor film and the metal film; and removing the silicide-capable refractory metal film leaving the silicide film A step of forming a pixel electrode made of ITO connected to the silicide film on the source side, a metal film for forming source / drain electrodes made of an Al-based metal film on the entire upper surface, and A protective metal film made of Cr for preventing the battery reaction between the Al-based metal film and the pixel electrode during wet etching is formed in this order, and these metal films are patterned by wet etching. A drain electrode is formed on the drain-side silicide film, the protective metal film is left on the drain electrode, and a source electrode is formed on the source-side silicide film and the protective metal is formed thereon. And a step of leaving the film and then peeling off the remaining protective metal film. According to a sixth aspect of the present invention, there is provided a display panel manufacturing method comprising: a step of forming a gate electrode, a gate insulating film, and a semiconductor film on a substrate in this order; and an N-type semiconductor on the drain side and the source side on the semiconductor film. Forming a film on the N-type semiconductor film, forming a silicide film on the interface between the N-type semiconductor film and the metal film, and forming a silicide film on the source side. Connected to metal filmMade of ITOA step of forming a pixel electrode, a metal film for forming a source / drain electrode made of an Al-based metal film on the entire upper surface, and a cell reaction between the Al-based metal film and the pixel electrode during wet etching.C r Consist ofA protective metal film is formed in this order, and these metal films are wet-etched so that the source electrode forming metal film made of the Al-based metal film is the N-type semiconductor film on the source side, the silicide A drain electrode made of an Al-based metal film is formed on the drain-side metal film by patterning so as to cover an end face of the film and the silicidable metal film, and the N-type semiconductor film on the source side Forming a source electrode made of an Al-based metal film that covers end surfaces of the silicide film and the metal film that can be silicidized. According to a seventh aspect of the present invention, there is provided a display panel manufacturing method comprising: forming a gate electrode, a gate insulating film, and a semiconductor film in this order on a substrate; and forming a channel protective film at a predetermined location on the semiconductor film. Then, by implanting N-type ions into the semiconductor film using the channel protective film as a mask, the semiconductor film in the drain and source regions other than under the channel protective film is made an N-type semiconductor film, and the N-type semiconductor Forming a silicide-capable metal film on the film to form a silicide film at an interface between the N-type semiconductor film and the metal film; and connecting to the source-side metal filmMade of ITOA step of forming a pixel electrode, a metal film for forming a source / drain electrode made of an Al-based metal film on the entire upper surface, and a cell reaction between the Al-based metal film and the pixel electrode during wet etching.C r Consist ofA protective metal film is formed in this order, and these metal films are wet-etched so that the source electrode forming metal film made of the Al-based metal film is the N-type semiconductor film on the source side, the silicide A drain electrode made of an Al-based metal film is formed on the drain side metal film by patterning so as to cover an end face of the film and the silicidable metal film, and the source side silicide film and the source film Forming a source electrode made of an Al-based metal film that covers the end face of the metal film that can be silicided. The method for manufacturing a display panel according to claim 8 includes a step of forming a gate electrode, a gate insulating film, and a semiconductor film on a substrate in this order, and an N-type semiconductor on the drain side and the source side on the semiconductor film. Forming a film on the N-type semiconductor film, forming a silicide film on the interface between the N-type semiconductor film and the metal film, and forming a silicide film on the source side. Connected to metal filmMade of ITOForming a pixel electrode, and forming a source electrode that covers an end surface of the N-type semiconductor film on the source side, the silicide film, and the metal film that can be silicided with the same conductive material as the pixel electrode; A source / drain electrode forming metal film composed entirely of an Al-based metal film and a battery reaction between the Al-based metal film and the pixel electrode during wet etching.C r Consist ofA step of forming protective metal films in this order, and patterning these metal films by wet etching, and removing unnecessary portions, thereby forming a drain made of an Al-based metal film on the metal film on the drain side. Forming an electrode. According to a ninth aspect of the present invention, there is provided a display panel manufacturing method comprising: forming a gate electrode, a gate insulating film, and a semiconductor film on a substrate in this order; and forming a channel protective film at a predetermined location on the semiconductor film. And using the channel protective film as a mask, implanting N-type ions into the semiconductor film to make the semiconductor film in the source and drain regions other than the channel protective film an N-type semiconductor film, and the N-type semiconductor Forming a silicide-capable metal film on the film to form a silicide film at an interface between the N-type semiconductor film and the metal film; and connecting to the source-side metal filmMade of ITOForming a pixel electrode, forming a source electrode covering the source-side silicide film and the end surface of the silicidable metal film with the same conductive material as the pixel electrode, and an Al-based metal film over the entire upper surface The source / drain electrode forming metal film and the Al-based metal film and the pixel electrode are prevented from causing a battery reaction during wet etching.C r Consist ofA step of forming protective metal films in this order, and patterning these metal films by wet etching, and removing unnecessary portions, thereby forming a drain made of an Al-based metal film on the metal film on the drain side. Forming an electrode. According to the above invention, since the high-quality silicide film is formed between the drain-side and source-side N-type semiconductor films and the drain electrode and the source electrode formed thereon, The contact resistance between the N-type semiconductor film on the source side and the drain electrode and the source electrode formed thereon can be reduced.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1A is a plan view of the main part of the liquid crystal display panel according to the first embodiment of the present invention, and FIG. 1B is a sectional view taken along the line BB. When manufacturing this liquid crystal display panel, first, as shown in FIG. 2, an Al-based metal film made of Al or Al alloy formed by sputtering at a predetermined position on the upper surface of the glass substrate 21 is photolithography. A gate electrode 22 and a gate line (scanning line) 23 (see FIG. 1A) are formed by processing into a predetermined pattern by a method (hereinafter referred to as a PL method). Next, a gate insulating film 24 made of silicon nitride, a semiconductor film 25 made of neutral amorphous silicon, and a channel protective film forming film 26 made of silicon nitride are successively formed on the entire upper surface by CVD. Next, the channel protection film formation film 26 is processed into a predetermined pattern by the PL method, thereby forming a channel protection film 26 A at a predetermined position on the gate electrode 22 on the upper surface of the semiconductor film 25. Next, a natural oxide film (not shown) on the surface of the semiconductor film 25 in a region other than under the channel protective film 26A is removed by surface treatment with an ammonium fluoride solution.
[0006]
Next, as shown in FIG. 3, an N-type semiconductor film 27 made of N-type amorphous silicon is formed on the entire upper surface by CVD. Next, the natural oxide film (not shown) on the surface of the N-type semiconductor film 27 is removed by surface treatment with an ammonium fluoride solution. Next, a Cr film 28 is formed on the upper surface of the N-type semiconductor film 27 by sputtering. Then, since the interface between the N-type semiconductor film 27 and the Cr film 28 is clean, a high-quality Cr silicide film 29 is formed at the interface between the N-type semiconductor film 27 and the Cr film 28. Next, as shown in FIG. 4, unnecessary portions of the Cr film 28, the Cr silicide film 29, the N-type semiconductor film 27, and the semiconductor film 25 are removed by a PL method. In this state, the semiconductor film 25 A is formed in a portion corresponding to the gate electrode 22 at a predetermined position on the upper surface of the gate insulating film 24, that is, in the device area. N-type semiconductor films 29D and 29S, Cr silicide films 29D and 29S, and Cr films 28D and 28S are formed on both sides of the upper surface of the channel protective film 26A and on the upper surface of the semiconductor film 25A on both sides thereof.
[0007]
Next, as shown in FIG. 5, a transparent metal film made of transparent ITO (indium-tin oxide) or the like formed by sputtering is processed into a predetermined pattern by PL, so that Cr on the source side is processed. Pixel electrodes 30 are formed at predetermined locations on the upper surface of the film 28 S and at predetermined locations on the upper surface of the gate insulating film 24. Next, as shown in FIG. 6, an Al-based metal film 31 and a protective Cr film 32 are successively formed on the entire upper surface by sputtering. Next, resist films 33D and 33S for forming a drain electrode, a drain line (signal line), and a source electrode are formed at predetermined locations on the upper surface of the protective Cr film 32. In this case, the size of the resist film 33D on the Cr film 28D is the same as the size of the Cr film 28D, but the size of the resist film 33S is larger than the size of the Cr film 28S by a predetermined size. The protective Cr film 32 is for preventing the pixel electrode 30 made of ITO and the Al-based metal film 31 from being corroded by a battery reaction during resist development.
[0008]
Next, as shown in FIG. 7, unnecessary portions of the protective Cr film 32 and the Al-based metal film 31 are removed by performing wet etching using the resist films 33D and 33S as a mask. Next, the resist films 33D and 33S are peeled off. Next, the protective Cr film 32 is removed by wet etching. Then, as shown in FIGS. 1A and 1B, the drain electrode 34 and the drain line 35 made of the Al-based metal film 31 are formed at predetermined positions on the upper surface of the Cr film 28D and the upper surface of the gate insulating film 24. The Further, the source electrode 36 made of the Al-based metal film 31 is formed on the upper surface of the Cr film 28S and a predetermined portion around it. In this case, end faces of the Cr film 28S, the Cr silicide film 29S, and the N-type semiconductor film 27S are covered with the source electrode 36. The reason for this will be described later. The gate electrode 22, the semiconductor film 25A, the N-type semiconductor films 27D and 27S, the Cr silicide films 29D and 29S, the Cr films 28D and 28S, the drain electrode 34, and the source electrode 36 constitute a thin film transistor as a switching element. .
[0009]
Here, the reason why the end faces of the source-side Cr film 28S, Cr silicide film 29S, and N-type semiconductor film 27S are covered with the source electrode 36 will be described. First, as shown in FIGS. 8A and 8B, when the predetermined three end faces a, b, c of the resist film 33S coincide with the predetermined three end faces of the Cr film 28S, the resist film 33S is used. When unnecessary portions of the protective Cr film 32 and the Al-based metal film 31 are removed by performing wet etching using as a mask, three predetermined end faces of the Cr film 28D are exposed. In this state, after removing the resist films 33D and 33S, when the protective Cr film 32 is removed by wet etching, the pixel electrode 30 made of ITO and the Cr film 28D are connected. As shown in FIGS. 9A and 9B, the side etching of the Cr film 28S proceeds violently due to the Cr-based battery reaction, and decreases to about 1/3 in about 10 seconds. In such a case, contact characteristics on the source side deteriorate, which is not preferable. Therefore, as shown in FIG. 7, when the end surfaces of the Cr film 28S, Cr silicide film 29S, and N-type semiconductor film 27S on the source side are covered with the source electrode 36, side etching of the Cr film 28S is prevented.
[0010]
In the liquid crystal display panel manufactured as described above, high-quality Cr silicide films 29D, 29S and N-type semiconductor films 27D, 27S and a drain electrode 34 and a source electrode 36 formed on each of them are provided. Since the Cr films 28D and 28S are formed, the contact resistance between the N-type semiconductor films 27D and 27S and the drain electrode 34 and the source electrode 36 formed on each of the N-type semiconductor films 27D and 27S can be reduced. The decrease in the on-current due to can be reduced.
[0011]
(Second Embodiment)
FIG. 10A shows a plan view of the main part of the liquid crystal display panel according to the second embodiment of the present invention, and FIG. 10B shows a cross-sectional view along the line BB. When manufacturing this liquid crystal display panel, the steps up to the steps shown in FIGS. 2 to 4 are the same as those in the case of the first embodiment, and the subsequent steps will be described. As shown in FIG. 11, an ITO film formed by sputtering at a predetermined position on the upper surface of the source-side Cr film 28S and its surroundings and at a predetermined position on the upper surface of the gate insulating film 24 has a predetermined pattern by the PL method. Thus, the source electrode 36 and the pixel electrode 30 are formed. In this case, predetermined three end faces of the Cr film 28S, the Cr silicide film 29S, and the N-type semiconductor film 27S are covered with the source electrode 36, and the remaining one end face is covered with the pixel electrode 30. Next, as shown in FIG. 12, an Al-based metal film 31 and a protective Cr film 32 are successively formed on the entire upper surface by sputtering. Next, a resist film 33 D for forming a drain electrode and a drain line is formed at a predetermined position on the upper surface of the protective Cr film 32. In this case, the size of the resist film 33D on the Cr film 28D is the same as the size of the Cr film 28D. The protective Cr film 32 is for preventing the pixel electrode 30 made of ITO and the Al-based metal film 31 from being corroded by a battery reaction during resist development.
[0012]
Next, as shown in FIG. 13, unnecessary portions of the protective Cr film 32 and the Al-based metal film 31 are removed by performing wet etching using the resist film 33D as a mask. Next, the resist film 33D is peeled off. Next, the protective Cr film 32 is removed by wet etching. Then, as shown in FIGS. 10A and 10B, the drain electrode 34 and the drain line 35 made of the Al-based metal film 31 are formed at predetermined positions on the upper surface of the Cr film 28D and the upper surface of the gate insulating film 24. The In this case, since the end surfaces of the Cr film 28S, the Cr silicide film 29S, and the N-type semiconductor film 27S are covered with the source electrode 36 made of ITO, side etching of the Cr film 28S is prevented.
[0013]
Even in the liquid crystal display panel manufactured as described above, high-quality Cr silicide films 29D, 29S and N-type semiconductor films 27D, 27S and a drain electrode 34 and a source electrode 36 formed thereon are provided. Since the Cr films 28D and 28S are formed, the contact resistance between the N-type semiconductor films 27D and 27S and the drain electrode 34 and the source electrode 36 formed on each of the N-type semiconductor films 27D and 27S can be reduced. The decrease in the on-current due to can be reduced.
[0014]
(Third embodiment)
FIG. 14A shows a plan view of the main part of a liquid crystal display panel according to the third embodiment of the present invention, and FIG. 14B shows a cross-sectional view along the line BB. When manufacturing this liquid crystal display panel, the steps up to the steps shown in FIGS. 2 to 3 are the same as in the case of the first embodiment, and the subsequent steps will be described. As shown in FIG. 15, the Cr film 28 shown in FIG. 3 is peeled off by wet etching. Next, as shown in FIG. 16, unnecessary portions of the Cr silicide film 29, the N-type semiconductor film 27, and the semiconductor film 25 are removed by a PL method. In this state, the semiconductor film 25 A is formed in a portion corresponding to the gate electrode 22 at a predetermined position on the upper surface of the gate insulating film 24, that is, in the device area. N-type semiconductor films 27D and 27S and Cr silicide films 29D and 29S are formed on both sides of the upper surface of the channel protective film 26A and on the upper surface of the semiconductor film 25A on both sides thereof.
[0015]
Next, as shown in FIG. 17, the ITO film formed by the sputtering method is processed into a predetermined pattern by the PL method, so that a predetermined portion of the upper surface of the source-side Cr silicide film 29S and the gate insulating film 24 are formed. A pixel electrode 30 is formed at a predetermined location on the upper surface. Next, an Al metal film 31 and a protective Cr film 32 are successively formed on the entire upper surface by sputtering. Next, resist films 33D and 33S for forming a drain electrode, a drain line (signal line), and a source electrode are formed at predetermined locations on the upper surface of the protective Cr film 32. In this case, the size of the resist film 33D on the Cr silicide film 29D is the same as the size of the Cr silicide film 29D, and the size of the resist film 33S on the Cr silicide film 29S is also the same as the size of the Cr silicide film 29S. It has become. The protective Cr film 32 is for preventing the pixel electrode 30 made of ITO and the Al-based metal film 31 from being corroded by a battery reaction during resist development.
[0016]
Next, as shown in FIG. 18, unnecessary portions of the protective Cr film 32 and the Al-based metal film 31 are removed by performing wet etching using the resist films 33D and 33S as a mask. Next, the resist films 33D and 33S are peeled off. Next, the protective Cr film 32 is removed by wet etching. Then, as shown in FIGS. 14A and 14B, the drain electrode 34 and the drain line 35 made of the Al-based metal film 31 are formed at predetermined positions on the upper surface of the Cr silicide film 29D and the upper surface of the gate insulating film 24. Is done. In addition, a source electrode 36 made of an Al-based metal film 31 is formed at predetermined locations on the upper surface of the Cr silicide film 29S and the upper surface of the pixel electrode 30. The gate electrode 22, the semiconductor film 25A, the N-type semiconductor films 27D and 27S, the Cr silicide films 29D and 29S, the drain electrode 34, and the source electrode 36 constitute a thin film transistor as a switching element.
[0017]
In the liquid crystal display panel manufactured as described above, high-quality Cr silicide films 29D and 29S are provided between the N-type semiconductor films 27D and 27S and the drain electrode 34 and the source electrode 36 formed thereon. Thus, the contact resistance between the N-type semiconductor films 27D and 27S and the drain electrode 34 and the source electrode 36 formed thereon can be reduced, and the on-current can be reduced due to parasitic resistance. Can be reduced.
[0018]
 (referenceEmbodiment)
 FIG. 19A shows a plan view of the main part of a liquid crystal display panel according to the fourth embodiment of the present invention, and FIG. 19B shows a cross-sectional view along the line BB. When the liquid crystal display panel is manufactured, the steps up to that shown in FIG. 2 are the same as those in the first embodiment, and the subsequent steps will be described. As shown in FIG. 20, a Cr film 28 is formed on the entire upper surface by sputtering. Then, since the interface between the semiconductor film 25 and the Cr film 28 in the region other than under the channel protective film 26A is clean, a good quality Cr is formed at the interface between the semiconductor film 25 and the Cr film 28 in the region other than under the channel protective film 26A. A silicide film 29 is formed. Next, as shown in FIG. 21, N-type ions such as phosphorus ions are implanted using the channel protective film 26A as a mask. The implanted N-type ions are injected into the Cr film 28 and also penetrate the Cr film 28 and the Cr silicide film 29 and are injected into the semiconductor film 25 in a region other than under the channel protective film 26A. As a result, the film quality of the Cr film 28 is improved by N-type ion implantation. A semiconductor film 25A made of neutral amorphous silicon is formed under the channel protective film 26A, and an N-type semiconductor film 27 made of N-type amorphous silicon is formed under the Cr silicide film 29.
[0019]
Next, as shown in FIG. 22, unnecessary portions of the Cr film 28, the Cr silicide film 29, and the N-type semiconductor film 27 are removed by a PL method. In this state, the semiconductor film 25A and the N-type semiconductor films 27D and 27S are formed in a portion corresponding to the gate electrode 22 at a predetermined position on the upper surface of the gate insulating film 24, that is, in the device area. In addition, Cr silicide films 29D and 29S are formed on the upper surfaces of the N-type semiconductor films 27D and 27S. Further, Cr films 28D and 28S are formed on both sides of the upper surface of the channel protective film 26A and on the upper surfaces of the Cr silicide films 29D and 29S.
[0020]
Next, as shown in FIG. 23, the ITO film formed by the sputtering method is processed into a predetermined pattern by the PL method, so that a predetermined location on the upper surface of the Cr film 28S on the source side and the upper surface of the gate insulating film 24 are obtained. The pixel electrode 30 is formed at a predetermined location. Next, an Al metal film 31 and a protective Cr film 32 are successively formed on the entire upper surface by sputtering. Next, resist films 33D and 33S for forming a drain electrode, a drain line (signal line), and a source electrode are formed at predetermined locations on the upper surface of the protective Cr film 32. In this case, the size of the resist film 33D on the Cr film 28D is the same as the size of the Cr film 28D, and the size of the resist film 33S on the Cr film 28S is the same as the size of the Cr film 28S. The protective Cr film 32 is for preventing the pixel electrode 30 made of ITO and the Al-based metal film 31 from being corroded by a battery reaction during resist development.
[0021]
Next, as shown in FIG. 24, unnecessary portions of the protective Cr film 32 and the Al-based metal film 31 are removed by performing wet etching using the resist films 33D and 33S as a mask. Next, the resist films 33D and 33S are peeled off. Next, the protective Cr film 32 is removed by wet etching. Then, as shown in FIGS. 19A and 19B, the drain electrode 34 and the drain line 35 made of the Al-based metal film 31 are formed at predetermined positions on the upper surface of the Cr film 28D and the upper surface of the gate insulating film 24. The Further, a source electrode 36 made of an Al-based metal film 31 is formed at predetermined locations on the upper surface of the Cr film 28S and the upper surface of the pixel electrode 30. In this case, the end face of the Cr film 28S is not covered with the source electrode 36, but the film quality of the Cr film 28 is modified by the implantation of N-type ions, so that side etching of the Cr film 28S is prevented. The gate electrode 22, the semiconductor film 25A, the N-type semiconductor films 27D and 27S, the Cr silicide films 29D and 29S, the Cr films 28D and 28S, the drain electrode 34, and the source electrode 36 constitute a thin film transistor as a switching element. .
[0022]
Even in the liquid crystal display panel manufactured as described above, high-quality Cr silicide films 29D, 29S and N-type semiconductor films 27D, 27S and a drain electrode 34 and a source electrode 36 formed thereon are provided. Since the Cr films 28D and 28S are formed, the contact resistance between the N-type semiconductor films 27D and 27S and the drain electrode 34 and the source electrode 36 formed on each of the N-type semiconductor films 27D and 27S can be reduced. The decrease in the on-current due to can be reduced.
[0023]
In the first to third embodiments, the case where the N-type semiconductor films 27D and 27S are formed on both sides of the upper surface of the semiconductor film 25A has been described. However, the present invention is not limited to this. For example, in FIG. 2, an N-type semiconductor film may be formed in a region other than the channel protective film 26A by implanting N-type ions such as phosphorus ions into the semiconductor film 25 using the channel protective film 26A as a mask. In the first to third embodiments, the case where the channel protective film 26A is provided has been described. However, the present invention is not limited to this, and the channel protective film 26A may be omitted. Further, in the first to fourth embodiments, the case where the thin film transistor is formed using amorphous silicon has been described. However, the present invention is not limited to this, and the thin film transistor may be formed using polysilicon.
[0024]
【The invention's effect】
As described above, according to the present invention, a high-quality silicide film is formed between the drain-side and source-side N-type semiconductor films and the drain electrode and the source electrode formed thereon, The contact resistance between the drain-side and source-side N-type semiconductor films and the drain electrode and the source electrode formed on each of them can be reduced, so that a decrease in on-current due to parasitic resistance can be reduced. .
[Brief description of the drawings]
FIG. 1A is a plan view of a main part of a liquid crystal display panel according to a first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line BB.
FIG. 2 is a cross-sectional view showing an initial process in manufacturing the liquid crystal display panel shown in FIG.
3 is a cross-sectional view showing a step that follows FIG. 2. FIG.
4 is a cross-sectional view showing a step that follows FIG. 3. FIG.
FIG. 5 is a sectional view showing a step following FIG.
6 is a cross-sectional view showing a step that follows FIG. 5. FIG.
7 is a cross-sectional view showing a step that follows FIG. 6. FIG.
8 is a view for explaining a case where end surfaces of a source-side Cr film, a Cr silicide film, and an N-type semiconductor film are not covered with a source electrode in the step shown in FIG. 7; FIG. (B) is sectional drawing which follows the BB line.
FIGS. 9A and 9B are views for explaining inconveniences in the case shown in FIG. 8, wherein FIG. 9A is a plan view, and FIG. 9B is a cross-sectional view taken along the line BB.
10A is a plan view of a main part of a liquid crystal display panel according to a second embodiment of the present invention, and FIG. 10B is a cross-sectional view taken along line BB.
11 is a cross-sectional view showing a predetermined step in manufacturing the liquid crystal display panel shown in FIG.
12 is a cross-sectional view showing a step that follows FIG.
13 is a cross-sectional view showing a step that follows the step shown in FIG. 12. FIG.
14A is a plan view of a main part of a liquid crystal display panel according to a third embodiment of the present invention, and FIG. 14B is a cross-sectional view taken along the line BB.
15 is a cross-sectional view showing a predetermined process in manufacturing the liquid crystal display panel shown in FIG. 14;
16 is a cross-sectional view showing a step that follows the step of FIG.
17 is a cross-sectional view showing a step that follows FIG. 16. FIG.
18 is a cross-sectional view showing a step that follows FIG.
FIG. 19A is a plan view of an essential part of a liquid crystal display panel according to a fourth embodiment of the present invention, and FIG. 19B is a sectional view taken along line BB.
20 is a cross-sectional view showing a predetermined process in manufacturing the liquid crystal display panel shown in FIG. 19;
21 is a cross-sectional view showing a step that follows FIG. 20. FIG.
22 is a cross-sectional view showing a step that follows the step shown in FIG. 21. FIG.
FIG. 23 is a cross-sectional view showing a step that follows the step shown in FIG.
24 is a cross-sectional view showing a step that follows the step shown in FIG. 23. FIG.
25A is a plan view of a part of an example of a conventional liquid crystal display panel, and FIG. 25B is a cross-sectional view taken along the line BB.
26 is a cross-sectional view showing an initial step in manufacturing the liquid crystal display panel shown in FIG. 25. FIG.
27 is a cross-sectional view showing a step that follows FIG. 26. FIG.
28 is a cross-sectional view showing a step that follows FIG. 27. FIG.
[Explanation of symbols]
21 Glass substrate
22 Gate electrode
24 Gate insulation film
25A semiconductor film
26A channel protective film
27D, 27S N-type semiconductor film
28D, 28S Cr film
29D, 29S Cr silicide film
30 pixel electrode
34 Drain electrode
36 Source electrode

Claims

In a display panel comprising a thin film transistor and a pixel electrode connected to the source electrode of the thin film transistor,
The thin film transistor
A gate electrode;
A gate insulating film provided on the gate electrode;
A semiconductor film provided in a device area on the gate insulating film;
An N-type semiconductor film provided on the drain side of the semiconductor film;
A silicide film provided on the N-type semiconductor film;
A drain electrode comprising a metal film capable of silicidation formed on the silicide film and an Al-based metal film formed on the metal film;
An N-type semiconductor film provided on the source side on the semiconductor film;
A silicide film provided on the N-type semiconductor film;
A source electrode comprising a metal film capable of silicidation formed on the silicide film and connected to the pixel electrode, and an Al-based metal film formed on the metal film;
Composed by
An end panel of the N-type semiconductor film on the source side, the silicide film, and the metal film capable of silicidation is covered with an Al-based metal film of the source electrode.

In a display panel comprising a thin film transistor and a pixel electrode connected to the source electrode of the thin film transistor,
The thin film transistor
A gate electrode;
A gate insulating film provided on the gate electrode;
A semiconductor film provided in a device area on the gate insulating film;
A drain-side and source-side N-type semiconductor film provided on both sides of the semiconductor film on the gate insulating film;
A silicide film provided on the drain-side N-type semiconductor film;
A drain electrode comprising a metal film capable of silicidation formed on the silicide film and an Al-based metal film formed on the metal film;
A silicide film provided on the N-type semiconductor film on the source side;
A source electrode comprising a metal film capable of silicidation formed on the silicide film and connected to the pixel electrode, and an Al-based metal film formed on the metal film;
Composed by
The display panel, wherein an end face of the silicide film on the source side and the metal film capable of silicidation is covered with an Al-based metal film of the source electrode.

In a display panel comprising a thin film transistor and a pixel electrode connected to the source electrode of the thin film transistor,
The thin film transistor
A gate electrode;
A gate insulating film provided on the gate electrode;
A semiconductor film provided in a device area on the gate insulating film;
An N-type semiconductor film provided on the drain side of the semiconductor film;
A silicide film provided on the N-type semiconductor film;
A drain electrode comprising a metal film capable of silicidation formed on the silicide film and an Al-based metal film formed on the metal film;
An N-type semiconductor film provided on the source side on the semiconductor film;
A silicide film provided on the N-type semiconductor film;
A source electrode made of the same conductive material as the pixel electrode, connected to the silicidable metal film formed on the silicide film and the pixel electrode formed on the metal film;
Composed by
The display panel, wherein the conductive material of the source electrode covers end surfaces of the N-type semiconductor film on the source side, the silicide film, and the metal film that can be silicided.

Forming a gate electrode, a gate insulating film, a semiconductor film, an N-type semiconductor film and a metal film capable of silicidation in this order on a substrate and forming a silicide film at an interface between the N-type semiconductor film and the metal film; When,
Peeling the refractory metal film capable of silicidation leaving the silicide film;
Leaving the N-type semiconductor film and the silicide film on the drain side and the source side on the semiconductor film;
Forming a pixel electrode made of ITO connected to the silicide film on the source side;
A source / drain electrode forming metal film made of an Al-based metal film on the entire upper surface and a protective metal film made of Cr for preventing the Al-based metal film and the pixel electrode from causing a battery reaction during wet etching. By depositing in this order, and patterning these metal films by wet etching, a drain electrode is formed on the drain-side silicide film, the protective metal film is left on the drain electrode, and the source-side film is formed. Forming a source electrode on the silicide film and leaving the protective metal film on the source electrode, and then peeling off the remaining protective metal film;
A method for manufacturing a display panel, comprising:

Forming a gate electrode, a gate insulating film and a semiconductor film in this order on the substrate;
A channel protective film is formed at a predetermined position on the semiconductor film, and N-type ions are implanted into the semiconductor film using the channel protective film as a mask, so that the semiconductor film in a region other than the region under the channel protective film is N-type. A step of forming a semiconductor film;
Forming a silicide-capable metal film on the N-type semiconductor film and forming a silicide film at an interface between the N-type semiconductor film and the metal film;
Peeling the refractory metal film capable of silicidation leaving the silicide film;
Forming a pixel electrode made of ITO connected to the silicide film on the source side;
A source / drain electrode forming metal film made of an Al-based metal film on the entire upper surface and a protective metal film made of Cr for preventing the Al-based metal film and the pixel electrode from causing a battery reaction during wet etching. By depositing in this order, and patterning these metal films by wet etching, a drain electrode is formed on the drain-side silicide film, the protective metal film is left on the drain electrode, and the source-side film is formed. Forming a source electrode on the silicide film and leaving the protective metal film on the source electrode, and then peeling off the remaining protective metal film;
A method for manufacturing a display panel, comprising:

Forming a gate electrode, a gate insulating film and a semiconductor film in this order on the substrate;
Forming an N-type semiconductor film on the drain side and the source side on the semiconductor film;
Forming a silicide-capable metal film on the N-type semiconductor film and forming a silicide film at an interface between the N-type semiconductor film and the metal film;
Forming a pixel electrode made of ITO connected to the metal film on the source side;
Protecting metal film on the entire upper surface and the Al-based metal film at Al-based metal film for the source and drain electrodes formed made of a metal film and wet etching and the pixel electrode is made of C r for preventing causing cell reaction A film forming process in this order;
These metal films are wet-etched so that the source electrode forming metal film made of the Al-based metal film covers the end surfaces of the N-type semiconductor film, the silicide film, and the metal film that can be silicided on the source side. The drain electrode made of an Al-based metal film is formed on the drain-side metal film, and the end surface of the N-type semiconductor film on the source side, the silicide film, and the metal film that can be silicided Forming a source electrode made of an Al-based metal film covering the substrate;
A method for manufacturing a display panel, comprising:

Forming a gate electrode, a gate insulating film and a semiconductor film in this order on the substrate;
Forming a channel protective film at a predetermined location on the semiconductor film, and implanting N-type ions into the semiconductor film using the channel protective film as a mask, so that the semiconductor film in the drain and source regions other than under the channel protective film Forming an N-type semiconductor film,
Forming a silicide-capable metal film on the N-type semiconductor film and forming a silicide film at an interface between the N-type semiconductor film and the metal film;
Forming a pixel electrode made of ITO connected to the metal film on the source side;
Protecting metal film on the entire upper surface and the Al-based metal film at Al-based metal film for the source and drain electrodes formed made of a metal film and wet etching and the pixel electrode is made of C r for preventing causing cell reaction A film forming process in this order;
These metal films are wet-etched so that the source electrode forming metal film made of the Al-based metal film covers the end surfaces of the N-type semiconductor film, the silicide film, and the metal film that can be silicided on the source side. The drain electrode made of an Al-based metal film is formed on the drain-side metal film, and the source-side silicide film and an Al-based metal film covering the end surfaces of the silicidable metal film are formed by patterning Forming a source electrode comprising:
A method for manufacturing a display panel, comprising:

Forming a gate electrode, a gate insulating film and a semiconductor film in this order on the substrate;
Forming an N-type semiconductor film on the drain side and the source side on the semiconductor film;
Forming a silicide-capable metal film on the N-type semiconductor film and forming a silicide film at an interface between the N-type semiconductor film and the metal film;
A pixel electrode made of ITO connected to the metal film on the source side is formed, and the N-type semiconductor film on the source side, the silicide film, and the metal film that can be silicidized by the same conductive material as the pixel electrode Forming a source electrode covering the end face of
Protecting metal film on the entire upper surface and the Al-based metal film at Al-based metal film for the source and drain electrodes formed made of a metal film and wet etching and the pixel electrode is made of C r for preventing causing cell reaction A film forming process in this order;
Forming a drain electrode made of an Al-based metal film on the metal film on the drain side by patterning these metal films by wet etching and removing unnecessary portions;
A method for manufacturing a display panel, comprising:

Forming a gate electrode, a gate insulating film and a semiconductor film in this order on the substrate;
Forming a channel protective film at a predetermined location on the semiconductor film, and implanting N-type ions into the semiconductor film using the channel protective film as a mask, thereby providing the semiconductor film in the source and drain regions other than the channel protective film. Forming an N-type semiconductor film,
Forming a silicide-capable metal film on the N-type semiconductor film and forming a silicide film at an interface between the N-type semiconductor film and the metal film;
Forming a pixel electrode made of ITO connected to the metal film on the source side, and covering the end surface of the silicide film on the source side and the metal film capable of silicidation with the same conductive material as the pixel electrode Forming a step;
Protecting metal film on the entire upper surface and the Al-based metal film at Al-based metal film for the source and drain electrodes formed made of a metal film and wet etching and the pixel electrode is made of C r for preventing causing cell reaction A film forming process in this order;
Forming a drain electrode made of an Al-based metal film on the metal film on the drain side by patterning these metal films by wet etching and removing unnecessary portions;
A method for manufacturing a display panel, comprising: