KR100552296B1 - Manufacturing Method of Polycrystalline Silicon Thin Film Transistor Board - Google Patents

Abstract

After depositing amorphous silicon on the insulating substrate and crystallizing to form a polycrystalline silicon layer, a gate insulating layer is deposited with silicon oxide or silicon nitride, and then a molybdenum or molybdenum alloy film and an ITO (indium-tim-oxide) film in that order Deposit. Next, using a mask having a lattice pattern, a photoresist pattern of which the edge portion is thinner than the thickness of the center portion is formed on the upper part of the ITO film, and dry etching to form a thin portion of the photoresist pattern, the ITO film, the molybdenum film, and the gate insulation. The layer is etched to form a double gate metal pattern and a stepped gate insulation pattern. Next, when ions are implanted using the gate insulating pattern as a mask, source and drain regions and low concentration LDD regions are simultaneously formed in the polysilicon layer due to the difference in thickness of the gate insulating pattern.

Description

Polycrystalline Silicon Thin Film Transistor Substrate and Manufacturing Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a polycrystalline silicon thin film transistor substrate, and more particularly, to a method of forming an offset and lightly doped drain (LDD) structure in a polycrystalline silicon layer.

The thin film transistor liquid crystal display is a display device in which a liquid crystal material is injected between a thin film transistor substrate on which a thin film transistor, a data line, a gate line, and the like are formed, and a substrate on which a color filter and a transparent common electrode are formed. Thin film transistors are used as elements for displacing materials.

The semiconductor layer of this thin film transistor is mainly formed using amorphous or polycrystalline silicon.

Amorphous silicon can be deposited at low temperatures and has excellent off current characteristics, but its mobility is less than 1 cm ³ / V · sec and is mainly used to form switching elements in liquid crystal displays. In addition, the driving circuit forms a separate IC (IC) and is mounted around. As the module process increases, the process cost increases.

On the other hand, since polycrystalline silicon has a greater mobility of 50 cm ³ / V · sec or more than amorphous silicon, it is possible to integrate a driving circuit in a substrate at the same time as forming a pixel portion, thereby reducing the cost of driving IC materials and related process equipment. Can be reduced. In addition, power consumption can be lowered by five times or more than when using amorphous silicon.

On the other hand, when the thin film transistor is closed, there is a problem such as excessive leakage of current.

As a method for controlling the off current, it is common to have a lightly doped drain (LDD) region or an undoped offset region inside the source and drain regions of the thin film transistor.

Although the structure in which both the offset region and the LDD region are formed can control the off current more effectively, there is a disadvantage in that the process is increased.

An object of the present invention is to provide a method of forming the offset and LDD regions without increasing the process.

In order to solve this problem, in the method of manufacturing a polysilicon thin film transistor substrate according to an embodiment of the present invention, a step-shaped photosensitive film pattern is formed, and the gate double metal film and the gate insulating layer disposed under the dry etching are performed. Similar to the photoresist pattern, the gate insulating layer is patterned in a step shape having a different thickness, and ions are implanted using the stepped gate insulating pattern as a mask to simultaneously form source and drain regions and LDD regions in the polysilicon layer. . Thereafter, the top layer of the gate metal layers of the two layers is removed by wet etching, and the bottom layer is undercut to form an offset structure.

As such, the process is simplified because the source and drain regions and the LDD region are formed in one process, and the offset structure is formed without adding a separate process.

The gate insulating pattern remaining on the source and drain regions may be removed by dry etching after ion doping, or may be simultaneously removed in the step of forming an interlayer insulating layer and then forming a contact hole exposing the source and drain regions.

The lower film of the gate metal film is formed of molybdenum or molybdenum alloy, and the upper film is preferably formed with a thickness of 500 kPa or less with ITO to prevent the thickness of the lower film from decreasing.

The stepped photoresist pattern may be formed by adjusting the amount of light exposed to the photoresist using a mask having a lattice pattern.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

1A to 1H are cross-sectional views illustrating a method of manufacturing a polysilicon thin film transistor substrate according to a first embodiment of the present invention in a process sequence.

First, as shown in FIG. 1A, 500 to 1,000 Å thick amorphous silicon is deposited on the insulating substrate 1 by low pressure chemical vapor deposition (LPCVD), and then crystallized to form a polycrystalline silicon layer ( To form 1).

As illustrated in FIG. 1B, a gate insulating layer having a thickness of 1,000 to 3,000 Å is deposited by depositing silicon oxide (SiOx) or silicon nitride (SiNx) material by plasma enhanced chemical vapor deposition (PECVD). ), And the first metal layer 4 and the second metal layer 5 for forming gate electrodes and wirings are successively deposited thereon by sputtering. The first metal layer 4 is formed of a molybdenum (Mo) -based metal such as molybdenum (Mo), molybdenum tungsten (MoW), molybdenum titanium (MoTi), and the like, and has a thickness of 2,000 to 3,000 kPa, preferably 3,000 kPa or more. The second metal layer 5 is formed of an ITO film having a thickness of 500 kPa or less in order to minimize the reduction of the thickness of the gate electrode during dry etching or wet etching.

Next, as shown in FIG. 1C, a photosensitive material is coated on the second metal layer 5, and a photosensitive film pattern 6 for a gate electrode is formed through an exposure and development process. At this time, the photographing process is performed using a mask 71 having a plurality of grating patterns 73 near the edge A. Light is not transmitted through the center portion 72 of the mask 71, and the grating Since the light is partially transmitted through the pattern 73, the edge portion 62 has a stepped shape that is thinner than the middle portion 61 of the photosensitive film pattern 6.

Next, as shown in FIG. 1D, the photoresist film 6 has a thin edge vicinity 61, the ITO second metal layer 5, the first metal layer 4, and the gate insulating layer 3 by dry etching. Etching is performed continuously to form the second metal pattern 51 and the first metal pattern 41 serving as the gate electrode. The second metal pattern 51 and the first metal pattern 41 are formed to have the same boundary, the first metal pattern 41 is undercut with respect to the second metal pattern 51, or the gate insulating layer 3 is formed. A part of) is formed in a structure that is undercut with respect to the second metal pattern 51.

In this step, the gate insulating layer 3 is etched stepwise like the photosensitive film pattern 6 described above. That is, the thickness of the gate insulating layer 3 may include a first portion 313 under the first metal pattern 41, a second portion 312 under the edge portion 62 of the photoresist pattern 6, and a photoresist layer. It is reduced in the order of the third part 311 located outside the pattern 6. At this time, in order not to damage the polysilicon layer 2, etching is performed so that a thickness of about 500 to 1,000 kPa remains without completely removing the gate insulating layer 31 of the third portion 311.

As shown in FIG. 1E, after the photosensitive film pattern 61 is removed, ions are doped. Since the second portion 312 of the gate insulating layer 31 is relatively thicker than the third portion 311, the amount of ions transmitted to the polycrystalline silicon layer 2 under the second portion 312 is increased. Less than the polycrystalline silicon layer 2 under the third portion 311. Therefore, the LDD region 212 and the source and drain regions 213 thinly ion-doped to the polycrystalline silicon layer 2 underlying the second portion 312 and the third portion 311 through one ion doping process. 214 is formed. In this case, the polysilicon layer 2 under the first portion 313 of the gate insulating layer 31 becomes the undoped channel region 211.

Next, as shown in FIG. 1F, the gate insulating layers 311 and 312 remaining on the source and drain regions 213 and 214 and the LDD region 212 are removed by dry etching to remove the isolation gate insulating layer 313. Form.

As shown in FIG. 1G, the second metal pattern 51 is completely etched and removed with an ITO etchant based on aqua regia. In this step, the side surface of the molybdenum (Mo) -based first metal pattern 41, which is somewhat etched in the ITO etchant, is simultaneously etched to form a gate electrode 42 having a reduced line width. And the under cut structure between the gate insulating layer 313 is removed. Thus, an offset region 215 is naturally formed outside the channel region 211.

As shown in FIG. 1H, the interlayer insulating layer 8 is deposited, and the contacts C1 and C2 are formed to expose the source and drain regions 213 and 214, and then the source and the through holes C1 and C2. Source and drain electrodes 91 and 92 in contact with the drain regions C1 and C2 are formed.

As described above, in the method of manufacturing the polysilicon thin film transistor liquid crystal display according to the first embodiment of the present invention, the LDD region 212 and the source and drain regions 213 and 214 are simultaneously formed by only one ion implantation process, and the second Since the offset region 212 is naturally formed in the process of removing the metal pattern 51, the overall process is reduced. In particular, since both the LDD region 212 and the offset region 212 is included, the effect of lowering the leakage current is also excellent.

Next, a method of manufacturing a polysilicon thin film transistor substrate according to a second embodiment of the present invention will be described with reference to FIGS. 2A to 2B.

2A to 2B are cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor substrate according to a second embodiment of the present invention, in the order of a process.

In the same manner as in FIGS. 1A-1E, the second metal pattern 51, the second metal pattern 41, the stepped gate insulating layers 331, 332, and 333, the source and drain regions 213 and 214. LDD region 212 and channel region 211 are formed.

Next, as shown in FIG. 2A, the second metal pattern is directly removed without removing the gate insulating layers 331 and 332 remaining on the source and drain regions 213 and 214 and the LDD region 212. Step 41 is performed. As in the previous embodiment, as the side surface of the first metal pattern 41 is partially etched to form a gate electrode 43 having a reduced line width, between the edge of the gate electrode 43 and the edge of the LDD region 212. An undoped offset region 215 is formed in the corresponding polycrystalline silicon layer 2.

As shown in FIG. 2B, the interlayer insulating layer 8 is deposited and patterned to form contact holes C1 and C2 exposing the source and drain regions 213 and 214. In this process, the gate insulating layer 331 on the source and drain regions 213 and 214 are also simultaneously removed.

Next, source and drain electrodes 91 and 92 contacting the source and drain regions 213 and 214 through the contact holes C1 and C2 are formed on the interlayer insulating layer 8.

In the second embodiment, since the gate insulating layer 331 on the doped region is separated in the process of forming the contact holes C1 and C2 rather than a separate process, the process is reduced by one step than in the first embodiment.

As described above, in the method of manufacturing the thin film transistor substrate according to the present invention, the LDD region, the source and drain regions are formed in a single process, and the offset region is formed without adding a separate process, thereby simplifying the manufacturing process of the entire substrate. can do.

1A to 1H are cross-sectional views illustrating a method of manufacturing a polysilicon thin film transistor substrate according to a first embodiment of the present invention in a process sequence;

2A to 2B are cross-sectional views of a part of a method of manufacturing a polysilicon thin film transistor substrate according to a second exemplary embodiment of the present invention, according to a process sequence.

Claims (14)

Forming a polycrystalline silicon layer on the insulating substrate, Continuously depositing a gate insulating layer, a first metal layer, and a second metal layer on the polycrystalline silicon layer; Forming a step-shaped photosensitive film pattern on the second metal layer, wherein the thickness of the edge portion is thinner than the thickness of the center portion; The edge portion of the photoresist pattern, the second metal layer, the first metal layer, and the gate insulating layer are sequentially dry-etched to form a second metal pattern under the photoresist pattern and a first metal pattern under the second metal pattern. And a second portion corresponding to a first portion positioned below the first metal pattern and an edge portion of the photoresist pattern, and having a thickness thinner than the first portion, and positioned outside the photoresist pattern and thicker than the second portion. Forming a gate insulation pattern comprising a thin third portion, Implanting ions into the gate insulating pattern as a mask to simultaneously form source and drain regions and low concentration LDD regions in the polycrystalline silicon layers under the third and second portions, respectively, And etching an entire surface of the second metal pattern through wet etching and partially etching a side surface of the first metal pattern to form an offset region inward of the LDD region. In claim 1, Wherein the dry etching is performed such that the thickness of the third portion of the gate insulating pattern remains in the range of 500 to 1,000 GPa. In claim 2, And dry etching to remove the second and third portions of the gate insulating pattern remaining on the source and drain regions. In claim 2, Forming an interlayer insulating layer covering the first metal pattern, the gate insulating pattern, and the polysilicon layer; etching the interlayer insulating layer and the third portion over the source and drain regions to expose the source and drain regions; Method for producing a polycrystalline silicon thin film transistor substrate further comprising. In claim 1, And the first metal layer deposits molybdenum or molybdenum alloy to a thickness of 2,000 to 3,000 kPa. In claim 5, The second metal layer is a method of manufacturing a polysilicon thin film transistor substrate which is deposited by ITO to a thickness of 500 Å or less. In claim 1, The forming of the step-shaped photoresist layer pattern may further include applying a photoresist layer on the second metal layer, applying a mask having the lattice pattern to an upper portion of the photoresist layer, and exposing and developing the photoresist layer. The method of manufacturing a polysilicon thin film transistor substrate by varying the thickness of the photosensitive film pattern by controlling the amount of light exposed to the photosensitive film by using the grating pattern. Insulation board, A polysilicon layer formed on the insulating substrate and having a channel region, a source region, a drain region, and an LDD region; A gate insulating film formed on the polycrystalline silicon layer, A gate electrode formed on the gate insulating layer and positioned on the channel region; An interlayer insulating film covering the gate electrode and having first and second contact holes exposing the source region and the drain region, A source electrode and a drain electrode formed on the interlayer insulating layer and connected to the source region and the drain region through the first and second contact holes, respectively; A first portion of the gate insulating layer corresponding to the LDD region and a second portion corresponding to the channel region have different thicknesses, And the polycrystalline silicon layer further comprises an offset region formed between the channel region and the LDD region. In claim 8, The gate insulating layer may further include a third portion positioned corresponding to the source region and the drain region and having a thickness different from that of the first and second portions. In claim 9, And the first portion is thicker than the second portion, and the third portion has a thickness thinner than the second portion. Insulation board, A channel region formed on the insulating substrate, an LDD region formed on both sides of the channel region, an offset region formed between the channel region and the LDD region, and a source region formed outside the LDD region; A polycrystalline silicon layer having a drain region, A gate insulating film formed on the polycrystalline silicon layer, A gate electrode formed on the gate insulating layer and positioned on the channel region; An interlayer insulating film covering the gate electrode and having first and second contact holes exposing the source region and the drain region, A source electrode and a drain electrode formed on the interlayer insulating layer and connected to the source region and the drain region through the first and second contact holes, respectively; And a first portion corresponding to the LDD region and a second portion corresponding to the channel region of the gate insulating layer have different thicknesses. In claim 11, The boundary between the first portion and the second portion is a polysilicon thin film transistor substrate positioned above the offset region. In claim 11, The gate insulating layer may further include a third portion positioned corresponding to the source region and the drain region and having a thickness different from that of the first and second portions. In claim 13, And the first portion is thicker than the second portion, and the third portion has a thickness thinner than the second portion.