JP3641929B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming an electrode of a vertical transistor represented by a semiconductor element, particularly a UMOS using a trench structure.
[0002]
[Prior art]
In recent years, power semiconductor devices have been put into practical use, typically represented by a structure called UMOS, in which grooves are formed from the surface of a semiconductor substrate and the side surfaces thereof are used as channels for high performance. The present applicant has invented a power device using a structure similar to this but having a completely new operation mechanism and has already filed an application (Japanese Patent Laid-Open No. 6-252408).
[0003]
FIG. 18 is a cross-sectional perspective view showing a schematic structure of the power element. In FIG. 18, a source region 23 of the same conductivity type is provided on the surface of the drain region 22 formed on the substrate 21, and a U-shaped fixing is performed so as to sandwich a part of the drain region 22 and the source region 23. A potential insulating electrode 26 is disposed. This fixed potential insulating electrode 26 is formed by filling the inside of an insulating film 25 provided on the inner surface of a groove (trench) formed from the substrate surface to form a MOS type electrode 24 by filling polycrystalline silicon or the like. And a material that forms a depletion layer in the adjacent drain region 22 (that is, the potential is fixed). The depletion layer is disposed so that the source region 23 and the drain region 22 are electrically cut off. A channel region 27 is formed between the grooves, that is, between the fixed potential insulating electrodes. Further, a gate region 28 of an opposite conductivity type that is in contact with the drain region 22 and the insulating film 25 of the fixed potential insulating electrode 26 and is not in contact with the source region 23 is provided so that a potential can be arbitrarily set from the outside. is there. That is, the potential at the interface of the insulating film 25 is manipulated by the potential of the gate region 28 and the conductivity of the drain region 22 is controlled. In addition, 29 is a drain electrode. In addition, about said code | symbol, a name, etc., it changes and displays with the original text suitably.
[0004]
When forming the above element, the source region 23 needs to be formed on the surface between the trenches. Therefore, in the above prior art, an impurity for forming the source region is introduced before the step of forming the trench, and the subsequent gate oxide film formation (the above insulating film 25 is formed by thermal oxidation) and other heat treatments. The method of activation is used.
[0005]
[Problems to be solved by the invention]
The above element has a characteristic that the current amplification factor of the element is improved as the interval between the trenches is narrowed and the trench depth is decreased. Therefore, it is desirable to manufacture with a mask with reduced design rules. However, as described above, the source region forming impurity is introduced before the step of forming the trench, and the method is activated in the subsequent gate oxidation or other heat treatment, that is, the trench is formed after the impurity is diffused. In the method of forming the oxide film on the inner wall, since the source region is sandwiched between the trenches, the oxygen-enhanced diffusion effect at the time of forming the gate oxide film becomes particularly remarkable, and the diffusion length of the source region becomes very large. . That is, oxygen is diffused during the formation of the oxide film, and the depth of the impurity layer is increased. As for the oxygen-enhanced diffusion effect, for example, “Tomo Matsumoto et al.,“ Analysis of time dependence of As, P, and B diffusion in silicon in oxidizing atmosphere ”Semiconductor and Integrated Circuit Technology Symposium, Vol22th, pp72 ˜77, 1982 ”.
[0006]
FIG. 19 is a cross-sectional view of the main part for explaining the above phenomenon, wherein 1 is a single crystal silicon substrate, 2 is a trench, 3 is silicon dioxide (oxide film), and 16 is a source diffusion layer subjected to accelerated diffusion. . As shown in FIG. 19, when the source diffusion layer 16 becomes deeper, the effective depth of the trench becomes shallower from A to B. Therefore, in order to maintain the breakdown voltage of the element, it is necessary to set the trench 2 deeply. However, as described above, this impedes the improvement of the current amplification factor, so that the performance improvement is hindered.
[0007]
In order to avoid the above problem, it is necessary to first form a trench and bury polycrystalline silicon for forming a MOS type electrode, and then introduce an impurity into a portion where a source region is to be formed. As the method, as shown in FIG. 20, a method of forming a resist mask 19 and performing ion implantation (for example, phosphorus ions) can be considered. However, the finer the pattern, the more difficult it becomes to align the mask of the pattern. When mask displacement occurs as shown in FIG. 20, phosphorus ions are implanted into the polycrystalline silicon 4 doped with boron in the trench (phosphorus ion implantation). This is because the diffusion layer region 17) causes deterioration of the electrical resistance, thereby deteriorating the cut-off characteristic of the element, and the unimplanted portion 18 of ions remains at the mask misalignment portion of the source region portion, thereby forming the Schottky contact. There is a problem in that the current amplification factor is lowered and the on-resistance is increased, resulting in a decrease in yield.
[0008]
The present invention has been made to solve the problems of the prior art as described above, and an object of the present invention is to provide a stable manufacturing method of a semiconductor device corresponding to further miniaturization.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is configured as described in the claims. That is, according to the first aspect of the present invention, in the structure in which the polycrystalline silicon in which the impurity is implanted is filled in the groove provided in the single crystal silicon substrate, the oxide film is formed by the single crystalline silicon and the polycrystalline silicon in which the impurity is implanted. By oxidizing at a temperature with different formation speeds, a thin first oxide film is formed on the main surface of the single crystal silicon substrate, and a thick second oxide film is formed on the surface of the polycrystalline silicon. In this case, an impurity layer is formed in the peripheral portion of the groove on the main surface of the single crystal silicon substrate by implanting impurities from the main surface side under the condition that the thin first oxide film passes.
[0010]
As described above, a thin oxide film is formed on the main surface of the single crystal silicon substrate by oxidizing at a temperature with different oxide film formation rates (for example, a low temperature of about 700 to 900 ° C. as described in claim 8). A thick oxide film can be automatically formed on the surface of the polycrystalline silicon. Therefore, if the impurity is implanted under the condition that the thin oxide film passes and the thick oxide film does not pass, an impurity layer (for example, a source region) is selectively formed only in the thin oxide film portion, that is, the peripheral portion of the trench. I can do it. In this case, since the impurity implantation is performed after the formation of the oxide film on the inner surface of the groove, there is no problem that the impurity layer becomes deep due to the oxygen-enhanced diffusion effect as in the prior art, and the thick second Since the oxide film is formed only on the surface of the polycrystalline silicon, there is no problem of mask displacement.
[0011]
Next, the invention described in claim 2 shows a more specific manufacturing process of the invention described in claim 1, wherein the dielectric mask (first dielectric film) used for forming the groove is used. Using as it is, after forming a high-concentration diffusion layer only on the surface of the polycrystalline silicon formed in the trench, the dielectric mask is removed, and the low-temperature oxidation is performed to perform the thin first oxide film and the thick second oxide film. An oxide film is formed, and ion implantation is performed only at a necessary portion (for example, a source region) using the difference in film thickness. In addition, the structure of Claim 1 or Claim 2 is corresponded to 1st Embodiment shown in postscript FIGS. 1-11, for example.
[0012]
According to a third aspect of the present invention, in the second aspect, the depth T1 for diffusing the second impurity from the polycrystalline silicon surface, and the thickness T2 of the second oxide film formed on the polycrystalline silicon surface In the case where the first impurity is boron and phosphorus, the relationship differs depending on the combination of the case where the second impurity is boron and phosphorus.
[0013]
According to a fourth aspect of the present invention, in the second aspect, the method for diffusing the third impurity and its energy condition are defined. By setting as described in the fourth aspect, the impurity is reduced. The first oxide film can pass and the second oxide film can be prevented from passing.
[0014]
The invention described in claim 5 defines the relationship between the film thickness T3 of the first dielectric film and the film thickness T2 of the second oxide film. By setting T3 ≧ T2, After removing the oxide film, unevenness due to the protruding portion of the polycrystalline silicon can be reduced, and the flatness can be improved.
The contents of claims 3 to 5 are described in the first embodiment to be described later.
[0015]
The invention described in claim 6 is the one in which the order of low-temperature oxidation and impurity implantation in the invention described in claim 1 is reversed. After impurity implantation, a thin oxide film and a thick film are formed by low-temperature oxidation. An oxide film is formed, and the impurity layer in the polycrystalline silicon is all taken into the thick oxide film, and the impurity layer is left only under the thin oxide film. With this configuration, the manufacturing process can be further simplified.
[0016]
Further, the invention described in claim 7 shows a more specific manufacturing process of the invention described in claim 6. The invention described in claim 6 or claim 7 corresponds to, for example, a second embodiment shown in FIGS.
[0017]
The invention according to claim 8 is the temperature according to claim 1, claim 2, claim 6 or claim 7, wherein the oxide film formation rate is different between single crystal silicon and polycrystalline silicon into which impurities are implanted. Values in the range of 700 ° C to 900 ° C are used. The above values are described in FIG. 17 and the first embodiment.
[0018]
【The invention's effect】
According to the manufacturing method of the present invention, since the impurity implantation is performed after the formation of the oxide film on the inner surface of the groove, there is no problem that the impurity layer becomes deep due to the oxygen-enhanced diffusion effect as in the prior art. Since the thick second oxide film is formed only on the surface of the polycrystalline silicon, there is an effect that a problem due to mask displacement does not occur. In addition, since all of the series of processes becomes a self-alignment process that does not require a resist mask, it is freed from misalignment associated with the resist process to improve the yield, and in order to improve the performance of the element, Since it is only necessary to consider the miniaturization of the groove pattern, further miniaturization is significantly facilitated.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
1 to 11 are cross-sectional views showing respective steps in the first embodiment of the present invention, and an example in which the present invention is applied to the case of forming the structure of the conventional example (Japanese Patent Laid-Open No. 6-252408). Indicates. Each drawing is deformed for easy explanation of the process, and there is a portion that does not show an accurate dimensional ratio. The numerical values in the embodiments are examples for explaining the present embodiment, and are not limited to these, and naturally change due to fluctuations in external conditions.
[0020]
First, FIG. 1 is a cross-sectional view showing a result of forming a structure according to the manufacturing method of the present invention. A diffusion layer 7 for a source region is formed on a single crystal silicon substrate 1. In the single crystal silicon substrate 1, a silicon dioxide film (insulating film) 3 is formed on the inner surface of the trench 2, and polycrystalline silicon 4 (which becomes a MOS type electrode) is embedded in the trench. A thick silicon dioxide film 5 is formed on the upper surface of the polycrystalline silicon 4. In addition, a portion where the thin silicon dioxide film 6 is formed is a region that becomes a source electrode, and a source diffusion layer 7 is formed under the region as described above. Hereinafter, details of the process will be described focusing on the process until this structure is formed. Incidentally, regarding the manufacture of the conventional example (Japanese Patent Laid-Open No. 6-252408), the process before the shape shown in FIG. 2 is independent of the present invention, and the description thereof will be omitted.
[0021]
In FIG. 2, a PSG film (dielectric film) 8 mainly composed of silicon dioxide serving as a mask at the time of trench etching is formed on a single crystal silicon substrate 1, and a trench etching region 9 is opened. The thickness T3 of the PSG film 8 was 400 nm, and the PSG concentration was 4 mol%.
[0022]
Next, as shown in FIG. 3, trench 2 is formed by performing trench etching. In this embodiment, as the trench etching, bromine hydride (HBr), nitrogen trifluoride (NF) _Three ), Oxygen (O ₂ ) And helium (He) mixed gas, and a magnetron plasma enhanced reactive ion etching (MERIE) method in which a high frequency power of 13.56 MHz is applied in a rotating magnetic field is used to form a trench having a depth of 4 μm. 2 was formed.
[0023]
Next, as shown in FIG. 4, a silicon dioxide film 3 having a thickness of 100 nm was formed as a gate oxide film on the inner surface of the trench 2 by dry oxidation at 950.degree.
[0024]
Next, as shown in FIG. 5, when the polycrystalline silicon 10 is formed thickly by using a low pressure chemical vapor deposition method while doping boron as the first impurity, the well-known good condition at the time of formation is formed. The surface is almost flattened by the coating properties.
[0025]
Next, as shown in FIG. 6, the polycrystalline silicon 10 is made of HBr, chlorine (C1 ₂ The mixed polycrystalline silicon 4 is left only in the trench 2 by etching back by the same MERIE method as in the trench etching.
[0026]
Next, as shown in FIG. 7, the second impurity is doped on the surface of the polycrystalline silicon 4 to form a high concentration doped layer 11. The present invention utilizes a phenomenon (details will be described later) in which the oxide film thickness in the high-concentration doping layer 11 in low-temperature oxidation becomes larger than the oxide film thickness in single crystal silicon, which is one of the points of the manufacturing method. This high-concentration doping on the surface of the polycrystalline silicon 4 is performed by using, for example, boron as the second impurity at 2 × 10 2 at an energy of 33 KeV. ¹⁵ cm ~ ² After the ion implantation, activation was performed in nitrogen at 900 ° C. for 20 minutes to obtain a diffusion layer having a thickness T1 of approximately 300 nm.
[0027]
In the formation of the high-concentration doped layer 11, the second impurity to be used may be either boron or phosphorus. In the case of boron, in addition to the above method, BBr _Three A method by impurity diffusion called deposition may be used. Further, when the second impurity is phosphorus, a phosphorus ion implantation method may be used, or POC. ₁₃ A method by impurity diffusion called deposition may be used.
[0028]
Next, as shown in FIG. 8, the PSG film 8 used for both the trench etching mask and the doping mask is removed by immersing in an etchant containing hydrofluoric acid as a main component. FIG. 8 shows the shape after the PSG film 8 is removed.
[0029]
Next, as shown in FIG. 9, a thick silicon dioxide film 5 (thickness T2) obtained by oxidizing the high-concentration doping layer 11 by low-temperature oxidation and a thin oxide film 6 (thickness obtained by oxidizing the surface of the single crystal silicon substrate 1). T4) is formed.
[0030]
Here, a phenomenon in which the oxide film thickness at the time of low-temperature oxidation is different between polycrystalline silicon doped with impurities at a high concentration and single crystal silicon will be described.
FIG. 17 is a characteristic diagram showing an example of the relationship between the temperature and the oxide film thickness in the oxidation for a fixed time. In FIG. 17, the alternate long and short dash line A is a characteristic of single crystal silicon, a solid line B is a characteristic of polycrystalline silicon doped with boron (B) at a high concentration, and a broken line C is a characteristic of polycrystalline silicon doped with phosphorus (P) at a high concentration. Show properties.
[0031]
As shown in FIG. 17, the oxidation of polycrystalline silicon doped with boron or phosphorus at a higher concentration than the oxide film thickness T4 of single crystal silicon as the temperature is lowered from 900 ° C. or higher, which is generally used, to a lower temperature. It was found that the tendency of the film thickness (T2) to become thicker becomes remarkable. For example, when the film thickness is 750 ° C., data of T2 / T4 = 2.7 times is obtained for boron, and T2 / T4 = 5.6 times is obtained for phosphorus.
[0032]
At an oxidation temperature of 900 ° C. or higher, which has been generally used from the past, the difference in oxidation rate between single crystal silicon and high-concentration polycrystalline silicon becomes small. When the temperature is below 700 ° C., an abnormally long oxidation time exceeding a common level is required although it depends on the oxide film thickness to be formed. Therefore, as in this embodiment, in order to increase the difference between T2 and T4 and prevent the oxidation time from becoming abnormally long, the temperature range is preferably set to 700 ° C. or higher and lower than 900 ° C. Therefore, in this embodiment, since oxidation is performed by boron, oxidation is performed by wet oxidation at 750 ° C. for 923 minutes to form a silicon dioxide film 5 having a thickness of 100 nm on the polycrystalline silicon 4. A silicon dioxide film 6 having a thickness of 37 nm was formed on the surface.
[0033]
The high-concentration doping layer 11 is made of BBr using boron as the second impurity. _Three When formed by deposition, the control of the diffusion depth (T1) becomes loose. In the case where the polycrystalline silicon 4 is doped with boron as the first impurity in advance and has a structure in which electrical connection (contact) is made with the metal wiring on the surface as in this embodiment, a substantial problem occurs. Absent. And the process is simplified, and it is not necessary to increase the required oxide film thickness.
[0034]
Further, since it is known that the oxide film thickness is generally 5/2 of the original silicon film consumed for formation, the thickness T1 of the high-concentration doping layer 11 and the oxide film thickness T2 after low-temperature oxidation. Is set so that T1 × 5/2> T2. Thus, a residual region that is not oxidized can be left at the bottom of the high-concentration doping layer 11. Since this remaining region serves as a high-concentration diffusion layer for the contact when a contact is formed later, the process can be further simplified.
[0035]
On the other hand, when phosphorus, which is an impurity having an oxidation rate larger than that of boron, is doped as the second impurity when forming the high-concentration doping layer 11, the oxide film thickness T2 on the polycrystalline silicon 4 in the low-temperature oxidation is The difference from the oxide film thickness T4 on the single crystal silicon becomes larger. Therefore, by setting the relationship between the thickness T1 of the high-concentration doping layer 11 and the oxide film thickness T2 after low-temperature oxidation so that T1 × 5/2 ≦ T2, the oxidation rate can be obtained even when thicker oxidation is performed. Therefore, there is an advantage that the oxidation time can be shortened. Further, by performing such thick oxidation, it is possible to prevent the electrical characteristics from being changed after the oxidation.
As described above, any of these steps can be selected.
[0036]
On the contrary, when the buried polycrystalline silicon 4 is doped with phosphorus as the first impurity, the second impurity of the high-concentration doped layer 11 is phosphorus from the viewpoint of eliminating the influence on the electrical characteristics. It can be seen that T1 × 5/2> T2, and that the second impurity is boron, T1 × 5/2 ≦ T2.
[0037]
Next, as shown in FIG. 10, ion implantation for forming a source region is performed using the difference between the two types of film thicknesses T2 and T4. In this case, it is necessary that most of the implanted ions do not reach the polycrystalline silicon 4 but remain in the thick oxide film 5 and that the implanted ions reach the single crystal silicon 1 under the thin oxide film 6. There is. Therefore, the relationship between the average projected range Rp of the implanted impurities under the ion implantation conditions and the standard deviation ΔRp is set so that 99% of the implanted ions are within the thickness T2.
Rp + (3 × ΔRp) <T2
and
Rp> T4
When the implantation energy is set so as to satisfy the relationship (for example, when the implantation energy is 34 keV, Rp = 0.0419 and ΔRp = 0.0184), as shown in FIG. Is introduced, and the impurity layer 14 is formed.
[0038]
Thereafter, in this embodiment, after activation annealing is performed in a nitrogen atmosphere at 950 ° C. for 20 minutes, the oxide film 5 and the oxide film 6 in the contact portion are removed, and the wiring layer (aluminum film) 15 is formed. A structure as shown in FIG. 11 is formed. The structure shown in FIG. 11 is a basic structure portion of the conventional example (Japanese Patent Laid-Open No. 6-252408), and 7 is a source diffusion layer (corresponding to the impurity layer 14). As shown in FIG. 18, since the MOS type electrode 24 and the source region 23 are commonly connected to the source electrode in the structure of the conventional example, the wiring layer 15 is formed on the entire surface in FIG. However, when connecting to separate electrodes, etching may be performed to form each electrode.
[0039]
In order to form a contact such as the wiring layer 15, it is desirable that the surface has little unevenness. For this purpose, the thickness T3 of the PSG film 8 that serves as a mask for forming the trench 2 and determines the protruding height from the surface of the polycrystalline silicon 4 is compared with the oxide film thickness T2 of the high-concentration doping layer 11. It is preferable to set T3 ≧ T2. The unevenness on the surface is greatly improved only by setting in this way.
[0040]
(Second Embodiment)
Next, FIG. 12 to FIG. 14 are cross-sectional views showing steps in the second embodiment of the present invention. This embodiment is a process in which the first embodiment is further simplified. The steps up to the formation of the polycrystalline silicon 4 shown in FIGS. 1 to 6 are the same as those in the first embodiment, and the description thereof is omitted.
[0041]
First, after the step of FIG. 6, the PSG film 8 is removed as shown in FIG.
Next, as shown in FIG. 13, first, ion implantation of a second impurity is performed. In this case, ion implantation is performed with high energy so that the ion implantation layer 14 is formed at a deep position as illustrated. However, in consideration of a low-temperature oxidation step (which takes a long time compared with high-temperature oxidation) to be performed later, it is desirable that the oxide film thickness is small. For this purpose, it is preferable that the implantation energy is as small as possible. ^Five cm ~ ² Only the ion implantation is performed to form the ion implantation layer 14. At this time, ions are implanted into both the surface portion of the single crystal silicon 1 and the surface of the polycrystalline silicon 4.
[0042]
Next, as shown in FIG. 14, low-temperature oxidation is performed in the same manner as in the first embodiment. The thickness of the oxide film formed at this time must be such that all the second impurities ion-implanted into the surface of the polycrystalline silicon 4 are taken into the oxide film.
Since the relationship between the thickness T1 of the ion-implanted layer and the oxide film thickness T2 after low-temperature oxidation is T1 × 5/2 ≦ T2, the above-described relationship is as described above in the present embodiment so as to satisfy this relationship. Then, phosphorus was ion-implanted at 40 keV. As a result, the depth T1 of the ion implantation layer 14 was T1 = Rp + (3 × ΔRp) ≈112 nm.
[0043]
In addition, since oxidation was performed using phosphorus, oxidation was performed for 193 minutes by a wet oxidation method at 750 ° C. to form a 150 nm thick polycrystalline silicon oxide film 5. At this time, the thickness of the oxide film 6 on the single crystal silicon side is about 26 nm, and is in the range of Rp−ΔRp = 18.8 nm, which is a high concentration range on the surface side with respect to Rp = 48.6 nm at the time of ion implantation. Only enters a little. Therefore, most of the phosphorus ion implantation layer 14 on the single crystal silicon side remains unoxidized and can be used for forming the source electrode diffusion layer. Note that since the diffusion constant of impurities such as boron and phosphorus is about four orders of magnitude smaller than that of oxygen atoms, it is not necessary to consider the disruption of the above relationship due to diffusion. Thereafter, activation annealing is performed in a nitrogen atmosphere at 950 ° C. for 20 minutes to form a structure similar to that shown in FIG. Subsequent steps are the same as those in FIG.
[0044]
In the present embodiment, there are restrictions on the impurities used, but the process can be further simplified while having the same effect as in the first embodiment.
[0045]
(Third embodiment)
Next, FIG. 15 and FIG. 16 are cross-sectional views showing manufacturing steps in the third embodiment of the present invention.
As described above, in the first and second embodiments, the case where the present invention is applied in the manufacture of the element described in JP-A-6-252408 has been described. It is not limited. In the third embodiment, a case where the present invention is applied to a UMOS device (for example, an element described in JP-A-4-145628) will be described as another device.
[0046]
First, as shown in FIG. 15, a conductive type diffusion layer 13 (portion portion) opposite to the single crystal silicon substrate 1 is formed in contact with the oxide film 3 on the side wall of the trench. Crystalline silicon 4 is filled. In FIG. 15, as in the first and second embodiments, the step of doping the impurity at a high concentration on the surface of the polycrystalline silicon 4 and oxidizing at a relatively low temperature is used. In the same manner as described above, a structure in which oxide films 5 and 6 having two kinds of film thickness are formed on the surface can be formed.
[0047]
Thereafter, ion implantation is performed in the same manner as in the above embodiment to form the source diffusion layer 7, and after further annealing, the contact is etched, and subsequently the wiring layer 15 (aluminum film) is formed, as shown in FIG. Thus, a narrow vertical UMOS structure between trenches can be easily formed. In this structure, it is necessary to separately form the contact of the polycrystalline silicon 4 and the contact of the diffusion layer 13 in the trench, but since the number of effective channels can be dramatically increased, the on-resistance can be greatly reduced. The effect is obtained.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a basic part of a structure formed in first and second embodiments of the present invention.
FIG. 2 is a cross-sectional view showing a state in which a mask for forming a trench is formed in the first and second embodiments of the present invention.
FIG. 3 is a cross-sectional view showing a state in which a trench is formed on single crystal silicon in the first and second embodiments of the present invention.
FIG. 4 is a cross-sectional view showing a state in which a silicon oxide film is formed on the inner surface of a trench in the first and second embodiments of the present invention.
FIG. 5 is a cross-sectional view showing a state in which polycrystalline silicon filling a trench is formed in the first and second embodiments of the present invention.
FIG. 6 is a cross-sectional view showing a state in which polycrystalline silicon is left only in a trench in the first and second embodiments of the present invention.
FIG. 7 is a cross-sectional view showing a state in which a high-concentration impurity doped layer is formed on the surface of buried polycrystalline silicon in the first embodiment of the present invention.
FIG. 8 is a cross-sectional view showing a state in which the dielectric film on the surface is removed in the first embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a state in which two kinds of oxide films having different film thicknesses are formed by oxidizing the surface at a low temperature in the first embodiment of the present invention.
FIG. 10 is a cross-sectional view showing a state in which ion implantation is performed on the surface in the first embodiment of the present invention.
FIG. 11 is a cross-sectional view showing a state in which the element structure according to the first embodiment of the present invention is formed.
FIG. 12 is a cross-sectional view showing a state in which the dielectric film is removed after the buried polycrystalline silicon is formed in the second embodiment of the present invention.
FIG. 13 is a cross-sectional view showing a state in which ion implantation is performed on the surface in the second embodiment of the present invention.
FIG. 14 is a cross-sectional view showing a state where the surface is oxidized at a low temperature and the implanted ion layer in the polycrystalline silicon is taken into the oxide film in the second embodiment of the present invention.
FIG. 15 is a cross-sectional view showing a state in which a diffusion layer is formed inside a single crystal silicon substrate and two types of oxide films having different thicknesses by low-temperature oxidation are formed on the surface in the third embodiment of the present invention.
FIG. 16 is a cross-sectional view showing a state in which a source diffusion layer is formed on the surface of single crystal silicon and a wiring layer is formed in the third embodiment of the present invention.
FIG. 17 is a characteristic diagram showing oxidation data characteristics of single crystal silicon and polycrystalline silicon for setting conditions for low-temperature oxidation in the present invention.
FIG. 18 is a cross-sectional perspective view of an example of a conventional apparatus to which the present invention is applied.
FIG. 19 is a cross-sectional view showing a state where the source diffusion layer, which is one of the problems of the conventional manufacturing method, is oxygen-accelerated.
FIG. 20 is a cross-sectional view for explaining problems at the time of ion implantation for forming a source region in a conventional manufacturing method.
[Explanation of symbols]
1 ... single crystal silicon substrate 2 ... groove
3 ... Silicon dioxide 4 ... Polycrystalline silicon
5 ... Thick silicon dioxide film 6 ... Thin silicon dioxide film
7 ... Source diffusion layer 8 ... Trench etching mask oxide film
9 ... Trench etching region 10 ... Polycrystalline silicon
11 ... High concentration doping layer 13 ... Diffusion region
14 ... Ion implantation layer 15 ... Wiring layer
16 ... Source diffusion layer subjected to oxygen-accelerated diffusion 17 ... Phosphorus ion implantation diffusion layer region
18 ... Uninjected portion of source electrode portion 19 ... Resist mask
21 ... Substrate 22 ... Drain region
23 ... Source region 24 ... MOS type electrode
25 ... Insulating film 26 ... Fixed potential insulating electrode
27 ... Channel region 28 ... Gate region
29 ... Drain electrode

Claims (8)

After forming a groove on one main surface of the single crystal silicon substrate and forming a dielectric film on the inner surface of the groove, a single crystal silicon and an impurity are implanted into the groove filled with polycrystalline silicon into which impurities are implanted. The first oxide film is formed on the main surface of the single crystal silicon substrate and the first oxide film is formed on the surface of the polycrystalline silicon by oxidizing at a temperature different from that of the polycrystalline silicon. A second oxide film thicker than the film is formed, the thick second oxide film does not pass through, and the thin first oxide film passes through the main surface side under the condition that the thin first oxide film passes through. A method of manufacturing a semiconductor device, comprising forming an impurity layer in a peripheral portion of the groove on a main surface of a single crystal silicon substrate. Forming a first dielectric film on one main surface of the single crystal silicon substrate;
Forming an opening exposing the single crystal silicon substrate in at least a portion of the first dielectric film;
Etching the single crystal silicon substrate from the opening to form a groove;
Forming a second dielectric film on at least the groove inner surface;
A step of filling the trench with polycrystalline silicon and implanting a first impurity;
Diffusing a second impurity from the surface of the polycrystalline silicon exposed in the opening of the first dielectric film;
A step of removing the first dielectric film;
Thereafter, the single crystal silicon and the polycrystalline silicon into which the impurities are implanted are oxidized at a temperature at which the oxide film formation rate is different, whereby the first oxide film is formed on the main surface of the single crystal silicon substrate. Forming a second oxide film thicker than the first oxide film on the surface of
A step of diffusing a third impurity from the main surface side under a condition that the thick second oxide film does not pass and the thin first oxide film passes;
A step of removing the first and second oxide films;
A method for manufacturing a semiconductor device, comprising: Regarding the relationship between the depth T1 for diffusing the second impurity from the polycrystalline silicon surface and the thickness T2 of the second oxide film formed on the polycrystalline silicon surface,
In the case where boron is implanted as the first impurity in the polycrystalline silicon, T1 × 5/2> T2 when the second impurity is boron, and T1 × when the second impurity is phosphorus. 5/2 ≦ T2,
In the case where phosphorus is implanted as the first impurity in the polycrystalline silicon, T1 × 5/2> T2 when the second impurity is phosphorus, and T1 when the second impurity is boron. 3. The method of manufacturing a semiconductor device according to claim 2, wherein x5 / 2≤T2. The method of diffusing the third impurity is an ion implantation method. The average projected range Rp and standard deviation ΔRp of the implanted impurity in the oxide film determined from the energy, and the film thickness of the second oxide film. The implantation energy is set so that the relationship with T2 is Rp + (3 × ΔRp) <T2, and the relationship with the film thickness T4 of the first oxide film is Rp> T4. Item 3. A method for manufacturing a semiconductor device according to Item 2. 3. The method of manufacturing a semiconductor device according to claim 2, wherein a relationship between a thickness T3 of the first dielectric film and a thickness T2 of the second oxide film satisfies T3 ≧ T2. After forming a groove on one main surface of a single crystal silicon substrate and forming a dielectric film on the inner surface of the groove, impurities are implanted into the groove filled with polycrystalline silicon into which impurities are implanted. When the impurity layer is formed on the main surface of the single crystal silicon substrate and the surface of the filled polycrystalline silicon, the oxide film formation rate is different between the single crystal silicon and the polycrystalline silicon into which the impurities are implanted. By oxidizing at a temperature, a first oxide film is formed on the main surface of the single crystal silicon substrate, and a second oxide film thicker than the first oxide film is formed on the surface of the polycrystalline silicon. And, the second thick oxide film captures all of the impurity layer formed on the surface of the polycrystalline silicon, and the thin first oxide film is set so as to leave the impurity layer formed on the main surface, Above Method of manufacturing a semiconductor device and forming an impurity layer in the peripheral portion of the groove in the major surface of the crystal substrate. Forming a first dielectric film on one main surface of the single crystal silicon substrate;
Forming an opening exposing the single crystal silicon substrate in at least a portion of the first dielectric film;
Etching the single crystal silicon substrate from the opening to form a groove;
Forming a second dielectric film on at least the groove inner surface;
A step of filling the trench with polycrystalline silicon and implanting a first impurity;
A step of removing the first dielectric film;
A step of diffusing a second impurity from the main surface side of the single crystal silicon substrate;
Thereafter, all of the second impurity layer formed on the surface of the polycrystalline silicon at a temperature at which the oxide film formation speed differs between the single crystal silicon and the polycrystalline silicon into which the impurity is implanted, is taken into the oxide film, and the main surface The first impurity film is formed on the main surface of the single crystal silicon substrate and the first oxide film is formed on the surface of the polycrystalline silicon. Forming a thick second oxide film;
A step of removing the first and second oxide films;
The method of manufacturing a semiconductor device according to claim 6, comprising: The temperature at which the oxide film forming speed differs between the single crystal silicon and the polycrystalline silicon into which impurities are implanted is a value in the range of 700 ° C to 900 ° C. A method for manufacturing a semiconductor device according to claim 6.

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