JP5675931B2 - Method for manufacturing trench type semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a trench type semiconductor device having an interlayer insulating film.

  Conventionally, trench type semiconductor elements such as vertical MOSFET (Metal Oxide Field Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor) in which a trench is formed in a substrate and a gate electrode is formed in the trench, and a manufacturing method thereof are known. ing. In such a trench type semiconductor element, an interlayer insulating film is formed so as to close the opening of the trench. The interlayer insulating film insulates the electrode inside the trench from the external electrode.

  Patent Document 1 discloses a trench type including an N-type silicon substrate in which a trench is formed, a gate poly formed in the trench, and a local oxide film (interlayer insulating film) formed on the upper surface of the N-type substrate. A MOS transistor is disclosed. The N-type silicon substrate includes a high-concentration P-type bulk layer formed on both ends of the trench, a low-concentration P-type bulk layer formed between the P-type bulk layer and the trench, and a P-type bulk. An N-type source layer formed on the upper layer portion of the layer is formed. A part of the local oxide film is also formed between the inner wall surface of the trench and the gate poly.

  In the method of manufacturing a MOS transistor described in Patent Document 1, after forming a P-type bulk layer on an N-type silicon substrate, a silicon nitride film and a low-temperature oxide film for forming a patterned trench are formed. Next, after forming the trench, the low-temperature oxide film is removed. Next, a gate poly is formed in the trench.

  Next, a local oxide film is formed on the gate poly by heat treatment based on the local oxidation of silicon (LOCOS). Thereafter, after the silicon nitride film is removed, P-type impurities and N-type impurities are sequentially ion-implanted to form low-concentration P-type bulk layers and N-type bulk layers. Here, since a thin thermal oxide film remains on the upper surface of the region where the low-concentration P-type bulk layer and N-type bulk layer are to be formed, the implanted ions pass through this thin thermal oxide film. Implanted with acceleration voltage. For this reason, many of the implanted ions pass through the thick local oxide film on the gate poly and do not remain inside the local oxide film. Thereby, the MOS transistor described in Patent Document 1 is completed.

JP-A-9-321303

  However, in the MOS transistor described in Patent Document 1, the upper surface of the gate poly is segregated by heat treatment to form a local oxide film. For this reason, there is a problem that it is not easy to make the gate poly thick enough to be insulated by the local oxide film. In order to make the local oxide film in such a thickness that can be insulated, a method such as a heat treatment for a long time or a long time can be considered. However, in these methods, another problem of deteriorating the element characteristics of the manufactured MOS transistor is considered. Will occur.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a method of manufacturing a trench type semiconductor device capable of easily increasing the thickness of an interlayer insulating film.

In order to achieve the above object, according to the present invention , an oxide film is formed on a substrate, a nitride film is formed on the oxide film, a resist film is formed on the nitride film, and the oxidation film is formed. by etching a portion of film and the nitride film, and a mask layer forming step of partially forming a mask layer of apertured insulating on the substrate, the substrate of the exposed area from the mask layer A trench forming step of forming a trench having an open top, a burying step of burying a semiconductor layer in the trench, a second ion implantation step of implanting ions into the substrate to form a conductive semiconductor region, after the second ion implantation step, a first ion implantation step of implanting the semiconductor layer buried different ions into the trench and the semiconductor material constituting the semiconductor layer, wherein in the first ion implantation step An interlayer insulating film forming step of forming an interlayer insulating film using the semiconductor layer of the on is implanted region is thermally oxidized, after the ion implantation step, and a removing step of removing the mask layer, the first The trench-type semiconductor device manufacturing method is characterized in that an acceleration voltage in the ion implantation step is smaller than an acceleration voltage in the second ion implantation step .

The invention according to claim 2 is characterized in that the concentration of impurities in the interlayer insulating film by the first ion implantation step is higher than the concentration of impurities in the conductive semiconductor region by the second ion implantation step. A method for manufacturing a trench type semiconductor device according to claim 2.

According to a third aspect of the present invention , in the trench according to the second or third aspect, a dose amount in the first ion implantation step is larger than a dose amount in the second ion implantation step. This is a method for manufacturing a type semiconductor device.

The invention according to claim 4 is characterized in that a reactive ion etching method is applied in the trench forming step. The trench type semiconductor element according to any one of claims 1 to 3 It is a manufacturing method.

  According to the method for manufacturing a trench type semiconductor element of the present invention, a semiconductor region in which an interlayer insulating film includes a semiconductor material and an impurity composed of an element different from the semiconductor material, and the impurity concentration of the interlayer insulating film is formed on the substrate. It is larger than the impurity concentration. Thereby, the volume of the interlayer insulating film can be easily increased and formed thick.

1 is a cross-sectional view of a trench type semiconductor device according to a first embodiment. It is a figure explaining the manufacturing method of the trench type semiconductor device by a 1st embodiment. It is a figure explaining the manufacturing method of the trench type semiconductor device by a 1st embodiment. It is a figure explaining the manufacturing method of the trench type semiconductor device by a 1st embodiment. It is a figure explaining the manufacturing method of the trench type semiconductor device by a 1st embodiment. It is a figure explaining the manufacturing method of the trench type semiconductor device by a 1st embodiment. It is a figure explaining the manufacturing method of the trench type semiconductor device by a 1st embodiment. It is a figure explaining the manufacturing method of the trench type semiconductor device by a 1st embodiment. It is a figure explaining the manufacturing method of the trench type semiconductor device by a 1st embodiment. It is a figure explaining the manufacturing method of the trench type semiconductor device by a 1st embodiment. It is a figure explaining the manufacturing method of the trench type semiconductor device by a 1st embodiment. It is a figure explaining the manufacturing method of the trench type semiconductor device by a 1st embodiment.

(First embodiment)
Hereinafter, a first embodiment in which the present invention is applied to a MOSFET will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a trench type semiconductor device according to the first embodiment. In addition, let the up-down direction shown by the arrow of FIG. 1 be an up-down direction.

  As shown in FIG. 1, the trench type semiconductor device 1 according to the first embodiment includes a substrate 2, a gate insulating film 3, a gate electrode 4, an interlayer insulating film 5, a barrier metal layer 6, and a source electrode 7. The drain electrode 8 is provided.

The substrate 2 is mainly composed of N ^- type silicon.

An N ⁻ type drain region 11 is formed on the substrate 2 on the drain electrode 8 side.

A P ⁻ type channel region 12 is formed in the middle layer portion of the substrate 2. The P ⁻ -type channel region 12 has a thickness of about 0.3 μm. The P ⁻ channel region 12 is doped with B (boron) as a P-type impurity. The P ⁻ -type channel region 12 has an impurity concentration of about 2.0 × 10 ¹⁶ atoms / cm ³ .

In the upper layer portion of the substrate 2, an N ⁺ type source region 13 is formed. The N ⁺ type source region 13 has a thickness of about 0.2 μm. The N ⁺ type source region 13 is doped with As (arsenic) as an N type impurity. The N ⁺ type source region 13 has an impurity concentration of about 1.0 × 10 ¹⁹ atoms / cm ³ .

  The regions 12 and 13 correspond to the conductive semiconductor regions described in the claims.

A trench 14 is formed in the substrate 2 to divide the N ⁺ source region 13 at a predetermined interval. The trench 14 penetrates the P ⁻ channel region 12 and the N ⁺ source region 13. That is, the trench 14 reaches the N ⁻ drain region 11 from the upper surface of the substrate 2. The trench 14 has a depth of about 1 μm. The trench 14 has a width of about 0.5 μm. The distance between adjacent trenches 14 is about 0.2 μm.

The gate insulating film 3 is for insulating the substrate 2 and the gate electrode 4. The gate insulating film 3 is formed so as to cover the inner peripheral surface of the trench 14. The gate insulating film 3 is made of SiO _2. The gate insulating film 3 has a thickness of about 55 nm.

The gate electrode 4 is for forming a channel in the P ⁻ channel region 12. The gate electrode 4 is embedded in the trench 14. The gate electrode 4 is made of polysilicon containing impurities.

The interlayer insulating film 5 is for insulating the gate electrode 4 and the source electrode 7. Interlayer insulating film 5 is made of an insulating material composed mainly of SiO _2. The interlayer insulating film 5 contains ion-implanted As (arsenic) as an impurity. Here, As (arsenic) contained in the interlayer insulating film 5 is for increasing the volume of the interlayer insulating film 5. The impurity concentration of As (arsenic) in the interlayer insulating film 5 is about 1.0 × 10 ¹⁹ atoms / cm ³ to about 1.0 × 10 ²¹ atoms / cm ³ . That is, the impurity concentration of As (arsenic) in the interlayer insulating film 5 is higher than the impurity concentration of the regions 11, 12, and 13. Interlayer insulating film 5 has a thickness of about 150 nm. The width of the interlayer insulating film 5 is about 10 nm to about 20 nm larger than the width of the trench 14. However, considering that the width of the trench 14 is about 0.5 μm, the width of the interlayer insulating film 5 and the width of the trench 14 are in a range that is considered to be substantially the same.

The barrier metal layer 6 is for suppressing the diffusion of the metal element constituting the source electrode 7 into the substrate 2 or the like. The barrier metal layer 6 is made of titanium silicide. The barrier metal layer 6 is formed so as to cover the entire upper surfaces of the N ⁺ -type source region 13 and the interlayer insulating film 5.

  The source electrode 7 is made of Al (aluminum) or Al / Cu (copper). The source electrode 7 is formed so as to cover the entire upper surface of the barrier metal layer 6.

  The drain electrode 8 is made of W (tungsten). The drain electrode 8 is formed on the entire lower surface of the substrate 2.

  The operation of the above-described trench type semiconductor element 1 will be described.

First, a predetermined voltage is applied to the gate electrode 4. As a result, a channel is formed in the P ⁻ type channel region 12 in the vicinity of the interface between the gate insulating film 3 and the P ⁻ type channel region 12. When a voltage is applied between the source electrode 7 and the drain electrode 8 in this state, electrons move through the N ⁺ -type source region 13, the channel of the P ⁻ -type channel region 12, and the N ⁻ -type drain region 11. As a result, a current flows between the source electrode 7 and the drain electrode 8.

  Next, a manufacturing method of the above-described trench type semiconductor element 1 will be described with reference to the drawings. 2 to 12 are views for explaining a method of manufacturing a trench type semiconductor device according to the first embodiment.

First, an SiO ₂ film 31 having a thickness of about 10 nm is formed on the substrate 2. The thickness of the SiO ₂ film 31 can be appropriately changed between about 5 nm and ₂₀ nm. Thereafter, a SiN film 32 having a thickness of 75 nm is formed on the SiO ₂ film 31. Note that the thickness of the SiN film 32 can be appropriately changed between 50 nm and 200 nm. Next, a resist film (not shown) is formed on the SiN film 32 by photolithography. Thereafter, as shown in FIG. 2, an insulating mask layer 33 having an opening 33a formed in a part thereof is formed on the substrate 2 by etching part of the SiN film 32 and the SiO ₂ film 31 (see FIG. 2). Mask layer forming step).

  Next, as shown in FIG. 3, the substrate 2 in the region exposed from the mask layer 33 is removed by RIE (reactive ion etching). As a result, a trench 14 having an upper end opened is formed in the region of the substrate 2 exposed from the mask layer 33 (trench formation step).

Next, the substrate 2 is heated. Thereby, as shown in FIG. 4, the inner wall portion of the trench 14 is thermally oxidized to form the gate insulating film 3 made of SiO ₂ .

  Next, as shown in FIG. 5, a polysilicon layer 35 is formed in the trench 14 and on the upper surface of the mask layer 33 by LPCVD (Low Pressure Chemical Vapor Deposition) (embedding step). The polysilicon layer 35 corresponds to the semiconductor layer recited in the claims.

  Next, as shown in FIG. 6, the upper surface of the polysilicon layer 35 is removed by etching so as to remain only in the trench 14. Here, the mask layer 33 functions as an etching stopper. For this reason, the substrate 2 below the mask layer 33 is not etched.

Next, B (boron) having a dose amount of about 1.0 × 10 ¹² atoms / cm ² to about 1.0 × 10 ¹⁴ atoms / cm ² accelerated by a voltage of about 40 keV to about 180 keV is applied to the upper surface of the substrate 2. Ion implantation. Thereafter, B (boron) is diffused by heating the substrate 2 to form a P ⁻ -type channel region 12 as shown in FIG.

Next, As (arsenic) having a dose of about 1.0 × 10 ¹⁴ atoms / cm ² to about 1.0 × 10 ¹⁶ atoms / cm ² accelerated by a voltage of about 40 keV to about 180 keV is applied to the upper surface of the substrate 2. Ion implantation. Thereafter, as shown in FIG. 7, the substrate 2 is heated to diffuse As (arsenic) to form an N ⁺ -type source region 13 (second ion implantation step).

  Here, B (boron) and As (arsenic) are implanted at an accelerating voltage that can pass through the mask layer 33.

Next, as shown in FIG. 8, As (arsenic) ions different from Si (silicon) constituting the polysilicon layer 35 are implanted into the upper surface of the polysilicon layer 35 embedded in the trench 14. Here, As (arsenic) is implanted at a dose of 5 × 10 ¹⁵ atoms / cm ^{2 to} 5 × 10 ¹⁶ atoms / cm ² and an acceleration voltage of 5 keV to 40 keV. As a result, the upper end portion of the polysilicon layer 35 is made amorphous. As a result, an ion implantation layer 36 is formed on the polysilicon layer 35. Since the acceleration voltage of As (arsenic) in this process is small, As (arsenic) is blocked by the mask layer 33. For this reason, As (arsenic) is hardly implanted into the N ⁺ type source region 13 of the substrate 2. Further, the polysilicon layer 35 in a region where As (arsenic) ions are not implanted becomes the gate electrode 4 (first ion implantation step).

  Here, the As (arsenic) impurity concentration of the ion implantation layer 36 ion-implanted in the first ion implantation step is higher than the impurity concentration of the regions 12 and 13 ion-implanted in the second ion implantation step.

  Next, the substrate 2 is heated at about 900 ° C. for 30 minutes. As a result, as shown in FIG. 9, the ion-implanted layer 36 into which As (arsenic) ions are implanted is thermally oxidized, and the volume is amplified. As a result, an interlayer insulating film 5 having a thickness of about 300 nm is formed on the gate electrode 4 so as to close the opening of the trench 14 (interlayer insulating film forming step).

  Here, when the interlayer insulating film is formed by the LOCOS method, it is necessary to heat the substrate at about 1100 ° C. for about 60 minutes. It can be seen that in the manufacturing method according to the first embodiment described above, the interlayer insulating film 5 is formed at a lower temperature and in a shorter time than the LOCOS method.

  Next, as shown in FIG. 10, the SiN film 32 of the mask layer 33 is removed by etching.

Next, as shown in FIG. 11, the SiO ₂ film 31 of the mask layer 33 is removed by etching. Here, part of the interlayer insulating film 5 mainly composed of SiO ₂ is also removed by this etching process. However, the thickness of the interlayer insulating film 5 is very large compared to the thickness of the SiO ₂ film 31 of the mask layer 33. For this reason, when viewed from the whole interlayer insulating film 5, the interlayer insulating film 5 to be removed is extremely small and does not cause a problem.

  Next, as shown in FIG. 12, the barrier metal layer 6 is formed so as to cover the entire upper surface. Thereafter, the source electrode 7 is formed so as to cover the entire barrier metal layer 6.

  Finally, the drain electrode 8 is formed on the lower surface of the substrate 2. Thereby, the trench type semiconductor element 1 shown in FIG. 1 is completed.

  As described above, in the trench type semiconductor element 1 according to the first embodiment, As (arsenic) different from Si (silicon) which is a semiconductor material constituting the interlayer insulating film 5 is ion-implanted into the interlayer insulating film 5. . Further, in the trench type semiconductor element 1, the concentration of impurities in the interlayer insulating film 5 is made larger than the concentration of impurities in the regions 12 and 13. For this reason, in the step of forming the interlayer insulating film 5 by heating the ion implantation layer 36, a large amount of As (arsenic) is taken in between the Si (silicon) atoms of the ion implantation layer 36. The amplification factor can be increased. Thereby, the insulation by the interlayer insulating film 5 can be improved, and a short circuit between the source electrode 7 and the gate electrode 4 can be suppressed. Further, compared to the LOCOS method, the interlayer insulating film 5 can be formed by oxidation and volume amplification by heating at a low temperature for a short time. Thereby, in each area | region 11, 12, 13, it can suppress that an impurity is spread | diffused by the heating for forming the interlayer insulation film 5. FIG. As a result, deterioration of element characteristics of the trench type semiconductor element 1 can be suppressed.

  In the method for manufacturing the trench type semiconductor element 1 according to the first embodiment, the mask layer 33 functions as a mask in the process of forming the trench 14 and also functions as a mask in the process of forming the interlayer insulating film 5. That is, the trench 14 and the interlayer insulating film 5 can be formed by self-alignment. As a result, the relative position between the trench 14 and the interlayer insulating film 5 can be prevented from shifting, and thus the interlayer insulating film 5 can be formed at an accurate position of the upper end portion of the trench 14.

Further, in the manufacturing method of the trench type semiconductor element 1, since the positional deviation between the trench 14 and the interlayer insulating film 5 can be suppressed, the region where the interlayer insulating film 5 and the N ⁺ type source region 13 overlap is very small. can do. Thereby, the space | interval between the adjacent trenches 14 can be made small, and integration can be improved. As a result, a reduction in channel resistance can be realized. That is, in the trench type semiconductor element 1, the on-resistance can be greatly reduced.

In the method for manufacturing the trench type semiconductor element 1, the N ⁺ type source region 13 can be exposed by removing the mask layer 33. As a result, a contact region with the source electrode 7 can be easily formed on the upper surface of the N ⁺ type source region 13 without requiring a contact mask process.

  As mentioned above, although this invention was demonstrated in detail using embodiment, this invention is not limited to embodiment described in this specification. The scope of the present invention is determined by the description of the claims and the scope equivalent to the description of the claims. Hereinafter, modified embodiments in which the above-described embodiment is partially modified will be described.

  For example, although the embodiment in which the present invention is applied to the MOSFET has been described, the present invention may be applied to other trench type semiconductor elements such as IGBTs.

  In addition, the material, shape, numerical value, and the like of each component in the above-described embodiment can be appropriately changed.

For example, elements (ions) implanted into the interlayer insulating film are B (boron), N (nitrogen), O (oxygen), Ne (neon), P (phosphorus), Ar (argon), Kr (krypton), Sb (antimony) or the like can be applied. Further, the impurity concentration of the element implanted into the interlayer insulating film can be appropriately changed as long as it is higher than the impurity concentration of the P ⁻ type channel region and N ⁺ type source region formed in the substrate. For example, the impurity concentration of the element implanted into the interlayer insulating film may be set between about 1.0 × 10 ¹⁴ atoms / cm ³ and about 1.0 × 10 ²¹ atoms / cm ³ .

Further, the acceleration voltage at the time of implanting impurities into the P ⁻ type channel region and the N ⁺ type source region can be changed as appropriate as long as it can pass through the mask layer. For example, the accelerating voltage for implanting impurities into the P ⁻ type channel region and the N ⁺ type source region may be set between about 20 keV and about 180 keV.

DESCRIPTION OF SYMBOLS 1 Trench type semiconductor element 2 Substrate 3 Gate insulating film 4 Gate electrode 5 Interlayer insulating film 6 Barrier metal layer 7 Source electrode 8 Drain electrode 11 N ⁻ type drain region 12 P ⁻ type channel region 13 N ⁺ type source region 14 Trench 31 SiO ₂ film 32 SiN film 33 mask layer 33a opening 35 polysilicon layer 36 ion implantation layer

Claims (8)

An oxide film is formed on the substrate, a nitride film is formed on the oxide film, a resist film is formed on the nitride film, and a part of the oxide film and the nitride film is etched. a mask layer forming step of forming an apertured insulating mask layer on the substrate,
A trench formation step of forming a trench having an upper end opened in the substrate in the region exposed from the mask layer;
A burying step of burying a semiconductor layer in the trench;
A second ion implantation step of implanting ions into the substrate to form a conductive semiconductor region;
A first ion implantation step of implanting ions different from the semiconductor material constituting the semiconductor layer into the semiconductor layer embedded in the trench after the second ion implantation step;
An interlayer insulating film forming step of forming an interlayer insulating film by thermally oxidizing the semiconductor layer in the region where the ions are implanted in the first ion implantation step ;
A removal step of removing the mask layer after the ion implantation step ,
The method of manufacturing a trench type semiconductor device , wherein an acceleration voltage in the first ion implantation step is smaller than an acceleration voltage in the second ion implantation step . The concentration of impurities in the interlayer insulating film according to the first ion implantation step, a trench-type semiconductor according to claim 1, wherein greater than the concentration of the impurity of the conductivity type semiconductor region by the second ion implantation step Device manufacturing method. The dose of the first ion implantation step, a manufacturing method of a trench type semiconductor device according to claim 1 or claim 2, wherein greater than the dose of the second ion implantation process. 4. The method of manufacturing a trench type semiconductor device according to claim 1, wherein a reactive ion etching method is applied to the trench forming step. 5. The trench forming step further includes
The method for manufacturing a trench type semiconductor device according to any one of claims 1 to 4, further comprising a step of forming a gate insulating film by thermal oxidation. The embedding process includes
Forming a semiconductor layer in the trench and on the upper surface of the mask layer;
Removing the upper surface of the semiconductor layer by etching so as to remain only inside the trench,
6. The method of manufacturing a trench type semiconductor device according to claim 1, wherein the mask layer functions as an etching stopper during the etching. The acceleration voltage in the second ion implantation step is an acceleration voltage at which the ions implanted in the second ion implantation step pass through the mask layer, and the acceleration voltage in the first ion implantation step is the first voltage The method for manufacturing a trench type semiconductor device according to any one of claims 1 to 6, wherein the ion implanted in one ion implantation step is an acceleration voltage blocked by the mask layer. The acceleration voltage of the second ion implantation step is 40 keV to 180 keV, and the acceleration voltage of the first ion implantation step is 5 keV to 40 keV. 2. A method for manufacturing a trench type semiconductor element according to item 1.

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