JP2010062477A - Trench type semiconductor device and its manufacturing method - Google Patents

Abstract

A fine structure is realized by self-alignment, on-resistance is reduced, and breakdown resistance is improved.
A gate insulating film 3 disposed on a bottom surface 14a and a side wall surface 14b of a trench 14 formed from the surface of a first base layer 11, and a gate electrode 4 disposed on the gate insulating film 3 to fill the trench. And an interlayer insulating film 5 covering the gate electrode 4, a second base layer 12 disposed on the surface of the first base layer 11 and formed shallower than the bottom surface of the trench, and a surface of the second base layer 12. The source layer 13 is connected to the second base layer 12 at the bottom surface 15a of the self-aligned contact groove 15 formed up to the second base layer 12 using the interlayer insulating film 5 as a mask, and the source layer 13 is connected to the side wall surface 15b. A trench type comprising a connected source electrode 7, a drain layer 10 disposed on the back surface of the first base layer 11, and a drain electrode 8 disposed on the drain layer 10. Conductor device and a manufacturing method thereof.
[Selection] Figure 1

Description

  The present invention relates to a trench type semiconductor device and a method for manufacturing the same, and more particularly to a trench type semiconductor device that realizes a fine structure by complete self-alignment, reduces on-resistance, and improves breakdown tolerance, and a method for manufacturing the same.

  Conventionally, a vertical insulating gate field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT) in which a trench is formed in a substrate and a gate electrode is formed in the trench, etc. A trench type semiconductor device and a manufacturing method thereof are known. In such a trench type semiconductor device, an interlayer insulating film is formed so as to close the opening of the trench. The interlayer insulating film insulates the electrode inside the trench from the external electrode.

  Patent Document 1 includes an n-type silicon substrate in which a trench is formed, a polysilicon gate formed in the trench, and a local oxide film (interlayer insulating film) formed on the upper surface of the n-type silicon substrate. A trench type MOS transistor is disclosed.

  The n-type silicon substrate includes a high-concentration p-type bulk layer formed on both ends of the trench, a low-concentration p-type bulk layer formed between the p-type bulk layer and the trench, and a p-type bulk. An n-type source layer formed in the upper layer portion of the layer is formed. A part of the local oxide film is also formed between the inner wall surface of the trench and the polysilicon gate.

  In the method of manufacturing a MOS transistor described in Patent Document 1, after forming a p-type bulk layer on an n-type silicon substrate, a silicon nitride film and a low-temperature oxide film for forming a patterned trench are formed. Next, after forming the trench, the low-temperature oxide film is removed. Next, a polysilicon gate is formed in the trench.

  Next, a local oxide film is formed on the polysilicon gate by heat treatment based on a local oxidation of silicon (LOCOS) method. Thereafter, after the silicon nitride film is removed, p-type impurities and n-type impurities are sequentially ion-implanted to form low-concentration p-type bulk layers and n-type bulk layers. Here, since a thin thermal oxide film remains on the upper surface of the layer forming the low-concentration p-type bulk layer and the n-type bulk layer, ions to be implanted pass through the thin thermal oxide film. Implanted with acceleration voltage. For this reason, many of the implanted ions pass through the thick local oxide film on the polysilicon gate and do not remain inside the local oxide film. Thereby, the MOS transistor described in Patent Document 1 is completed.

  However, the MOS transistor described in Patent Document 1 forms a local oxide film by segregating the upper surface of the polysilicon gate by heat treatment. For this reason, there exists a subject that it is not easy to make it the thickness which can insulate a polysilicon gate with a local oxide film. In order to make the local oxide film in such a thickness that can be insulated, methods such as high-temperature or long-time heat treatment can be considered. However, in these methods, another problem such as deterioration of element characteristics of the manufactured MOS transistor is considered. Occurs.

Further, in a MOSFET or IGBT having a trench type gate structure, when a contact is formed on the base layer and the emitter layer or the source layer between the trench and the trench, the contact area can be ensured together with the miniaturization of the device structure. It was difficult. For this reason, as the contact area is reduced, there is a problem that the on-resistance increases and the breakdown tolerance decreases.
JP-A-9-321303

  An object of the present invention is to provide a trench type semiconductor device that realizes a fine structure by self-alignment, reduces on-resistance, and improves breakdown resistance, and a method for manufacturing the same.

  According to one aspect of the present invention for achieving the above object, the first base layer of the first conductivity type having high resistance and the bottom surface and the side wall surface of the trench formed from the surface of the first base layer are disposed. A gate insulating film, a gate electrode disposed on the gate insulating film and filling the trench, an interlayer insulating film disposed to cover the gate electrode, and a surface of the first base layer, A second conductive type second base layer formed shallower than the bottom surface of the trench, a first conductive type first main electrode layer disposed on the surface of the second base layer, and the interlayer insulating film as a mask The first main electrode layer is connected to the second base layer at the bottom surface of the self-aligned contact groove formed to the inside of the second base layer, and the first main electrode layer is connected to the side wall surface of the self-aligned contact groove. Electrode layer There is provided a semiconductor device comprising a connected first main electrode, a second main electrode layer disposed on the back surface of the first base layer, and a second main electrode disposed on the second main electrode layer. .

  According to another aspect of the present invention, a first resistance type first base layer having a high resistance is formed, and a gate insulating film is formed on the bottom surface and the side wall surface of the trench formed from the surface of the first base layer. A step of forming a gate electrode filling the trench on the gate insulating film, a step of forming an interlayer insulating film by covering the gate electrode, and a surface of the first base layer, Forming a second conductivity type second base layer formed shallower than a bottom surface of the trench; forming a first conductivity type first main electrode layer on a surface of the second base layer; A side wall surface of the self-alignment contact groove, which is connected to the second base layer at the bottom surface of the self-alignment contact groove formed through the first main electrode layer using the interlayer insulating film as a mask and into the second base layer. In Forming a first main electrode connected to the first main electrode layer; forming a second main electrode layer on a back surface of the first base layer; and a second main electrode on the second main electrode layer. A method for manufacturing a semiconductor device is provided.

  According to the present invention, it is possible to provide a trench type semiconductor device that realizes a fine structure by self-alignment, reduces on-resistance, and improves breakdown tolerance, and a method for manufacturing the same.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following, the same reference numerals are assigned to the same blocks or elements to avoid duplication of explanation and simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention. In the embodiments of the present invention, the arrangement of each component is as follows. Not specific. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

  The trench type semiconductor device according to the embodiment of the present invention is intended for a MOSFET or an IGBT. In the case of MOSFET, the first main electrode layer 13 forms a source layer, the second main electrode layer 10 forms a drain layer of the same first conductivity type as the first main electrode layer 13, and the first main electrode 7 forms a source electrode. The second main electrode 8 forms a drain electrode. In the case of the IGBT, the first main electrode layer 13 forms an emitter layer, the second main electrode layer 10 forms a second conductivity type collector layer opposite to the first main electrode layer 13, and the first main electrode 7 The emitter electrode and the second main electrode 8 form a collector electrode.

  In the following description, the MOSFET is mainly described. However, the IGBT is the same as the MOSFET, assuming that the conductivity type of the second main electrode layer 10 is reversed and that the names of the main electrodes may be changed. Can think.

[First embodiment]
(Element structure)
A schematic cross-sectional structure of the trench type semiconductor device according to the first embodiment of the present invention is expressed as shown in FIG. Moreover, the lattice-like planar pattern configuration of the trench type semiconductor device according to the first embodiment is expressed as shown in FIG. FIG. 1 corresponds to a schematic cross-sectional structure taken along line II in FIG.

As shown in FIG. 1, the trench type semiconductor device according to the first embodiment of the present invention includes an n ⁻ -type first base layer 11 and a trench 14 formed from the surface of the n ⁻ -type first base layer 11. The gate insulating film 3 disposed on the bottom surface 14a and the side wall surface 14b, the gate electrode 4 disposed on the gate insulating film 3 and filling the trench 14, and the interlayer insulating film 5 disposed so as to cover the gate electrode 4 P-type second base layer 12 disposed on the surface of n ⁻ -type first base layer 11 and formed shallower than bottom surface 14a of trench 14, and n ^- type disposed on the surface of p-type second base layer 12. ^The p-type second base 13 is formed on the bottom surface 15a of the self-aligned contact groove 15 that penetrates the n-type source layer 13 and the p-type second base layer 12 through the n ⁺ -type source layer 13 using the interlayer insulating film 5 as a mask. Cell connected to layer 12 In the side wall surface 15b of the Hua line contact grooves 15, the source electrode 7 connected to the n ⁺ -type source layer 13, n ^- and n ⁺ -type drain layer 10 disposed on the rear surface of the mold first base layer 11, n ⁺ A drain electrode 8 disposed on the mold drain layer 10.

The bottom surface 15 a of the self-aligned contact groove 15 may be provided with a body contact layer 12 a that is p ⁺ type and has a higher impurity density than the p-type second base layer 12.

  The first base layer 11 starts from the substrate 2 and decreases in thickness with the formation of the second base layer 12, the source layer 13, and the drain layer 10. In the final completed device, the first base layer 11 has a predetermined thickness. Have Therefore, in the completed device structure shown in FIG. 1, the substrate 2 is represented as a layer including the first base layer 11, the second base layer 12, the source layer 13, and the drain layer 10.

  As shown in FIG. 1, the interlayer insulating film 5 is formed of a LOCOS oxide film, and is disposed so as to cover part of the gate insulating film 3 and part of the source layer 13.

  As shown in FIG. 1, a body contact layer 12 a having a higher impurity density than the second base layer 12 may be provided on the bottom surface 15 a of the self-aligned contact groove 15.

  As shown in FIG. 1, the source electrode 7 may be disposed on the entire surface of the device.

  Further, the source electrode 7 may include a barrier metal layer 6 as a base as shown in FIG.

  Since the first base layer 11 and the second base layer 12 are advantageous in terms of electron mobility, the plane orientation may have a (100) plane.

  The trench 14 formed from the surface of the source layer 13 to the first base layer 11 through the source layer 13 and the second base layer 12 has, for example, a rectangular planar pattern.

  Since the bottom surface 14a and the side wall surface 14b of the trench 14 are advantageous in terms of electron mobility, both may have a (100) plane or a plane parallel thereto.

  Since the bottom surface 15a and the side wall surface 15b of the self-alignment contact groove 15 are advantageous in terms of electron mobility, both may have a (100) plane or a plane parallel thereto.

  The self-aligned contact groove 15 has a lattice pattern as shown in FIG. 2 or a staggered pattern as shown in FIG.

  The trench type semiconductor device according to the first embodiment adopts a lattice pattern as shown in FIG. 2 by adjusting the exposure amount. In the lattice pattern as shown in FIG. 2, pattern dulling due to variations in exposure amount is likely to occur particularly at the intersection of the trench 14 pattern. In the portion where the bluntness of the pattern occurs, a plane orientation different from the (100) plane is likely to occur on the inner wall surface of the trench. In the staggered pattern as shown in FIG. 3, the pattern of the trenches 14 is arranged in a staggered pattern, so that the pattern is less likely to be dull due to variations in exposure amount. Further, the self-alignment contact groove 15 may be formed in a stripe shape as shown in FIG.

  FIG. 5 shows a schematic bird's-eye view of the trench type semiconductor device according to the first embodiment. FIG. 5 shows a cross-sectional structure taken along line II-II of the lattice pattern of FIG. 2 and a bird's-eye view structure including the cross-sectional structure. As is apparent from FIG. 5, since the trench semiconductor device according to the first embodiment has a self-aligned contact structure, when viewed from above, the region other than the interlayer insulating film 5 by the LOCOS oxide film is A source electrode 7 can be formed on the entire surface of the device structure with respect to the self-aligned contact groove 15 in which the self-aligned contact groove 15 is formed.

  Hereinafter, materials and dimension examples of each layer of the trench type semiconductor device 1 according to the first embodiment will be described.

The substrate 2 is mainly made of n ⁻ type silicon.

The p-type second base layer 12 has a thickness of about 0.3 μm, for example. The p-type second base layer 12 is doped with B (boron) as a p-type impurity. The p-type second base layer 12 has an impurity density of about 2.0 × 10 ¹⁶ atoms / cm ^3, for example.

The n ⁺ type source layer 13 has a thickness of about 0.2 μm, for example. The n ⁺ -type source layer 13 is doped with As (arsenic) as an n-type impurity. The n ⁺ type source layer 13 has an impurity density of about 1.0 × 10 ¹⁹ atoms / cm ^3, for example.

A trench 14 is formed in the substrate 2 to divide the n ⁺ -type source layer 13 at a predetermined interval. Trenches 14 through the p-type second base layer 12 and the n ⁺ -type source layer 13. That is, the trench 14 reaches the n ⁻ -type first base layer 11 from the upper surface of the substrate 2. The trench 14 has a depth of about 1 μm, for example, and has a width of about 0.25 to 0.5 μm, for example. The pitch interval between the adjacent trenches 14 and the trenches 14 is, for example, about 0.6 μm to 1.0 μm. The width of the self-aligned contact groove 15 is, for example, about 0.2 μm.

The gate insulating film 3 is for insulating the substrate 2 and the gate electrode 4. The gate insulating film 3 is made of a silicon oxide film (SiO ₂ ) and has a thickness of about 20 nm to 100 nm, for example.

  The gate electrode 4 is for forming a channel in the p-type second base layer 12. The gate electrode 4 is embedded in the trench 14. The gate electrode 4 is made of polysilicon containing impurities.

  The interlayer insulating film 5 is for insulating the gate electrode 4 and the source electrode 7.

The interlayer insulating film 5 is made of an insulating material mainly composed of SiO ₂ . The interlayer insulating film 5 contains ion-implanted As (arsenic) as an impurity. Here, As (arsenic) contained in the interlayer insulating film 5 is for increasing the volume of the interlayer insulating film 5. The impurity concentration of As (arsenic) in the interlayer insulating film 5 is, for example, about ^{1.0 × 10 19 atoms / cm 3} ~ about 1.0 × 10 ²¹ atoms / cm ³ or so. That is, the impurity concentration of As (arsenic) in the interlayer insulating film 5 is higher than the impurity concentration of each layer 11, 12, 13. The interlayer insulating film 5 has a thickness of about 150 nm, for example. The width of the interlayer insulating film 5 is about 10 nm to about 20 nm larger than the width of the trench 14.

  The source electrode 7 is made of Al (aluminum) or Al / Cu (copper).

  The barrier metal layer 6 is for suppressing the diffusion of the metal element constituting the source electrode 7 into the substrate 2 or the like. For example, titanium (Ti), platinum (Pt), nickel (Ni), tungsten (W), or a silicide film thereof can be applied to the barrier metal layer 6.

The barrier metal layer 6 penetrates the n ⁺ -type source layer 13 of the interlayer insulating film 5 as a mask, p-type second base layer at the bottom surface 15a of the self-aligned contact grooves 15 formed to the p-type second base layer 12 12, and may be connected to the n ⁺ -type source layer 13 on the side wall surface 15 b of the self-aligned contact groove 15. Further, the barrier metal layer 6 may be formed so as to cover the entire upper surface of the interlayer insulating film 5.

The n ⁺ type drain layer 10 has a thickness of about 0.2 μm, for example. The n ⁺ -type drain layer 10 is doped with As (arsenic) or P (phosphorus) as an n-type impurity. The n ⁺ -type drain layer 10 has an impurity density of about 1.0 × 10 ¹⁹ atoms / cm ^3, for example.

  The drain electrode 8 is made of W (tungsten). The drain electrode 8 is formed on the entire lower surface of the substrate 2.

  The operation of the above-described trench type semiconductor device 1 will be described.

First, a predetermined voltage is applied to the gate electrode 4. As a result, a channel is formed in the p-type second base layer 12 in the vicinity of the interface between the gate insulating film 3 and the p-type second base layer 12. In this state, when a voltage is applied between the source electrode 7 and the drain electrode 8, electrons pass through the n ⁺ -type source layer 13, the p-type second base layer 12 channel, and the n ⁻ -type first base layer 11. It moves and reaches the n ⁺ type drain layer 10. As a result, a current flows between the source electrode 7 and the drain electrode 8.

  On the other hand, in the case of an IGBT, it operates in a latch-up operation mode similar to that of a thyristor, or operates in a non-latch-up operation mode equivalent to that of a bipolar transistor without performing a latch-up operation.

(Production method)
The method of manufacturing a trench type semiconductor device according to the first embodiment includes a step of forming a first base layer 11 having a high resistance and a first conductivity type, as shown in FIGS. 11, a step of forming the gate insulating film 3 on the bottom surface 14a and the side wall surface 14b of the trench 14 formed from the surface, a step of forming the gate electrode 4 filling the trench 14 on the gate insulating film 3, and a gate electrode 4, a step of forming an interlayer insulating film 5 by covering 4, a step of forming a p-type second base layer 12 formed shallower than the bottom surface 14 a of the trench 14 on the surface of the first base layer 11, A step of forming an n ⁺ -type source layer 13 on the surface of the base layer 12 and a self-aligned contact formed through the n ⁺ -type source layer 13 using the interlayer insulating film 5 as a mask and into the p-type second base layer 12 Bottom surface 1 of groove 15 Is connected to the p-type second base layer 12 in 5a, in the side wall surface 15b of the self-aligned contact groove 15, forming a source electrode 7 connected to the n ⁺ -type source layer 13, the back surface of the first base layer 11 and a step of forming an n ⁺ -type drain layer 10, and forming a drain electrode 8 to the n ⁺ -type drain layer 10 to.

  The interlayer insulating film 5 is formed of a LOCOS oxide film and covers a part of the gate insulating film 3 and a part of the source layer 13.

  In the step of forming the source electrode 7, the source electrode 7 may be formed on the entire device surface.

  The step of forming the source electrode 7 may include a step of forming the barrier metal layer 6 on the base of the source electrode 7.

  In each step of forming the first base layer 11 and the second base layer 12, it is desirable that the first base layer 11 and the second base layer 12 have a (100) plane orientation.

  In the step of forming the trench 14, the trench 14 may have, for example, a rectangular structure in a planar pattern.

  In the step of forming the trench 14, it is desirable that both the bottom surface 14a and the side wall surface 14b of the trench 14 have a (100) plane.

  In the step of forming the self-alignment contact groove 15, it is desirable that both the bottom surface 15a and the side wall surface 15b of the self-alignment contact groove 15 have a (100) plane or a plane parallel to the (100) plane.

  In the step of forming the self-aligned contact groove 15, the self-aligned contact groove 15 may have a lattice pattern or a staggered pattern.

  Next, a manufacturing method of the trench type semiconductor device 1 described above will be described with reference to the drawings. 6 to 18 are views for explaining a method of manufacturing the trench type semiconductor device according to the first embodiment.

(A) First, as shown in FIG. 6, an oxide film (SiO ₂ film) 31 having a thickness of about 10 nm is formed on the substrate 2. Note that the thickness of the oxide film 31 can be appropriately changed between about 5 nm and 20 nm, for example. Thereafter, a nitride film (SiN film) 32 having a thickness of about 75 nm is formed on the oxide film 31, for example. Note that the thickness of the nitride film 32 can be appropriately changed between about 50 nm and 200 nm, for example. Next, a resist film (not shown) is formed on the nitride film 32 by photolithography. Thereafter, as shown in FIG. 6, a part of the nitride film 32 and the oxide film 31 is etched to form an insulating mask layer 33 having an opening 33a in part on the substrate 2 (mask). Layer forming step).

(B) Next, as shown in FIG. 7, the substrate 2 in the region exposed from the mask layer 33 is removed by etching by a reactive ion etching (RIE) method. As a result, a trench 14 having an upper end opened is formed in the region of the substrate 2 exposed from the mask layer 33 (trench formation step).

(C) Next, as shown in FIG. 8, the inner wall portion of the trench 14 is thermally oxidized to form the gate insulating film 3 made of SiO ₂ . Here, a Bird's Beak-shaped LOCOS oxide film 3a is formed on the oxide film 31 underlying the nitride film 32 by thermal oxidation from the lateral direction.

(D) Next, as shown in FIG. 9, a polysilicon layer 35 is formed in the trench 14 and on the upper surface of the mask layer 33 by a low pressure chemical vapor deposition (LPCVD) method (see FIG. 9). Burial process).

(E) Next, as shown in FIG. 10, the upper surface of the polysilicon layer 35 is removed by etching so that the polysilicon layer 35 remains only in the trench 14. Here, the mask layer 33 functions as an etching stopper. For this reason, the substrate 2 below the mask layer 33 is not etched.

(F) Next, acceleration is performed at a voltage of about 40 keV to about 180 keV, for example, and a dose amount of about 1.0 × 10 ¹² atoms / cm ² to about 1.0 × 10 ¹⁴ atoms / cm ² is used. B (boron) is ion-implanted from the upper surface of the substrate 2. Thereafter, B (boron) is diffused by heating the substrate 2 to form the p-type second base layer 12 as shown in FIG.

(G) Next, acceleration is performed at a voltage of, for example, about 40 keV to about 180 keV, for example, As having a dose amount of about 1.0 × 10 ¹⁴ atoms / cm ² to about 1.0 × 10 ¹⁶ atoms / cm ^2. (Arsenic) is ion-implanted from the upper surface of the substrate 2. Thereafter, as shown in FIG. 11, the substrate 2 is heated to diffuse As (arsenic) and form an n ⁺ -type source layer 13 (second ion implantation step). Here, B (boron) and As (arsenic) are implanted at an accelerating voltage that can pass through the mask layer 33.

(H) Next, as shown in FIG. 12, As (arsenic) ions different from Si (silicon) constituting the polysilicon layer 35 are implanted into the upper surface of the polysilicon layer 35 embedded in the trench 14. Here, As (arsenic), for example, about ^{5 × 10 15 atoms / cm 2} ~5 × 10 16 atoms / cm 2 dose of about, and, for example, are implanted at an acceleration voltage of about 5keV~40keV . As a result, the upper end portion of the polysilicon layer 35 is made amorphous. As a result, an ion implantation layer 36 is formed on the polysilicon layer 35. Since the acceleration voltage of As (arsenic) in this process is small, As (arsenic) is blocked by the mask layer 33. For this reason, As (arsenic) is hardly implanted into the n ⁺ -type source layer 13 of the substrate 2. Further, the polysilicon layer 35 in a region where As (arsenic) ions are not implanted becomes the gate electrode 4 (first ion implantation step). Here, the As (arsenic) impurity concentration of the ion implantation layer 36 ion-implanted in the first ion implantation step is higher than the impurity concentration of the regions 12 and 13 ion-implanted in the second ion implantation step.

(I) Next, the substrate 2 is heated at about 900 ° C. for about 30 minutes. As a result, as shown in FIG. 13, the ion-implanted layer 36 into which As (arsenic) ions are implanted is thermally oxidized, and the volume is amplified. As a result, an interlayer insulating film (LOCOS insulating film) 5 having a thickness of about 300 nm, for example, is formed on the gate electrode 4 so as to close the opening of the trench 14 (interlayer insulating film forming step). Here, the interlayer insulating film 5 may be formed by a general LOCOS method. In this case, it is necessary to heat the substrate at about 1100 ° C. for about 60 minutes. In the manufacturing method according to the first embodiment described above, the interlayer insulating film 5 is formed at a lower temperature and in a shorter time than the general LOCOS method.

(J) Next, as shown in FIG. 14, the nitride film 32 of the mask layer 33 is removed by etching.

(K) Next, as shown in FIG. 15, the oxide film 31 is removed by etching. Here, part of the interlayer insulating film 5 mainly composed of a silicon oxide film (SiO ₂ film) is also removed by this etching process. However, the thickness of the interlayer insulating film 5 is very large compared to the thickness of the oxide film 31. For this reason, when viewed from the whole interlayer insulating film 5, the interlayer insulating film 5 to be removed is extremely small and does not cause a problem.

(L) Next, as shown in FIG. 16, a self-aligned contact trench 15 is formed in a self-aligning manner using the interlayer insulating film 5 as a mask. The depth of the self-aligned contact grooves 15, as shown in FIG. 16, through the n ⁺ -type source layer 13, the bottom surface 15a of the self-aligned contact groove 15, reaches the p-type second base layer 12. In the formation of the self-alignment contact groove 15 described above, the RIE method similar to the silicon dry etching technique in which the trench 14 is formed can be applied (self-alignment contact groove formation step).

(M) Next, as shown in FIG. 17, a barrier metal layer 6 is formed so as to cover the entire device surface. Here, the barrier metal layer 6 is connected to the second base layer 12 at the bottom surface 15 a of the self-aligned contact groove 15, and is connected to the source layer 13 at the side wall surface 15 b of the self-aligned contact groove 15.

(N) Next, as shown in FIG. 18, the source electrode 7 is formed so as to cover the entire device surface.

(O) Next, the back surface of the substrate 2 is polished by a chemical mechanical polishing (CMP) technique, the substrate 2 is thinned, and then an n ⁺ -type drain layer is formed on the back surface of the first base layer 11. 10 is formed using diffusion or ion implantation techniques. The reason for thinning the substrate 2 is to increase the speed by shortening the traveling distance of electrons between the source layer 13 and the drain layer 10 while ensuring a predetermined breakdown voltage.

(O) Finally, the drain electrode 8 is formed on the lower surface of the substrate 2. Thereby, the trench type semiconductor device 1 shown in FIG. 1 is completed.

  As described above, the trench type semiconductor device 1 according to the first embodiment ion-implants As (arsenic) different from Si (silicon), which is a semiconductor material constituting the interlayer insulating film 5, into the interlayer insulating film 5. is doing. Further, in the trench type semiconductor device 1, the impurity concentration of the interlayer insulating film 5 is made larger than the impurity concentration of the regions 12 and 13. For this reason, in the step of forming the interlayer insulating film 5 by heating the ion implantation layer 36, a large amount of As (arsenic) is taken in between the Si (silicon) atoms of the ion implantation layer 36. The amplification factor can be increased. Thereby, the insulation by the interlayer insulating film 5 can be improved, and a short circuit between the source electrode 7 and the gate electrode 4 can be suppressed. Further, the interlayer insulating film 5 can be formed by oxidation and volume amplification by heating at a low temperature for a short time as compared with the formation temperature and time by general LOCOS. Thereby, in each layer 11, 12, 13, it can suppress that an impurity diffuses by the heating for forming the interlayer insulation film 5. FIG. As a result, deterioration of element characteristics of the trench type semiconductor device 1 can be suppressed.

  In the first embodiment, the interlayer insulating film 5 between the electrodes is formed by self-alignment by LOCOS, and further, a fine contact hole is formed in a self-aligned manner between the trenches using the LOCOS oxide film as a mask. It becomes possible.

  According to the first embodiment, the interlayer insulating film 5 includes a semiconductor material and an impurity made of a different element from the semiconductor material, and the impurity concentration of the interlayer insulating film 5 is the impurity in the semiconductor region formed in the substrate. It is larger than the concentration. Thereby, the volume of the interlayer insulating film 5 can be easily increased and formed thick.

  According to the first embodiment, the self-aligned contact groove 15 deeper than the diffusion depth of the source layer 13 is formed in the region where the contact is conventionally formed, using the interlayer insulating film 5 above the trench 14 as a mask. . As a result, a source contact is made on the side wall surface 15 b of the self-alignment contact groove 15 and a body contact is made on the bottom surface 15 a of the self-alignment contact groove 15. With this self-aligned contact structure, the contact area can be greatly increased as compared with the conventional structure, the contact resistance can be reduced, and the on-resistance can be reduced.

  According to the first embodiment, the contact area is increased due to the structure of the self-aligned contact groove 15, so that the contact resistance of the source contact portion which is a current path is reduced, and the on-resistance when the MOSFET is conductive can be reduced.

  Furthermore, according to the first embodiment, the body contact connection method, which has been a problem of miniaturization, and the contact area can be connected in a self-aligned and reliable manner at the bottom of the self-aligned contact hole. Therefore, it is possible to improve the destruction resistance against avalanche destruction, body diode (BD) destruction, and the like.

After the LOCOS interlayer film is formed and the SiN film is removed, the entire surface is etched with silicon deeper than the junction depth of the source layer 13. By this step, the silicon etching region is determined in a self-aligned manner, and miniaturization becomes possible.

  Further, the mask layer 33 functions as a mask in the process of forming the trench 14 and also functions as a mask in the process of forming the interlayer insulating film 5. That is, the trench 14 and the interlayer insulating film 5 can be formed by self-alignment. As a result, the relative position between the trench 14 and the interlayer insulating film 5 can be prevented from shifting, and thus the interlayer insulating film 5 can be formed at an accurate position of the upper end portion of the trench 14.

  Further, by using the interlayer insulating film 5 formed in the self-alignment, the self-alignment contact groove 15 can be formed in the self-alignment, the contact area can be increased, the contact resistance is reduced, and the on-resistance is reduced. Can be planned.

  According to the first embodiment, in a MOSFET, IGBT, or the like having a trench type gate structure, an interelectrode interlayer film necessary for the upper part of the trench is formed by self-alignment by LOCOS, and the LOCOS oxide film is further used as a mask. Then, a silicon groove is formed between the trenches, and a metal layer is formed in the dug groove. As a result, contact holes can be formed in a self-aligned manner. This self-aligned contact makes it possible to make contact in the vertical direction, so the contact area, which was a problem of miniaturization, can be improved, and the on-resistance and the breakdown resistance are improved. be able to.

  According to the first embodiment, it is possible to provide a trench type semiconductor device that realizes a fine structure by complete self-alignment, reduces on-resistance, and improves breakdown resistance, and a method for manufacturing the same.

[Other embodiments]
As described above, the present invention has been described according to the first embodiment. However, it should be understood that the descriptions and drawings constituting a part of this disclosure are illustrative and limit the present invention. Absent. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, in the first embodiment, the embodiment applied to the MOSFET has been described. However, the present invention may be applied to other trench type semiconductor devices such as IGBTs.

  In addition, the materials, shapes, numerical values, and the like of the components in the above-described embodiments can be changed as appropriate.

For example, the elements (ions) implanted into the interlayer insulating film 5 are B (boron), N (nitrogen), O (oxygen), Ne (neon), P (phosphorus), Ar (argon), Kr (krypton). Sb (antimony) or the like can be applied. The impurity concentration of the element implanted into the interlayer insulating film 5 can be changed as appropriate as long as it is higher than the impurity density of the p-type second base layer 12 and the n ⁺ -type source layer 13 formed on the substrate 2. For example, the impurity density of the element implanted into the interlayer insulating film 5 may be set, for example, between about 1.0 × 10 ¹⁴ atoms / cm ³ to about 1.0 × 10 ²¹ atoms / cm ^3. .

Further, the acceleration voltage at the time of implanting impurities into the p-type second base layer 12 and the n ⁺ -type source layer 13 can be changed as appropriate as long as it can pass through the mask layer 33. For example, the acceleration voltage at the time of implanting impurity into the p-type second base layer 12 and the n ⁺ -type source layer 13 may be set between about 20keV~ about 180 keV.

  As described above, the present invention includes various embodiments not described herein.

  The semiconductor device of the present invention can be applied to various AC-AC, AC-DC, DC-DC, DC-AC power converters, etc. from low power to large power including DC-DC converters and PWM inverters. Specifically, the present invention can be applied to a bridge circuit using a high voltage MOSFET or IGBT, an LCD inverter, a motor, an automobile HID (High Intensity Discharge lamp) headlight lighting device, and the like.

1 is a schematic cross-sectional structure diagram of a trench type semiconductor device according to a first embodiment of the present invention. FIG. 3 is a configuration diagram of a lattice-like planar pattern of the trench type semiconductor device according to the first embodiment of the present invention. 1 is a staggered planar pattern configuration diagram of a trench type semiconductor device according to a first embodiment of the present invention. FIG. 1 is a stripe planar pattern configuration diagram of a trench type semiconductor device according to a first embodiment of the present invention. FIG. 1 is a schematic bird's-eye view of a trench type semiconductor device according to a first embodiment of the present invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the trench type semiconductor device according to the first embodiment of the invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the trench type semiconductor device according to the first embodiment of the invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the trench type semiconductor device according to the first embodiment of the invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the trench type semiconductor device according to the first embodiment of the invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the trench type semiconductor device according to the first embodiment of the invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the trench type semiconductor device according to the first embodiment of the invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the trench type semiconductor device according to the first embodiment of the invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the trench type semiconductor device according to the first embodiment of the invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the trench type semiconductor device according to the first embodiment of the invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the trench type semiconductor device according to the first embodiment of the invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the trench type semiconductor device according to the first embodiment of the invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the trench type semiconductor device according to the first embodiment of the invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the trench type semiconductor device according to the first embodiment of the invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Trench type semiconductor device 2 ... Substrate 3 ... Gate insulating film 3a ... LOCOS oxide film 4 ... Gate electrode 5 ... Interlayer insulating film (LOCOS insulating film)
6 ... Barrier metal layer 7 ... First main electrode (source electrode, emitter electrode)
8 ... Second main electrode (drain electrode, collector electrode)
10: Second main electrode layer (drain layer, collector layer)
DESCRIPTION OF SYMBOLS 11 ... 1st base layer 12 ... 2nd base layer 12a ... Body contact layer 13 ... 1st main electrode layer (source layer, emitter layer)
DESCRIPTION OF SYMBOLS 14 ... Trench 14a ... Trench bottom surface 14b ... Trench side wall surface 15 ... Self-aligned contact groove 15a ... Self-aligned contact groove bottom surface 15b ... Self-aligned contact groove side wall surface 31 ... Oxide film 32 ... Nitride film 33 ... Mask layer 33a ... Opening 35 ... Polysilicon layer 36 ... Ion implantation layer

Claims (23)

A first base layer of high resistance and first conductivity type;
A gate insulating film disposed on a bottom surface and a side wall surface of a trench formed from the surface of the first base layer;
A gate electrode disposed on the gate insulating film and filling the trench;
An interlayer insulating film disposed to cover the gate electrode;
A second base layer of a second conductivity type disposed on a surface of the first base layer and formed shallower than a bottom surface of the trench;
A first main electrode layer of a first conductivity type disposed on a surface of the second base layer;
Using the interlayer insulating film as a mask, it penetrates through the first main electrode layer and is connected to the second base layer at the bottom surface of the self-aligned contact groove formed to the inside of the second base layer. On the wall, a first main electrode connected to the first main electrode layer;
A second main electrode layer disposed on the back surface of the first base layer;
A trench type semiconductor device comprising: a second main electrode disposed on the second main electrode layer.   2. The trench according to claim 1, wherein the interlayer insulating film is formed of a LOCOS oxide film and is disposed so as to cover a part of the gate insulating film and a part of the first main electrode layer. Type semiconductor device.   3. The trench type semiconductor device according to claim 1, wherein a body contact layer having a second conductivity type and having an impurity density higher than that of the second base layer is provided on a bottom surface of the self-aligned contact groove.   The trench type semiconductor device according to claim 1, wherein the first main electrode is disposed on the entire device surface.   The trench type semiconductor device according to claim 1, wherein the first main electrode includes a barrier metal layer as a base.   The trench type semiconductor device according to claim 1, wherein the first base layer and the second base layer have a (100) plane orientation.   The trench type semiconductor device according to claim 1, wherein the trench formed up to the first base layer has a rectangular planar pattern.   8. The trench type semiconductor device according to claim 1, wherein a bottom surface and a side wall surface of the trench formed up to the inside of the first base layer each have a (100) surface. 9.   9. The trench type semiconductor device according to claim 1, wherein a bottom surface and a side wall surface of the self-aligned contact groove both have a (100) surface.   The trench type semiconductor device according to claim 1, wherein the self-aligned contact groove has a lattice pattern.   The trench type semiconductor device according to claim 1, wherein the self-aligned contact groove has a staggered pattern.   The trench type semiconductor device according to claim 1, wherein the self-aligned contact groove has a stripe pattern. Forming a first base layer of high conductivity and first conductivity type;
Forming a gate insulating film on a bottom surface and a side wall surface of a trench formed from the surface of the first base layer;
Forming a gate electrode filling the trench on the gate insulating film;
Forming an interlayer insulating film by covering the gate electrode;
Forming a second conductivity type second base layer formed shallower than a bottom surface of the trench on a surface of the first base layer;
Forming a first conductive type first main electrode layer on a surface of the second base layer;
Using the interlayer insulating film as a mask, it penetrates through the first main electrode layer and is connected to the second base layer at the bottom surface of the self-aligned contact groove formed to the inside of the second base layer. Forming a first main electrode connected to the first main electrode layer on the wall surface;
Forming a second main electrode layer on the back surface of the first base layer;
Forming a second main electrode on the second main electrode layer. A method of manufacturing a trench type semiconductor device, comprising:   14. The trench according to claim 13, wherein the interlayer insulating film is formed of a LOCOS oxide film and covers a part of the gate insulating film and a part of the first main electrode layer. Type semiconductor device manufacturing method.   15. The method of manufacturing a trench type semiconductor device according to claim 13, wherein in the step of forming the first main electrode, the first main electrode is formed on the entire device surface.   The trench type semiconductor device according to any one of claims 13 to 15, wherein the step of forming the first main electrode includes a step of forming a barrier metal layer on a base of the first main electrode. Manufacturing method.   The formation process of the first base layer and the second base layer, wherein the first base layer and the second base layer have a (100) plane orientation. A manufacturing method of a trench type semiconductor device given in any 1 paragraph.   18. The method of manufacturing a trench type semiconductor device according to claim 13, wherein, in the step of forming the trench, a planar pattern of the trench has a rectangular structure.   19. The method of manufacturing a trench type semiconductor device according to claim 13, wherein in the step of forming the trench, the bottom surface and the side wall surface of the trench both have a (100) surface. .   20. The trench according to claim 13, wherein in the step of forming the self-alignment contact groove, the bottom surface and the side wall surface of the self-alignment contact groove each have a (100) surface. Type semiconductor device manufacturing method.   21. The method of manufacturing a trench type semiconductor device according to claim 13, wherein in the step of forming the self-aligned contact groove, the self-aligned contact groove has a lattice pattern.   21. The method of manufacturing a trench type semiconductor device according to claim 13, wherein in the step of forming the self-alignment contact groove, the self-alignment contact groove has a staggered pattern. .   21. The method of manufacturing a trench type semiconductor device according to claim 13, wherein the self-aligned contact groove has a stripe pattern.

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