KR940001813B1 - Isolation method and device of semiconductor - Google Patents

Abstract

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Description

Semiconductor device element isolation method and semiconductor device having the device isolation region

1 is a process flow diagram illustrating a LOCOS method.

2 is a process flow chart illustrating a device isolation method of the present invention.

3 is a cross-sectional view of a semiconductor device having a trench structure showing an application of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to device isolation of semiconductor devices, and more particularly to semiconductor devices using device isolation techniques, as well as semiconductor devices having a novel device isolation region that can be usefully applied to miniaturized highly integrated semiconductor devices and a series of realizing the same. It relates to a manufacturing method of.

Currently, the most widely known techniques for semiconductor device isolation are the so-called local oxidation of silicon (LOCOS) method by selective oxidation and its improvements. LOCOS is a technique for roughly describing pad oxides, silicon nitride, and other films as masks to selectively oxidize substrate silicon to form field oxide films that are inactive regions.

An active region for an inactive region means a region between field oxide films, such as a desired semiconductor element formation region, and each element is electrically separated by a boundary between the separated regions.

The LOCOS process already established for the critical purpose of device isolation is described with reference to the process flow diagram in FIG.

In FIG. 1A, after the pad oxide layer 3 and the nitride layer are grown on the prepared semiconductor substrate 1, an opening A is formed using a photolithography process to define an isolation region or an inactive region. The layer to be etched is the nitride film 15. Then, in order to prevent field inversion through the open region, ion implantation of the same conductivity type as that of the semiconductor substrate is performed to form a channelstop layer 7.

Subsequently, the field oxide film 11 is formed by depositing an oxide layer in a thermal oxidation process by selective oxidation as shown in FIG.

The well-known technique is as described above, the problem is that the generation of bird beaks that invade the active region along the pad oxide film 3 and the high temperature treatment by the thermal oxidation process is the ion of the implanted ion layer 7 And dopant diffusion into the substrate, thereby making it impossible to maintain a high impurity concentration at the interface between the field oxide film, that is, the device isolation region and the substrate silicon, and furthermore the mechanical stress applied to the silicon substrate according to the selective thermal oxidation process. One problem is pointed out.

Although the above technique may be satisfactorily applied when forming a relatively low density integrated circuit, devices must be formed in a narrow area according to a trend toward increasingly integrated semiconductor devices, which means reduction of active regions between device isolation regions. Bud beak erosion to the narrowed active region makes it difficult to realize the fire-fighting semiconductor device, and even if it is formed, the required electrical properties are not obtained, and the electrical properties of the device are weakened by the diffusion of channel blocking ions in the process.

In FIG. 1B, the nitride layer 5 and the oxide layer 3, which acted as a mask during ion implantation, were removed, and a device isolation region as shown in FIG. 1C was formed. At this time, overetching by a buffered oxide etchant (BOE) solution of the pad oxide layer was performed. As shown in FIG. 1C, which is an enlarged view of the portion indicated by the circle of FIG. 1C, the depression p is formed at the plate and field oxide film and the surface boundary. It becomes a factor which lowers an electrical characteristic.

Since the conventional LOCOS family having many of these problems cannot be applied to realizing highly integrated semiconductor devices, improved LOCOS (ie, ALOCOS) methods have been developed in recent years.

The related art has been disclosed, for example, the so-called selective polysilicon oxidation (SEPOX) technology disclosed on pages 561-567 of IEEE Transition Electron Device Volume ED-29, No, 4, published in April 1982, but these related technologies are selective oxidation. In contrast, instead of oxidizing a substrate by inserting a polycrystalline silicon layer between the buffer oxide layer and the silicon nitride layer, the main purpose is to oxidize the crystalline silicon layer to form a field oxide film, which does not fundamentally solve the problem mentioned above.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems raised, and has a novel structure of a semiconductor device having no device erosion of a bird beak and a device structure of a novel structure which is applied during device isolation of a highly integrated semiconductor device by maintaining the concentration of the channel blocking layer. Its purpose is to provide a set of process steps for providing and preparing the same.

According to a first aspect of the present invention, there is provided a device isolation method of a semiconductor device, comprising: forming an insulating layer on a semiconductor substrate to form an opening for defining a device isolation region; Forming a first spacer in the opening and exposing the substrate to a region defined by the first spacer in the opening; Forming a polysilicon layer (DPS layer) containing impurities of the same conductive layer as the substrate on a region defined by the spacer in the opening; Performing a thermal process to diffuse impurities in the DPS layer formed in the openings into the substrate to form a channel blocking layer; Removing the insulating layer and depositing an oxide layer to form a second spacer in contact with the first spacer to form a spacer (S) spaced apart from each other with the DPS layer interposed therebetween; A method of separating a semiconductor device is provided, comprising forming a device isolation region by growing a thermal oxide film over an entire surface of a substrate including a DPS layer exposed when the spacer S is formed.

According to a second aspect of the invention, in a semiconductor device having an element isolation region, the device isolation region includes a spacer or insulating layer (S) having an approximately semicircular cross section, and the impurity-containing polysilicon (DPS) layer 19. And a device isolation region formed by including the insulating layer S of the one phase and a thermal oxidation layer formed thereon, and a channel stop layer 21 formed below the DPS layer. A phosphor semiconductor device is provided.

According to a third aspect of the present invention, in the device isolation method of a semiconductor device having a trench structure, the impurity layer formed on the inner circumferential surface of the trench is formed after the formation of the trench hole, and the polysilicon layer (DPS) containing impurities in the trench ) Is deposited, and a thermal process is performed so that impurities in the deposited DPS layer are diffused to the substrate to form an impurity layer.

The present invention has a step of forming a channel blocking layer by filling spacers and diffusion of impurities doped into a spacer defined region by placing a spacer in an opening in which an inactive region is defined, and by defining a device isolation region by the spacer. Provides no device isolation region.

There is also provided in the present invention a method of forming and forming a semiconductor wafer having another type of device isolation region formed by application to a device isolation pattern having a trench structure in accordance with the principles of the present invention.

In connection with the object of the present invention, the present invention is described with reference to FIG.

In FIG. 2A, as the starting material, a semiconductor substrate 11 of p-type semiconductor is used, and a pad oxide film 13 and a nitride film are sequentially formed on the substrate as an insulating layer for defining an inactive region or an element isolation region. In order to define the isolation region, the nitride film 15 deposited by the photolithography method is etched to form the opening 4.

In FIG. 2B, in order to form a spacer in the formed opening 4, an oxide film is deposited by a low pressure chemical vapor deposition method (LPCVD) and then an oxide film in the opening using a dry etching method such as reactive ion etching (RIE). 11) Etch until. A spacer 17 is formed on the sidewall of the nitride film 15 forming the opening, and the semiconductor substrate is exposed by dry etching the region 6 defined by the spacer.

Subsequently, a polysilicon layer containing boron in this embodiment is deposited over the entire surface of the substrate to fill doped polysilicon (hereinafter referred to as DPS) in a region defined by a spacer in the opening as shown in FIG. 2C. After etching, the DPS is filled into the opening.

At this time, the impurity doped in the polysilicon layer is to form the p ⁺ channel blocking layer 21 for the p-type semiconductor substrate, the process is as follows. That is, the DPS layer 19 deposited in the opening contains impurities and heat is applied to the wafer so that the impurities are diffused into the substrate to form the channel blocking layer 21. Impurities distributed in the substrate by diffusion exist near the spacers with little side diffusion occurring beyond the spacers 17 and beyond.

After forming the p ⁺ channel treatment layer 21 under the device isolation region as described above, the insulating layer 15 used as the buffer layer is wet-etched and removed using a phosphoric acid (H ₃ PO ₄ ) solution to form an oxide layer over the entire surface of the substrate. . Here, the formation method of the oxide layer and its thickness are important variables. In the formation method, since the thermal oxide film is grown while being exposed in the opening of the DPS layer, the thermal oxide film is grown while consuming this DPS layer, that is, to prevent this, that is, to form the oxide layer without changing the properties of the silicon layer by the LPCVD method. It is preferable to deposit and form an oxide layer.

In addition, in the thickness of FIG. 2C, the thickness is formed to be the same as or larger than the thickness for forming the spacer (hereinafter, referred to as the first spacer) in the opening. The reason is that the oxide film forms a space substantially symmetrically with the spacer formed first.

That is, as shown in FIG. 2E, the pad oxide layer 13 and the oxide layer 23 formed thereon are removed and the DPS layer 19 is exposed until the surface of the silicon substrate is exposed by dry etching. That is, the second spacer 25 is formed to be in contact with the first spacer symmetrically or smaller or larger than the first spacer to form a spacer S having a substantially semicircular cross section. This spacer S, which consists of two first and second spacers, constitutes an isolation region. A DPS layer is formed between the two spacers spaced apart, and the cross-sectional structure of FIG. 2e is typical of the device isolation region according to the present invention.

In FIG. 2E, the distance k from the point where the second spacer is in contact with the substrate to the p ⁺ channel blocking layer 21 is sufficiently secured, which is the reason for forming the second spacer, thereby blocking the channel by at least 'k' length. By suppressing or preventing ions from penetrating into the active region, the electrical properties of the device formed in the active region are not affected.

In order to form a complete device isolation region following the step of FIG. 2e, a thermal oxide film is grown based on the exposed DPS layer to form a device isolation region as shown in FIG. 2f. The cross section includes a DPS layer 19 in an insulating layer 29 constituting an isolation region, that is, a spacer of two oxide films and an insulating layer 29 of a thermal oxidation layer thereon, and a channel blocking layer 21 beneath it. ) Has a structure with. FIG. 2f shows that the thermal oxide layer formed on the device isolation region is also formed in the active region to form the gate oxide layer 10, which has advantages in the process progression in forming the MOS transistor element.

Also, in the bud beak problem, there is no room for bud beak because the inactive region is defined by spacer formation rather than the selective oxidation process as in the prior art. Moreover, the stress generated during ion implantation of the channel stop layer formation by the diffusion process. It also eliminates the problem.

The series of processes described now is according to the present invention, but the semiconductor wafer having the resulting device isolation region of the new structure is also provided by the present invention.

Hereinafter, another application example according to the principles of the present invention will be described with reference to FIG.

Highly integrated semiconductor integrated circuits employ a trench isolation method on the one hand for electrical isolation between devices formed on the same substrate.

The trench is sometimes used to form a capacitor in a semiconductor memory device such as a DRAM. However, in any case, a trench is formed by forming a hole in the substrate and inserting a suitable filler in the hole as shown in FIG.

In the example shown in FIG. 3, reference numeral 21 denotes a semiconductor substrate, 23 an oxide film, 25 a nitride film, 27 a spacer, 29 a polysilicon filled in a trench, and 31 an impurity layer formed on the inner circumferential surface of the trench.

The trench formation forms holes in the substrate by a dry etching method after the nitride film etching and the spacers 27 are formed on the sites for subsequent deposition of the oxide film and the nitride films 23 and 25 and the formation of holes.

In the formed trench, the impurity layer 31 is generally formed by implanting ions into the inner circumferential surface thereof. However, in the present invention, during the polysilicon deposition, the impurity such as boron is simultaneously contained to fill the DPS 29, followed by a heat treatment process. This allows impurities in the DPS layer to diffuse into the semiconductor substrate.

Therefore, since the impurity layer 31 is formed only by heat treatment without a process such as the adjustment of the ion implantation angle, the process is easy and the process is simplified.

The structure of the device isolation region according to the invention is particularly suitable for forming microdevices.

Any method of manufacturing a semiconductor device or a device therewith, which can be applied to a semiconductor device having device isolation, and furthermore, an impurity layer formation according to a diffusion method by a DPS layer is applied is also included in the present invention.

Claims (6)

An element isolation method of a semiconductor device, comprising: forming an insulating layer on a semiconductor substrate to form an opening for defining an element isolation region; Forming a first spacer in the opening and exposing the substrate to a region defined by the first spacer in the opening; Forming a polysilicon layer (DPS layer) containing impurities of the same conductive layer as the substrate on a region defined by the spacer in the opening; Performing a thermal process to diffuse impurities in the DPS layer formed in the openings into the substrate to form a channel blocking layer; Removing the insulating layer and depositing an oxide layer to form spacers S spaced apart from each other with a DPS layer forming a second spacer in contact with the first spacer; Forming a device isolation region by growing a thermal oxide film over the entire surface of the substrate, including the DPS layer exposed when the spacer (S) is formed. The method of claim 1, wherein the oxide layer for forming the second spacer is deposited by low pressure chemical vapor deposition. The semiconductor device of claim 1, wherein the channel blocking layer formed by diffusion is formed to be spaced apart from the active region by at least the width of the spacer S, thereby preventing impurities of the channel blocking layer from penetrating into the active region. Separation method. In a device on a peninsula having an element isolation region, the element isolation region is formed in a horizontal direction on a substrate with a spacer or insulating layer S having an approximately semicircular cross section interposed therebetween with an impurity-containing polysilicon (DPS) layer 19. And a device isolation region including a pair of insulating layers (S) spaced apart from each other, a thermal oxidation layer formed thereon, and a channel stop layer (21) formed under the DPS layer. 5. The semiconductor device according to claim 4, wherein the channel blocking layer (21) is formed spaced apart from the active region by at least the width of the insulating layer (S). In the device isolation method of a semiconductor device having a trench structure, the impurity layer formed on the inner circumferential surface of the trench is formed by forming a trench hole, depositing a polysilicon layer (DPS) containing impurities in the trench, and performing a thermal process. Wherein the impurity of the deposited DPS layer is diffused to the substrate to form an impurity layer.