KR0144026B1 - Forming method of element isolation - Google Patents
Forming method of element isolationInfo
- Publication number
- KR0144026B1 KR0144026B1 KR1019950003785A KR19950003785A KR0144026B1 KR 0144026 B1 KR0144026 B1 KR 0144026B1 KR 1019950003785 A KR1019950003785 A KR 1019950003785A KR 19950003785 A KR19950003785 A KR 19950003785A KR 0144026 B1 KR0144026 B1 KR 0144026B1
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- Prior art keywords
- insulating film
- film
- forming
- insulating
- exposed
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000002955 isolation Methods 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims description 31
- 239000004065 semiconductor Substances 0.000 claims description 23
- 125000006850 spacer group Chemical group 0.000 claims description 18
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 17
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- 238000005498 polishing Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 abstract description 9
- 238000007254 oxidation reaction Methods 0.000 abstract description 9
- 230000010354 integration Effects 0.000 abstract description 3
- 238000005137 deposition process Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
본 발명은 열산화 공정이 아닌 증착공정으로 형성된 절연막으로 소자분리용 절연막을 형성하는 것으로, 버즈비크의 발생을 원천적으로 방지함으로써 소자의 활성영역을 증대시키고 소자의 고집적화를 이루는 효과를 가져온다.The present invention forms an insulating film for device isolation using an insulating film formed by a deposition process rather than a thermal oxidation process, and thereby prevents the occurrence of Buzzbee, thereby increasing the active area of the device and achieving high integration of the device.
Description
제 1 도는 종래기술에 따라 소자분리막이 형성된 상태의 단면도,1 is a cross-sectional view of a device isolation film formed in accordance with the prior art,
제 2a 도 내지 제 2e 도는 본 발명의 일실시예에 따른 소자분리막 형성 공정도,2a to 2e is a device isolation film forming process according to an embodiment of the present invention,
제 3a 도 내지 제 3e 도는 본 발명의 다른 실시예에 따른 소자분리막 형성 공정도.3A through 3E illustrate a process of forming a device isolation film according to another exemplary embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21,31 : 실리콘 기판 22,32,25,35 : 패드산화막21,31 silicon substrate 22,32,25,35 pad oxide film
24,34,27,37 : TEOS 산화막 23,33,26,36 : 질화막24,34,27,37: TEOS oxide film 23,33,26,36 nitride film
24', 34' : TEOS 산화막 스페이서 38 : 감광막24 ', 34': TEOS oxide film spacer 38: photosensitive film
39 : 에피택셜막39 epitaxial film
본 발명은 반도체 제조 공정중 소자 및 셀 간의 절연을 목적으로 하는 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of forming a device isolation film for the purpose of insulating between devices and cells during a semiconductor manufacturing process.
일반적으로, 소자분리막은 국부산화 공정인 LOCOS(local oxidation of silicon) 공정에 의해 형성되고 있으나, 반도체 소자의 고집적화로 인하여 LOCOS 공정이 가지고 있는 버즈비크와 같은 문제점이 소자의 특성을 크게 좌우하게 된다.In general, the device isolation layer is formed by a local oxidation of silicon (LOCOS) process, which is a local oxidation process, but due to the high integration of semiconductor devices, problems such as Buzzbeek, which the LOCOS process has, largely influence the characteristics of the device.
제 1 도는 종래기술에 따라 소자분리막이 형성된 상태의 단면도로서, LOCOS공정의 변형인 PBL(polysilicon bufferred LOCOS) 공정에 의해 형성된 소자분리막을 나타내는데, 그 방법을 살펴보면 다음과 같다.FIG. 1 is a cross-sectional view of a device isolation film formed according to the prior art, and shows a device isolation film formed by a polysilicon bufferred LOCOS (PBL) process, which is a variation of the LOCOS process.
먼저, 반도체 기판(11)상에 열적공정에 의한 패드산화막(12)을 형성하고, 패드산화막(12) 상부에 하학기상증착법으로 폴리실리콘막(13) 및 질화막(14)을 차례로 형성한 상태에서, 마스크 및 식각공정으로 소자분리영역의 질화막(14)과 폴리실리콘막(13)을 제거한 다음에, 열산화 공정으로 소자분리용 필드산화막(15)을 형성한다.First, in a state in which a pad oxide film 12 is formed on the semiconductor substrate 11 by a thermal process, and the polysilicon film 13 and the nitride film 14 are sequentially formed on the pad oxide film 12 by a gas phase vapor deposition method. After removal of the nitride film 14 and the polysilicon film 13 in the device isolation region by a mask and an etching process, a field oxide film 15 for device isolation is formed by a thermal oxidation process.
그러나, 필드산화를 위한 열산화공정시 질화막(14)의 하부에도 산화가 일어나 필드산화막의 가장자리에 버즈비크(bird's beed)가 발생되면서, 소자의 활성영역을 감소시키는 문제점이 발생하게 되어, 고집적 소자의 특성을 저해하는 중요한 요소가 된다.However, during the thermal oxidation process for field oxidation, oxidation occurs in the lower portion of the nitride film 14, so that bird's beed is generated at the edge of the field oxide film, thereby reducing the active area of the device. It is an important factor that impedes the characteristics of.
따라서, 본 발명은 버즈비크의 발생을 원천적으로 방지하는 고집적 반도체 소자의 소자분리막 형성 방법을 제공함을 그 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a device isolation film of a highly integrated semiconductor device that prevents the occurrence of the Burj beak.
상기 목적을 달성하기 위하여 본 밭명은 반도체 기판상에 예정된 소자분리영역이 오픈된 제1절연막을 형성하는 단계 : 상기 오픈 부위의 제1절연막 측벽에 제2절연막 스페이서를 형성하는 단계 : 전체구조 상부에 제3절연막을 형성하는 단계 ; 상기 제2절연막 스페이서가 노출될 때까지 기판 상부를 화학적 기계적 폴리싱하는 단계 : 상기 노출된 제2절연막 스페이서를 제거하는 단계, 노출된 반도체 기판을 비등방성 식각하는 단계 : 전체구조 상부에 제4절연막을 형성하는 단계, 및 반도체 기판 표면이 노출될 때까지 기판 상부를 화학적 기계적 폴리싱하는 단계를 포함하여 제4절연막으로 이루어진 소자분리막을 형성하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of forming a first insulating film having a predetermined device isolation region open on a semiconductor substrate, and forming a second insulating film spacer on the sidewall of the first insulating film. Forming a third insulating film; Chemical mechanical polishing an upper portion of the substrate until the second insulating layer spacers are exposed; removing the exposed second insulating layer spacers; and anisotropically etching the exposed semiconductor substrate: forming a fourth insulating layer over the entire structure And forming a device isolation film made of a fourth insulating film, including forming and chemically polishing the upper portion of the substrate until the surface of the semiconductor substrate is exposed.
또한, 본 발명은 반도체 기판상에 예정된 소자분리영역이 오픈된 제1절연막을 형성하는 단계 : 상기 오픈 부위의 제1절연막 측벽에 제2절연막 스페이서를 형성하는 단계 : 전체구조 상부에 제3절연막을 형성하는 단계 : 상기 제2절연막 스페이서가 노출될 때까지 기판 상부를 화학적 기계적 폴리싱하는 단계 ; 상기 노출된 제2절연막 스페이서를 제거하는 단계 : 노출된 반도체 기판을 비등방성 식각하는 단계 : 전체구조 상부에 제4절연막을 형성하는 단계, 상기 예정된 소자분리영역 이외의 상기 제4절연막 및 제1절연막을 제거하여 활성영역의 반도체 기판을 노출시키는 단계 : 및 노출된 활성영역 부위의 반도체 기판 상에 에피택셜막을 형성하는 단계를 포함하여 상기 제4절연막 및 제4절연막으로 둘러싸인 제3절연막으로 이루어지는 소자분리막을 형성하는 것을 특징으로 한다.The present invention also provides a method for forming a semiconductor device, the method including: forming a first insulating film having a predetermined device isolation region open on a semiconductor substrate; forming a second insulating film spacer on a sidewall of the first insulating film; Forming: chemically mechanical polishing an upper portion of the substrate until the second insulating spacer is exposed; Removing the exposed second insulating layer spacers: anisotropically etching the exposed semiconductor substrate: forming a fourth insulating layer over the entire structure, the fourth insulating layer and the first insulating layer other than the predetermined device isolation region Exposing the semiconductor substrate of the active region by removing the semiconductor layer; and forming an epitaxial layer on the exposed semiconductor substrate of the active region, wherein the device isolation layer includes the fourth insulating layer and a third insulating layer surrounded by the fourth insulating layer. It characterized in that to form.
이하, 첨부된 도면 제 2a 도 내지 제 3e 도를 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings 2A to 3E.
제 2a 도 내지 제 2e 도는 본 발명의 일실시예에 따른 소자분리막 형성 공정도로서, 먼저, 제 2a 도에 도시된 바와같이 실리콘 기판(21)상에 100∼300Å의 패드산화막(22), 1000∼1300Å의 질화막(23)을 적층하고, 마스크 및 식각공정으로 질화막(23)과 패드산화막(32)을 제거하여 소자분리영역의 실리콘 기판(21)을 노출시킨 다음에, 전체구조 상부에 1000∼1300Å의 TEOS 산화막(24)을 형성한다.2A through 2E are diagrams illustrating a process of forming a device isolation film according to an embodiment of the present invention. First, as shown in FIG. 2A, a pad oxide film 22 and a film from 100 to 300 Å are formed on a silicon substrate 21. A nitride film 23 of 1300 GPa is laminated, and the nitride film 23 and the pad oxide film 32 are removed by a mask and etching process to expose the silicon substrate 21 in the device isolation region, and then 1000 to 1300 GPa on the entire structure. TEOS oxide film 24 is formed.
이어서, 제 2b 도와 같이 비등방성 전면식각으로 상기 TEOS 산화막(24)을 식각하여 식각부위 질화막(23) 측벽에 TEOS 산화막 스페이서(24')를 형성한 후, 열산화공정으로 노출된 실리콘 기판(21) 상부에 100∼300Å의 패드산화막(25)을 형성하고 전체구조 상부에 1000∼1300Å의 질화막(26)을 형성한다.Subsequently, as illustrated in FIG. 2B, the TEOS oxide layer 24 is etched by anisotropic front etching to form the TEOS oxide spacer 24 ′ on the sidewall of the etch nitride layer 23, and then the silicon substrate 21 exposed by the thermal oxidation process. ) 100-300 kPa pad oxide film 25 is formed on the upper part, and 1000-1300 kV nitride film 26 is formed on the entire structure.
계속해서, 제 2c 도에 도시된 바와같이 상기 TEOS 산화막 스페이서 (24')가 노출될 때까지 화학적 기계적 폴리싱으로 반도체 기판 전체구조 상부를 식각한 후, HF로 TEOS 산화막 스페이서(24')을 제거한 다음, 상기 TEOS 산화막 스페이서(24') 제거로 인해 노출된 실리콘 기판(21)을 비등성 식각하여 트렌치를 형성한다. 이때, TEOS 산화막 스페이서(24')를 습식으로 제거하기 때문에 질화막(23,26) 하부의 패드산화막(22,25)도 다소 식각되어 언더컷 부위가 발생한다.Subsequently, as shown in FIG. 2C, the semiconductor substrate overall structure is etched by chemical mechanical polishing until the TEOS oxide spacer 24 'is exposed, and then the TEOS oxide spacer 24' is removed with HF. In addition, the silicon substrate 21 exposed by the TEOS oxide spacer 24 'is removed by anisotropic etching to form a trench. At this time, since the TEOS oxide spacer 24 'is removed by wet, the pad oxide layers 22 and 25 under the nitride layers 23 and 26 are also etched to generate undercut portions.
그리고, 10∼50kev, 1 × 1012~ 1 × 1018원자/ ㎠의 조건에서 BF2이온을 이온주입하는 채널스탑 이온주입공정을 실시한다. 공정에 따라 채널스탑 이온주입공정은 생략될 수 있다.Then, a channel stop ion implantation step of ion implantation of BF 2 ions under conditions of 10 to 50 kev and 1 x 10 12 to 1 x 10 18 atoms / cm 2 is performed. Depending on the process, the channel stop ion implantation process may be omitted.
계속해서, 제 2d 도와 같이 전체구조 상부에 1500∼2000Å의 TEOS 산화막(27)을 형성한다.Subsequently, a TEOS oxide film 27 of 1500 to 2000 microseconds is formed on the entire structure as shown in the second diagram.
끝으로, 제 2e 도와 같이 화학적 기계적 폴리싱으로 실리콘 기판 표면이 노출될 때까지 기판 상부를 식각하여 버즈비크 및 미세한 크기로 형성된 소자분리막용 TEOS 산화막(27)을 형성한다.Finally, the upper part of the substrate is etched until the surface of the silicon substrate is exposed by chemical mechanical polishing as shown in FIG. 2e to form the TEOS oxide layer 27 for the device isolation layer formed of Buzzbee and fine size.
제 3a 도 내지 제 3e 도는 본 발명의 다른 실시예에 따른 소자분리막 형성 공정도로서, 제 3a 도 내지 제 제 3c 도는 앞서 설명한 제 2a 도 내지 제 2c 도와 동일함으로 그 설명을 생략한다.3A through 3E are diagrams illustrating a process of forming an isolation layer according to another exemplary embodiment of the present invention, and FIGS. 3A through 3C are the same as those of FIGS. 2A through 2C described above, and thus description thereof is omitted.
제 3d 도는 제 3c 도와 같은 전체구조 상부에 1500∼2000Å의 TEOS 산화막(27)을 형성한 다음, 소자분리막이 형성될 부위에 마스크 물질인 감광막 패턴(28)을 형성하는데, 이때 형성되는 감광막 패턴(28)은 제 3a 도에서 소자분리영역을 노출시키기 위해 사용한 감광막 패턴(마스크)과는 정반대의 패턴이다.In FIG. 3d or 3c, a TEOS oxide film 27 of 1500 to 2000 kV is formed on the entire structure, and then a photosensitive film pattern 28, which is a mask material, is formed on a portion where the device isolation film is to be formed. 28 is a pattern opposite to that of the photoresist pattern (mask) used to expose the device isolation region in FIG. 3A.
계속해서 , 제 3e 도와 같이 상기 감광막 패턴(28)을 식각장벽으로 하여 상기 TEOS 산화막(27)을 습식식각하고, 감광막 패턴(28)을 제거한 다음, 노출된 질화막(23) 및 패드산화막(22)을 차례로 제거한 상태에서 노출된 활성영역 부위의 실리콘 기판(21) 상부에 단결정 에피택셜 실리콘막(29)을 형성한다.Subsequently, the TEOS oxide layer 27 is wet-etched by removing the photoresist layer pattern 28 by removing the photoresist layer pattern 28 by using the photoresist pattern 28 as an etch barrier as shown in FIG. 3E. The single crystal epitaxial silicon film 29 is formed on the exposed silicon substrate 21 in the state of sequentially removing.
상기 제 3e 도에서 TEOS 산화막(27)과 TEOS 산화막(27)으로 둘러싸인 질화막(26) 및 패드 산화막(25)은 소자분리막 역할을 한다.In FIG. 3E, the nitride layer 26 and the pad oxide layer 25 surrounded by the TEOS oxide layer 27 and the TEOS oxide layer 27 serve as device isolation layers.
이상, 상기 설명과 같이 이루어지는 본 발명은 열산화 공정이 아닌 증착공정으로 형성된 절연막으로 소자분리용 절연막을 형성하는 것으로, 버즈비크의 발생을 원천적으로 방지함으로써 소자의 활성영역을 증대시키고 소자의 고집적화를 이루는 효과를 가겨온다.As described above, the present invention, as described above, forms an insulating film for isolation of a device by using an insulating film formed by a deposition process rather than a thermal oxidation process, thereby increasing the active area of the device and preventing the integration of devices by inherently preventing the occurrence of Buzzbeek. It brings about the effect.
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| KR1019950003785A KR0144026B1 (en) | 1995-02-25 | 1995-02-25 | Forming method of element isolation |
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