JP2726851B2 - Manufacturing method of one-dimensional quantum wires - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method of manufacturing a one-dimensional quantum wire used for an ultra-high-speed one-dimensional electron transistor or a non-linear element having high conversion efficiency utilizing quantum interference. It is about. In the following description, () indicates a crystal plane, and [] indicates a crystal axis. (Prior Art) FIG. 5 shows a structure of a conventionally proposed one-dimensional quantum wire using AlGaAs / GaAs as an example. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a non-doped AlGaAs growth layer, 3 is a non-doped GaAs growth layer, 4 is non-doped AlGaAs.
The spacer layers 5 and 5 are Si-doped AlGaAs growth layers. This is Al
A one-dimensional electronic state is realized by modulation doping on the side surface of a GaAs / GaAs superlattice. The portion of the superlattice / AlGaAs interface surrounded by the dotted line in the figure becomes a one-dimensional electronic state. Next, a method for manufacturing this structure will be described with reference to FIG.
First, non-doped AlGaAs2 and GaAs3 are sequentially grown on the substrate 1 by a molecular beam epitaxy method or a metal organic chemical vapor deposition method to produce a superlattice. The best non-doped Al
The GaAs layer is formed thick. Next, an etching mask 6 is arranged on the superlattice wafer in the [10] direction (FIG. 6A), and a step is formed by chemical etching or plasma etching (FIG. 6B). After removing the etching mask 6, grown etched side non-doped AlGaAs4 a thickness of 10nm again molecular beam epitaxy or metal organic chemical vapor deposition method, subsequently Si-doped (to 10 ¹⁸ cm
^-3 ) By growing AlGaAs5 to a thickness of 100 nm, a one-dimensional electronic state is realized on the side surface of GaAs3 which becomes a potential valley (FIG. 6 (c)). (Problems to be solved by the invention) However, the above-described method for producing a quantum wire has the following problems. The side surface (shaded portion in FIG. 5) formed by the chemical etching is contaminated with carbon, oxygen, silicon, and the like, and these contaminants have a problem that they become scattering factors of electrons and recombination centers. Further, in chemical etching, since the etching rate varies depending on the type of substance, the side surface of the etching becomes uneven, which again becomes a factor of scattering of electrons. On the other hand, when processing is performed by plasma etching, a damaged layer or a deteriorated layer is formed on the processed surface (the hatched portion in FIG. 5). These layers also act as electron scattering factors and recombination centers, causing a problem that the performance of a device using this quantum wire is remarkably deteriorated. Since the quantum wire having the structure shown in FIG. 5 uses the interface on the side surface, contamination or processing damage of the interface becomes a fatal defect. (Object of the Invention) The present invention has been proposed in order to improve the above-mentioned drawbacks. The object of the present invention is to form a quantum wire by a growth step only without a processing step such as etching. It is another object of the present invention to provide a method for producing a high-quality one-dimensional quantum wire, which is completely free from processing damage and contamination and can control the steepness of the interface in the lateral direction on the order of a single atom. (Means for Solving the Problems) In order to achieve the above object, the present invention provides a step of forming a stripe having a step in the [10] direction on a surface of a (001) compound semiconductor substrate; By metalorganic vapor phase epitaxy, two or more types of low-impurity-concentration semiconductor layers whose width in the horizontal direction is wider than that at which the quantum wire effect occurs are alternately stacked to grow a superlattice stripe in a trapezoidal shape. Forming a thickness of at least one type of growth layer of the same type of growth layer to a thickness of about 100 nanometers or less; and forming a low impurity concentration on at least the upper surface of the trapezoidal stacked layer. Growing the other semiconductor to a thickness of about 50 nanometers or less, or continuously embedding the trapezoidal superlattice with a high impurity concentration semiconductor without growing the semiconductor. That is a method for manufacturing a one-dimensional quantum wire which the gist of the invention. Thus, the present invention grows a trapezoidal superlattice on a substrate that has been processed into a predetermined shape in advance using a metalorganic vapor phase epitaxy method. The main feature is to form a semiconductor of a concentration, realize a one-dimensional electronic state by modulation doping, and produce a quantum wire. Next, examples of the present invention will be described. It should be noted that the embodiments are merely examples, and it is needless to say that various changes or improvements can be made without departing from the spirit of the present invention. (Example) Hereinafter, an example of the present invention will be described in detail using AlGaAs / GaAs as an example. FIG. 1 shows a basic structure of a quantum wire produced by the method of the present invention. The quantum wire exists at a portion of an interface surrounded by a dotted line. In the figure, 1 is a semi-insulating GaAs substrate, 2 is non-doped
An AlGaAs growth layer, 3 is a non-doped GaAs growth layer, 4 is a non-doped AlGaAs spacer layer, and 5 is a Si-doped AlGaAs growth layer. FIG. 2 shows a procedure for fabricating the structure of FIG. 1, which will be sequentially described below. First, an etching mask 6 on a stripe long in the [001] direction is arranged on the (001) plane of the GaAs substrate 1 (FIG. 2 (a)), and is subjected to chemical etching or plasma etching as shown in FIG. 2 (b). On the board
10] Make stripes with steps in the direction. At this time, the shape of the side wall of the step may be any shape. Non-doped AlGaAs2 and GaAs are deposited on this substrate using metal organic chemical vapor deposition.
s3 is sequentially grown to a thickness of 10 nm. At this time, since no growth occurs on the trapezoidal side walls, a trapezoidal superlattice can be produced (FIG. 2 (c)). The growth conditions at this time will be described later in detail. Next, non-doped AlGaAs4 is grown on the trapezoidal superlattice by 50 nm or more, for example, 100 nm (FIG. 2 (d)), and then Si-doped (.about.10 @ ¹⁸ cm @ ^-3 ) AlGaAs5 is grown. The growth of the top surface of the step eventually becomes triangular (FIG. 2 (e)), and then grows in the lateral direction, so that the trapezoidal superlattice is covered with Si-doped AlGaAs5 (FIG. 2 (f)). ). The growth on the upper surface of the step does not grow at all on the side wall until the shape becomes triangular, but after the triangular shape, growth occurs in the lateral direction from the side wall, so that the structure shown in FIG. it can. Due to the non-doped AlGaAs layer 1, the trapezoidal upper surface is not modulation-doped. On the other hand, since the side of the trapezoidal lattice is in contact with Si-doped AlGaAs5, GaAs3 and AlGa
A one-dimensional electronic state can be realized by modulation doping at the interface of As5. Note that a thin non-doped AlGaAs layer may be interposed between the trapezoidal lattice side surface and the Si-doped AlGaAs5. Next, the crystal growth conditions of this embodiment will be described. Growth is carried out under normal pressure using a horizontal furnace with high frequency heating. Using trimethylgallium, trimethylaluminum, and arsine as raw materials, they are grown on the substrate 1 shown in FIG. 2 (b). Assuming that the angle between the side wall of the growth layer on the step upper surface and the step upper surface is θ (see the inset in FIG. 3A), FIG. 3 shows the relationship between θ and the growth conditions. As can be seen from the figure, θ shows exactly 55 ° at all growth temperatures (FIG. 3 (a)), arsine partial pressure (FIG. 3 (b)), and trimethylgallium partial pressure (FIG. 3 (c)). . This indicates that the trapezoidal side surface is a (111) B surface, that this surface is an atomically flat surface, and that no growth occurs on the trapezoidal side surface, that is, the (111) B surface. . Where A
The plane is a Ga plane, and the B plane is an As plane. In order to confirm this, the dependence of the growth rate on the plane orientation was examined.
The result is shown in FIG. It is clear from the figure that no growth occurs on the (111) B plane. Therefore, the trapezoidal superlattices shown in FIGS. 2C and 2D can be easily produced by metal organic chemical vapor deposition. As described above, according to the manufacturing method of this embodiment,
Since it can be manufactured only by the growth step without any processing step, there is no etching contamination or processing damage, and the side face is a flat quantum wire on the order of a single atom. In the present embodiment, the description has been given of the AlGaAs / GaAs material.
III-V group semiconductors such as nP / GaAs and GaInAs / InP and mixed crystal systems thereof, and II-VI group semiconductors such as ZnSe / GaAs and mixed crystal materials thereof can also be realized. (Effects of the Invention) According to the manufacturing method of the present invention, a quantum wire is formed only by a growth process, so that it is completely free from processing damage and contamination, and the steepness of a horizontal interface is also simple. It is possible to obtain high-quality one-dimensional quantum wires that can be controlled in atomic order.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows the basic structure of a quantum wire produced by the method of the present invention, FIG. 2 shows the manufacturing procedure of the present invention, FIG. 3 shows the relationship between the growth side wall angle and the growth conditions, and FIG. The figure shows the relationship between the growth rate and the plane orientation of the substrate, FIG. 5 is a cross-sectional view of a conventionally proposed quantum wire structure, and FIG. 6 is a view for explaining a conventionally proposed manufacturing method. 1 Semi-insulating GaAs substrate 2 Non-doped AlGaAs growth layer 3 Non-doped GaAs growth layer 4 Non-doped AlGaAs spacer layer 5 Si-doped AlGaAs growth layer 6 Etching mask

Claims (1)

(57) [Claims] Forming a stripe having a step in the [10] direction on the surface of the (001) compound semiconductor substrate, and forming the stripe in the horizontal direction on the semiconductor substrate by a metal organic chemical vapor deposition method so that the width in the horizontal direction is smaller than the width at which the quantum wire effect occurs. A superlattice stripe is grown in a trapezoidal shape by alternately laminating two or more types of semiconductor layers having a low impurity concentration, and the thickness of at least one type of growth layer among the same type of growth layer is reduced. Forming the semiconductor to a thickness of about 100 nanometers or less, and then growing or growing another semiconductor with a low impurity concentration to a thickness of about 50 nanometers or less on at least the upper surface of the trapezoidal stacked layer. And continuously embedding the trapezoidal superlattice with a semiconductor having a high impurity concentration.