JP2846576B2 - Method for producing III-V compound semiconductor epitaxial layer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a method for producing a group III-V compound semiconductor epitaxial layer having a stripe-shaped fine surface structure. The III-V compound semiconductor epitaxial layer is used for manufacturing various semiconductor devices using quantum wires made of a III-V compound semiconductor.

[0002]

2. Description of the Related Art Heretofore, in order to form a structure such as a quantum wire (quantum well wire) or a quantum dot (quantum well box) by processing a group III-V compound semiconductor, it is necessary to process the compound semiconductor in the stacking direction. Epitaxial growth techniques such as linear epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD) are used, while planar processing involves lithography techniques such as interference exposure and electron beam lithography and dry etching such as reactive ion etching. Etching techniques have been used. These techniques are excellent in that the size of the structure to be formed can be freely designed within a range of dimensions that can be processed, but have several disadvantages described below.

In other words, the minimum processing shape in the planar direction is limited by the performance of the lithography technique, and the combination of the lithography processing step and the epitaxial growth step requires a complicated process, resulting in poor manufacturing efficiency. It is known that contamination or damage of a substrate due to lithography or etching seriously affects physical properties of a semiconductor interface, which seriously affects the performance of quantum wires and quantum dots.

An example of a method combining the lithography process and the epitaxial growth process will be described with reference to FIG. A stripe-shaped resist pattern (2) is formed by lithography on a semiconductor substrate (1) or an epitaxial substrate on which an epitaxial layer has been previously formed (FIG. 8A), and etching is performed using this as a mask. This stripe pattern is transferred onto the semiconductor substrate as stripe-shaped irregularities (3) (FIG. 8).
(B)). By performing epitaxial growth of semiconductor layers having different properties on the semiconductor substrate (1) having the striped concavo-convex structure, a buried quantum wire (4) as shown in FIG. 8C is formed. However, in this case, since the interface of the semiconductor substrate (1) is a semiconductor surface originally formed by lithography and etching,
It is a serious problem that this interface has contaminants and damage introduced by being exposed to the air during or after the lithography process or the etching process.

In order to avoid contamination, a method of connecting a semiconductor crystal growing apparatus, a drawing apparatus and a dry etching apparatus with an ultra-high vacuum wafer transfer apparatus and performing all processes in an ultra-high vacuum consistently has been attempted. ing. However, even in an ultra-high vacuum, it is impossible to remove all the surface contamination, and in this case, the damage introduced in the dry etching process becomes a serious problem.
In any case, the process is complicated, special processing equipment is required, and productivity is low.

In order to overcome this, the plane orientation of the surface is changed to (1).
[0099] Several attempts have been made in the known literature regarding a technique for forming a quantum structure such as a quantum wire on almost the entire surface of an epitaxial layer using only an epitaxial growth technique by performing crystal growth using a substrate that is slightly inclined. Has been reported to. For example, overseas, PMPetroff et al., Journal of Crystal Growth, Vol. 95 (1989)
260-265 pages, and in Japan, T.Fukui and H.Saito
Author, Journal of Crystal Growth, Volume 115 (1991
Year) 61-63 pages. Since these methods use the atomic steps formed on the crystal surface by using a tilted substrate, it is possible to simultaneously form an ultrafine structure characterized by the size of the atoms on the entire surface of the substrate crystal. It is possible in principle.

The principle of this method will be described with reference to FIGS. (1) in FIG. 9 represents a substrate crystal. The group III-V compound semiconductor substrate (1) having a surface plane orientation of (100) has a structure in which a group III element and a group V element are periodically repeated in a layered manner, so that the surface plane orientation is (100). On the surface of a substrate that is slightly tilted from the direction (tilted substrate), there are surface atomic layer steps with a density that depends on the tilt angle on average.

For example, a cross section of a substrate inclined in the <10> direction by two degrees from the (001) surface in the <110> direction has a surface (5) of the substrate (1) shown in FIG. There is an atomic layer step (6). Generally, there is a limit in the surface processing accuracy of the growth substrate obtained by processes such as cutting, polishing, and etching, so that the atomic layer steps (6) on the surface (5) of the growth substrate have roughness. In other words, the size of the step interval (step width) is not uniform. On the other hand, when the semiconductor layer (7) is crystal-grown on the substrate (1) under a certain condition, the surface (8) of the grown semiconductor layer has a uniform step width and a molecular layer step having a height of half the lattice constant. (9) is formed in a stripe shape (JP-A-5-326922). For example, when a GaAs substrate having a tilt angle of 2 degrees is used, the terrace width, which is the interval of step (9), is 8 nm. After growing a semiconductor thin line portion (10) having a property different from that of the semiconductor layer (7) on the surface under the condition of adhering to the step portion, the semiconductor confinement layer (7 ') is grown. If a semiconductor having a smaller band gap than the semiconductors of the semiconductor layers (7) and (7 ') is selected as the semiconductor wire (10), the semiconductor wire (10) becomes a so-called quantum wire.

This method is characterized in that a quantum wire structure is formed by utilizing an atomic layer step inherently present in a tilted substrate and performing crystal growth conditions under step edge growth conditions. Therefore, the size of a structure that can be formed (that is, a step width, a step height, and the like) is limited, and is effective for a structure characterized by an atomic level size. It is not a technology that enables control over a wide range.

[0010]

FIG. 10 is a schematic diagram of an energy band for electrons confined in a quantum wire. It can be said that the quantum wire has a structure in which a potential well as shown in FIG. 10 has a so-called one-dimensional potential well which is continuous in the direction of the wire. Therefore, the properties of this potential well determine the properties of the quantum wire. The basic properties of a potential well are determined by the depth of the potential well (11), which depends on the combination of semiconductor materials, and the width (12) of the potential well, which depends on the size of the structure.

Since there is a limit in the degree of freedom of combinations of semiconductor materials that can be generally used, a technique for freely manufacturing the size of a semiconductor structure forming a potential well is indispensable for controlling the characteristics of the potential well. Also,
Such a potential well is formed by an interface structure between semiconductors having different properties (semiconductor heterointerface), and the potential shape at the interface corresponds to (13) and (13 ') in FIG. If there is a localized level (14) at the interface due to a defect due to contamination or damage, electrons in the well are affected by the level, and it is necessary to remove this. The above-mentioned problems, namely, that the characteristics are controlled by the size of the structure and that it is necessary to remove the localized level at the interface, are the two points that almost all semiconductor devices having a fine structure as well as quantum wires. This is a common matter.

However, of the conventional techniques, the use of a combination of the lithography technique and the epitaxial growth technique allows the size of the semiconductor structure to be freely designed within a certain range. However, it is impossible to remove contamination and damage at the interface. It was possible. Further, in the technology using the inclined substrate, problems of interface contamination and damage do not occur, but it is impossible to freely design the size of the semiconductor structure.

[0013]

SUMMARY OF THE INVENTION The present invention provides a technique for forming a semiconductor fine structure such as a quantum wire, which does not cause the problem of interface contamination or damage and controls the size of the structure. According to the present invention, as shown in FIG. 1, an arbitrary height (h) of 5 nm or more, which is used for forming a microstructure semiconductor device such as a quantum wire, and a base (w) is
A structure having a stripe-shaped fine surface in which a number of ridges having a triangular cross section of 300 nm or more are arranged is formed on the entire surface of the epitaxial layer.

That is, the present invention provides a technique for forming a semiconductor fine structure which does not cause contamination and damage to the interface and has controllability of the size of the structure in a wide range, and is 0.5 to 10 degrees from the (001) plane. On a semiconductor substrate having an inclined plane orientation,
III- with a carbon concentration of 1 × 10 ¹⁹ cm ^-3 or more and a thickness of 100 nm or more
A first step of growing a group V compound semiconductor epitaxial layer, and a second step of heat-treating the substrate after the epitaxial layer growth at a temperature of 750 ° C. or more while supplying a group V element to the atmosphere. Further, a plurality of ridges having a triangular cross section with a height of 5 nm or more and a base of 300 nm or more are juxtaposed on the surface of the epitaxial layer by the heat treatment.

[0015]

The present invention is characterized in that in order to achieve the above object, the above-mentioned three components are used at the same time, and a stripe-shaped fine surface structure is obtained only when these three components are used simultaneously. An epitaxial layer is formed. That is, a semiconductor substrate whose plane orientation is inclined from the (001) plane is used as the first element. As a second element, a semiconductor epitaxial layer containing a high concentration (1 × 10 ¹⁹ cm ⁻³ or more) of carbon impurities and preferably having a sufficient thickness is epitaxially grown on the semiconductor substrate (first step). Third
A relatively high-temperature heat treatment is performed while supplying a group V material so that the group V element is not desorbed from the semiconductor epitaxial growth layer grown as the element (2) (second step). In the present invention, the semiconductor substrate is not limited to the substrate itself, and may have a structure in which another epitaxial layer is grown thereon.

By controlling the inclination angle of the semiconductor substrate in the first element and the amount of carbon impurity added in the second element, a triangular section (width w) serving as a unit of the fine surface structure on the surface of the epitaxial layer is controlled. And height h) can be controlled. In addition, the heat treatment step of the third element is necessary for developing a triangular-shaped ridge on the surface of the epitaxial layer as described later. And 2 of the second element and the third element
First, it can be realized by using a conventional MOCVD apparatus or MBE apparatus, and it is possible to continuously perform the crystal growth of the quantum wire portion and the confinement layer following the second step. Therefore, surface contamination and damage are extremely small.

Now, considering the above elements individually, each is a technique that has been used conventionally. That is, the method using the inclined substrate has been used for a long time in the crystal growth technology for the purpose of preventing the surface of the substrate from being roughened, in addition to the method described in the related art. Further, the high-concentration carbon impurity addition technique is used for forming a III-V semiconductor epitaxial layer having a high hole concentration. Also,
Heat treatment after crystal growth is used for the purpose of relaxing internal strain after crystal growth.

However, the present inventors have found that by combining these three techniques, it is possible to newly control the structure of the surface of the epitaxial layer to complete the present invention.

Next, the present invention will be described in more detail with reference to FIG. FIG. 2 (a) shows an epitaxial layer (1) doped with high concentration of carbon using a substrate (15) having no inclination.
After the first step in the case where 6 ′) is formed, FIG. 2B shows the state after the first step in the case where an epitaxial layer (16) also doped with carbon at a high concentration is formed using the inclined substrate (17). Shows respective cross sections. FIG. 2C shows the cross section of the epitaxial layer obtained after the second step when the substrate (15) having no inclination is used, and FIG. 2D shows the cross section of the epitaxial layer obtained after the second step when the inclined substrate (17) is used. Is represented. That is, the cross-sectional structure of the surface portion (18) of the epitaxial layer obtained by the present invention has a shape in which a triangular cross-section is periodically repeated as shown in FIG. On the other hand, when a substrate (15) having no inclination is used as shown in FIG. 2 (c), the surface portion (18 ') of the epitaxial layer has an irregular shape.

In the first step of the present invention, the growth of the epitaxial layer with high concentration of carbon is performed because the covalent bond radius of carbon atoms is smaller than that of general group III-V semiconductor constituent atoms. This leads to intentional introduction of tensile stress. In the epitaxial layers (16) and (16 ') of FIG. 2, the strain is alleviated by a slight extension of bonds between atoms constituting the crystal. Therefore, the internal energy is higher than in the case where there is no distortion.

After that, when the heat treatment in the second step is performed, the surface (18) (18 ') of these epitaxial layers has a greater degree of freedom than the inside of the epitaxial layers, so that the surface structure is changed to include distortion. The energy of the entire system can be reduced. That is, by forming unevenness whose size is determined by the amount of strain introduced in the first step on the surface, a low energy state is realized as a whole.
This phenomenon is based on the magnitude of the intrinsic strain of the grown epitaxial layer, and the surface irregularity structure having the smallest surface energy is uniquely determined thermodynamically.

Therefore, the surface structure of the epitaxial layer including the intrinsic strain formed in the first step is sufficiently activated by the heat treatment performed in the second step after the growth of the layer is stopped, whereby It will change to a structure having the most stable unevenness. In order to obtain sufficient activation by the heat treatment of the second step, the temperature of the heat treatment must be 7
The temperature must be 50 ° C or higher. At a temperature lower than 750 ° C., activation is insufficient, so that the uneven structure of the present invention cannot be sufficiently formed within a desirable time as the heat treatment time of the heat treatment step. On the other hand, the upper limit of the heat treatment temperature is limited by the supply pressure of the group V element supplied during the heat treatment. If the dissociation pressure of the group V element in the epitaxial layer becomes higher than the supply pressure of the group V element at the time of the heat treatment with an increase in the heat treatment temperature, the epitaxial layer will be broken by the desorption of the group V element. GaAs as III-V compound semiconductor
If you select s and perform heat treatment with a normal MOCVD device,
The upper limit is about 900 ° C. The heat treatment time of the second step can be completed in a shorter time as the heat treatment temperature is higher. For example, heat treatment at 800 ° C for 60 minutes and heat treatment at 850 ° C for 30 minutes show almost the same heat treatment effect.

In the case of an epitaxial layer grown on a substrate having no inclination, the irregularities on the surface are generally irregular as shown in FIG. 2C, and in many cases, the surface is irregular due to the formation of surface defects and the like. However, when an inclined substrate is used as a substrate for growing an epitaxial layer, these irregularities appear in FIG.
As shown in (d), a regularity in which the triangular cross section periodically repeats can be generated. This phenomenon has been described by Kasu et al. In Applied Physics Letter, Vol. 62 (1993) 1262-1.
As reported on page 264, this is due to the fact that when the shape of the unevenness is made up of facets of a low index surface having lower energy, a lower energy state is realized.

In general, carbon is one of the elements that can be added at the highest concentration as a dopant to a group III-V semiconductor epitaxial layer, and one of the elements that diffuses the least in the epitaxial layer after being added. It is known that Therefore, in order to realize the stabilization of the epitaxial layer by changing to a stable surface structure state, activation by heat treatment at a high temperature is necessary,
When other elements are added and used, the diffusion of these added elements toward the substrate or partial diffusion occurs before the change to the surface structure state of the present invention, resulting in uneven distribution of internal strain. Therefore, the effect of the present invention is not exhibited.

As the growth semiconductor substrate used in the present invention, a substrate whose plane orientation is inclined by 0.5 to 10 degrees in an arbitrary direction from the (001) plane may be used, and is preferably shown in FIG. <100> direction, <1
A highly symmetric direction such as the 10> or <10> direction is effective. As the range of the inclination angle θ, the lower limit is
At present, from 0.5 degrees that can be manufactured with high accuracy in reality, the upper limit is considered to be about 10 degrees which is a plane equivalent to the facet plane used in the present invention, and furthermore, the range of 1 to 5 degrees is considered. Good. By changing this angle, it is possible to change the in-plane density (period width: w) of the surface structure of the obtained epitaxial layer.

The most preferable impurity atom to be added to the epitaxial layer is carbon having a small diffusion even if it is added at a high concentration. However, by adding the impurity atom, tensile strain is introduced into the growth layer and diffusion is as small as carbon. Available if additives are present. In this sense, it is conceivable to use a mixed crystal semiconductor whose composition is slightly different from the composition lattice-matched to the substrate, but a device for suppressing diffusion is required.

The greater the thickness of the epitaxial layer to be grown, the better the uniformity in the surface of a plurality of ridges having a triangular cross section, which is a stripe-shaped fine surface structure formed on the surface, is good. desirable. If the thickness is too thin, the shape of the surface of the semiconductor substrate may affect the fine stripe structure on the surface of the epitaxial layer, and a uniform structure may not be obtained.

As described above, the operation of the present invention is based on the Kasu
Utilizes the phenomenon of low index plane generation at the interface and surface of the epitaxial layer reported by the authors, but the phenomenon in the present invention is the relaxation process due to the change in the surface structure state of the intrinsic strain contained in the epitaxial layer. Is that
That is what the inventors have found for the first time. That is, in the method from Kasu which controls only the angle of the inclined substrate, the control range of the surface structure was extremely narrow. Utilizing the addition of carbon, which is advantageous for the subsequent thermal process, to introduce the intrinsic strain is an unprecedented new use of the technique of adding carbon to III-V compound semiconductors. The present inventors have studied in depth each of several element technologies in order to realize the control of the fine structure of the semiconductor surface by the epitaxial technology, and have reached the combination of the element technologies shown in the present invention. It is possible to control the size of the surface structure in a wider range than ever before.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment of the present invention, the production of an epitaxial layer having a stripe-shaped fine surface structure by using the MOCVD method will be described with reference to the drawings. As a semiconductor substrate, the surface orientation of the substrate surface is <100> from the (001) plane.
Two GaAs substrates inclined two degrees in the direction were used. The inclined state of these substrates corresponds to θ being 2 degrees in FIG. As a first step, a GaAs epitaxial layer doped with 3 × 10 ¹⁹ cm ⁻³ of carbon (Sample A) and a GaAs epitaxial layer doped with 5 × 10 ¹⁹ cm ⁻³ (Sample B) on each substrate at a substrate temperature of 500 ° C. It grew to a thickness of 1 μm.

The GaAs epitaxial layers include As
Since carbon atoms having a smaller atomic radius are added at a high concentration, the lattice constant of sample A is smaller than that of the substrate GaAs crystal by about 0.03% and that of sample B is smaller by about 0.05%, and tensile strain is included. The magnitude of the strain is desirably 0.3% or less at which dislocation does not occur in this system. Also, 0.01
% Or more, the effect of the present invention, which has not existed before, is remarkably observed.
Therefore, in this case, it is desirable that the carbon impurity addition amount is in the range of 1 × 10 ¹⁹ cm ^{−3 to} 3 × 10 ²⁰ cm ⁻³ . Further, both samples were continuously processed in the same furnace at a temperature of 800 ° C as a second step.
Heat treatment was performed in an arsine gas atmosphere for minutes.

The structure of the surface (18) of the obtained epitaxial layer was as shown in FIG. FIG. 4 shows the periodic width w and the height h representing the size of the striped surface structure for the samples A and B of the examples, with the horizontal axis representing the carbon addition amount. As shown in FIG. 4, a surface structure whose height h reaches 25 nm, which cannot be obtained by the conventional technique, is obtained. Also,
The surface structures of Sample A and Sample B are similar, and from FIG.
It can be seen that this height h can be controlled in a wide range by the amount of impurity added. For example, when carbon impurity of 1 × 10 ²⁰ cm ⁻³ is added, h is expected to reach 50 nm. On the other hand, if the amount of strain is reduced by reducing the concentration of the added impurity, the height of the stripe-shaped surface structure is also reduced. Then, it approaches the monolayer step reported conventionally. In addition, in order to observe the structures of these examples, an atomic force microscope having further excellent resolution was used in addition to the scanning electron microscope.

On the other hand, the relationship between the periodic width w of the surface structure and the structure height h is determined by the angle of the inclined substrate used.
Therefore, various combinations of w and h can be realized by the combination of the amount of added carbon and the substrate inclination angle. For example, GaAs
The amount of carbon added to the epitaxial layer grown under the same conditions as in Example 1 was set to 0 to 1 × 10 3 using a substrate in which the plane orientation of the substrate surface was inclined by 1 to 7 degrees in the <100> direction from the (001) plane.
FIG. 5 shows the relationship between the period w and the height h of the stripe-shaped surface structure obtained when the heat treatment was performed under the same conditions while changing the range in the range of ²⁰ cm ⁻³ . FIG. 6 shows the relationship between w and h when using a substrate in which the plane orientation of the GaAs substrate surface is inclined by 1 to 10 degrees in the <110> or <10> direction from the (001) plane. The shaded region in FIGS. 5 and 6 is expected to be a structure that can be formed by the method of the present invention.

In the above embodiment, a GaAs epitaxial layer doped with high-concentration carbon is grown using a GaAs substrate. However, the combination of this substrate and the epitaxial layer is not limited to this. Various things are possible.

[0034]

[Table 1]

Further, the first step and the second step of the present invention can be continuously performed in a crystal growth apparatus without affecting a normal crystal growth step. Therefore, when the present invention is used, it is possible to form various structures using only the crystal growing apparatus and without having to go out of the crystal growing apparatus to the outside such as in the air.

FIG. 7 shows some of these applications. FIG. 7A shows a layered semiconductor layer (20) before the first step.
This is an example in which is formed. FIG. 7B shows an example in which a semiconductor layer (21) having different properties is formed after the second step so as to keep the shape of the crystal surface structure up to the second step. FIG.
(C) shows an example in which the semiconductor layer (22) is formed so that the crystal surface structure up to the second step is embedded and the crystal surface structure becomes flat. FIG. 7D shows an example in which a semiconductor layer (23) having a different property only at a valley (step end) in the crystal surface structure up to the second step. Further, by combining the embodiments and the application examples described above in various ways, it is possible to form a wide variety of structures. For example, FIG.
Is an example in which an embedded quantum wire structure is formed by combining these.

[0037]

As described above, according to the present invention,
It is possible to provide a semiconductor epitaxial layer having a stripe-shaped fine surface structure having an arbitrary height that can be used for manufacturing a quantum wire. Furthermore, since it is possible to perform consistent production in the same apparatus using an existing semiconductor crystal growth apparatus, the process can be shortened as compared with the conventional one, and furthermore, a semiconductor structure having excellent performance can be obtained because there is very little surface contamination and damage. . Therefore, various structures such as quantum wires having excellent characteristics can be efficiently manufactured. In addition, there is an effect that application to a new device structure using this structure is possible.

[Brief description of the drawings]

FIG. 1 is a perspective explanatory view showing a stripe-shaped surface structure obtained by the present invention.

FIG. 2A is a cross-sectional explanatory view after a first step when a substrate having no inclination is used, FIG. 2B is a cross-sectional explanatory view after the first step when an inclined substrate is used according to the present invention, (C) is an explanatory cross-sectional view after the second step in the case of using a substrate having no inclination,
(D) is a cross-sectional explanatory view after the second step in the case where an inclined substrate is used according to the present invention.

FIG. 3 is an explanatory diagram showing a substrate tilt state of θ degrees from a (001) plane in a <100> direction.

FIG. 4 is a diagram showing an experimental result of a relationship between a period w of a stripe-shaped surface structure obtained according to the present invention and a carbon addition concentration at a height h.

FIG. 5 shows that the plane orientation of the semiconductor substrate surface is from (001) plane to <
FIG. 10 is a diagram showing the relationship between the period w of the stripe-shaped surface structure and the carbon concentration at the height h when a substrate inclined by 1 to 7 degrees in the 100> direction is used.

FIG. 6 shows that the plane orientation of the surface of the semiconductor substrate is changed from (001) plane to <
Period w and height h of the stripe-shaped surface structure when using a substrate inclined by 1 to 10 degrees in the <110> or <10> direction.
FIG. 3 is a diagram showing a relationship between the carbon content and the concentration of carbon.

FIG. 7 shows the structures of various semiconductor epitaxial layers grown by using the present invention, and (a) to (e) are cross-sectional explanatory views.

8A and 8B show a conventional method for producing a quantum wire using lithography and epitaxy, in which FIG. 8A is a perspective explanatory view showing the formation of a resist mask by lithography,
(B) is a perspective explanatory view showing transfer of a resist mask to a semiconductor substrate by etching, and (c) is a perspective explanatory view showing growth of a quantum wire structure on the substrate by epitaxy.

9A and 9B show a method of manufacturing a quantum wire according to a conventional technique, in which FIG. 9A is an explanatory view of a <110> cross section of a substrate inclined by θ degrees in a <10> direction from a (001) plane, and FIG. Cross-sectional explanatory view showing the surface molecular layer step of the semiconductor layer,
(C) is an explanatory sectional view showing the formation of quantum wires by the growth of the confinement layer.

FIG. 10 is an explanatory diagram showing an energy band for electrons confined in a quantum wire.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 resist pattern 3 stripe-shaped unevenness 4 semiconductor thin wire portion 5 substrate surface 6 atomic layer step 7 semiconductor layer 8 semiconductor layer surface 9 molecular layer step 10 semiconductor thin wire portion 11 potential well depth 12 potential well width 13 semiconductor hetero Potential shape at interface 14 Localized level 15 Semiconductor substrate without inclination 16 High-concentration carbon-doped epitaxial layer 17 Inclined substrate 18 Surface portion of epitaxial layer after heat treatment 20-23 Semiconductor layer

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-160098 (JP, A) JP-A-5-175202 (JP, A) JP-A-3-188619 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) H01L 21/205 C30B 25/18 C30B 29/40 502 C30B 33/02

Claims (2)

(57) [Claims] 1. A group III-V compound semiconductor epitaxial layer having a carbon concentration of 1 × 10 ¹⁹ cm ^-3 or more and a thickness of 100 nm or more on a semiconductor substrate having a plane orientation inclined by 0.5 to 10 degrees from the (001) plane. The substrate after the epitaxial layer growth while supplying a group V element to the atmosphere.
And a second step of performing a heat treatment at a temperature of 750 ° C. or higher. 2. The method according to claim 1, wherein a plurality of ridges having a triangular cross section having a height of 5 nm or more and a base of 300 nm or more are arranged on the surface of the epitaxial layer by heat treatment.
A method for producing a group V compound semiconductor epitaxial layer.