JPS63299113A - Manufacture of one-dimensional quantum thin line - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention is a method for manufacturing a one-dimensional quantum wire used for ultra-high-speed one-dimensional electronic transistors or nonlinear elements with high conversion efficiency using quantum interference. It is related to.

In the following explanation, () indicates the surface of the crystal, and [
] is the crystal axis.

(Prior Art) FIG. 5 shows the structure of a one-dimensional quantum wire that has been proposed in the past, using AIGaAa/GaAa as an example of the material.

In the figure, 1 is a semi-isolated GaAs substrate, 2 is a non-doped AlGa^3 growth layer, 3 is a non-doped GaAs growth layer, 4 is a non-doped AlGaAs spacer layer, and 5 is a Si-doped ^lGaAs grown layer. /
A one-dimensional electronic state is realized by modulation doping on the side surface of the superlattice of Ga Todo S. The part of the superlattice/AlGaAs interface surrounded by the dotted line in Figure 0 becomes a one-dimensional electronic state.

Next, a method for manufacturing this structure will be explained using FIG. 6. First, nondoped AlGaAs 2 and GaAs 3 are sequentially grown on a substrate 1 by molecular beam epitaxial method or metal organic vapor phase epitaxy to create a superlattice. The uppermost non-doped AlGaAs layer is formed to be thick. - Next, an etching mask 6 is placed in the [110] direction on the superlattice wafer, and steps are created by chemical etching or plasma etching (Fig. 6 (b));
After removing the etching mask 6, the non-doped AlGa is grown again by molecular beam epitaxial method or organometallic vapor phase epitaxy.
As4 is grown on the etched sides to a thickness of Ion-, followed by Sl-doped (~10"am-") AlGaA
By growing S 5 to a thickness of 100 nm, a one-dimensional electronic state is realized on the side surface of GaAs 3 which becomes a potential valley (FIG. 6 (C3)).

(Problems to be Solved by the Invention) However, the quantum wire manufacturing method described above has the following problems. The side surfaces (shaded areas in FIG. 5) formed by chemical etching are contaminated with carbon, oxygen, silicon, etc., and these contaminants pose a problem in that they become electron scattering factors and recombination centers. Furthermore, in chemical etching, the etching speed varies depending on the type of substrate, so the sides of the etching become uneven, which also causes scattering of electrons. On the other hand, when processing is performed by plasma etching, a damaged layer or altered layer is formed on the processed surface (the shaded area in FIG. 5). These layers also act as electron scattering factors and recombination centers, which poses the problem of significantly deteriorating the performance of devices using quantum wires. Since the quantum wire with the structure shown in Figure 5 uses side interfaces, contamination of the interfaces and processing damage are fatal defects.

(Purpose of the Invention) The present invention was proposed to improve the above-mentioned drawbacks, and its purpose is to form quantum wires only through a growth process without any processing steps such as etching. Not only is it completely free from processing damage and contamination, but also the steepness of the lateral interface can be controlled on the order of a single atom.
The object of the present invention is to provide a method for manufacturing high-quality one-dimensional quantum wires.

(Means for Solving the Problems) In order to achieve the above object, the present invention includes a step of forming a stripe growing steps in the [110] direction on a (001) compound semiconductor substrate surface, and Two or more types of low impurity concentration semiconductor layers are alternately laminated on the substrate by metal organic vapor phase epitaxy to grow trapezoidal superlattice stripes, and within the growth layers of the same type. forming at least one type of growth layer with a thickness of approximately 100 nanometers or less;
A method for producing a one-dimensional quantum wire, comprising the step of growing the trapezoidal superlattice to a thickness of nanometers or less, or burying the trapezoidal superlattice with a semiconductor having a high impurity concentration without growing it. This is the gist of the invention.

Therefore, in the present invention, a trapezoidal superlattice is grown on a substrate that has been processed into a predetermined shape using metal organic vapor phase epitaxy, and by subsequent growth, high impurities are added to the sides of the trapezoidal superlattice. The main feature is to form a semiconductor with high concentration, realize a one-dimensional electronic state through modulation doping, and create quantum wires.

Next, examples of the present invention will be described. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.

(Example) Hereinafter, examples of the present invention will be described in detail using AIGaAa/GaAs as an example of the material.

FIG. 1 shows the basic structure of a quantum wire produced by the method of the present invention, and the quantum wire exists in the interface portion surrounded by the dotted line.

In the figure, 1 is a semi-insulating GaAa substrate, 2 is a non-doped AlGaAs long layer, 3 is a non-doped GaAa growth layer, 4 is a non-doped AlGaAs spacer layer, and 5 is a Si-doped ^IGa^3 growth layer.

FIG. 2 shows the procedure for producing the structure shown in FIG. 1,
The following will be explained in order. First, (001) of GaAs substrate 1
A long stripe-shaped etching mask 6 is placed in the (110) direction on the substrate (Fig. 2(a)), and chemical etching or plasma etching is applied to the substrate in the (110) direction as shown in Fig. 2(c). Create stripes with steps. At this time, the sidewalls of the step may have any shape, and non-doped IG is deposited on this substrate using metal-organic vapor phase epitaxy.
AAa 2 and GaAs 3 are sequentially grown to a thickness of Ion-. At this time, no growth occurs on the side walls of the trapezoid, so a trapezoidal superlattice can be created (see Figure 2 (C
)), the growth conditions at this time will be described in detail later.
After growing more than n−, e.g. 100 n− (Fig. 2(
b)), S1 doped (~1G"am-") AlGaA
The growth of s5 on the top surface with zero step finally becomes triangular (Fig. 2(e)), after which it grows laterally, and as a result, the trapezoidal superlattice is covered with St-doped ^1GaAs 5. (Figure 2(f)).

Growth on the top surface of the step does not grow on the side walls at all until the shape becomes a triangle, but after it becomes triangular, growth occurs laterally from the side walls, so the structure shown in Figure 2 (0) can be realized. Due to the non-doped AlGaAs layer l, the trapezoidal top surface is not modulated doped, while the trapezoidal lattice side surfaces are St
Since it is in contact with doped AlGaAs 5, GaAs3
A one-dimensional electronic state can be realized by modulation doping at the interface between AlGaAs5 and AlGaAs5.

Note that a thin non-doped AlGaAs layer may be interposed between the side surface of the trapezoidal lattice and the St-doped AlGaA 15.

Next, the crystal growth conditions of this example will be described.

Growth is performed under normal pressure using a horizontal furnace with high-frequency heating.

Using trimethylgallium, trimethylaluminum, and arsine as raw materials, let θ be the angle between the side wall and the top surface of the layer grown on the top surface of the 0-step layer grown on the substrate l shown in FIG. As can be seen from the diagram 0 shown in Figure 3, which shows the relationship between θ and the growth conditions, θ is different from any growth temperature (Figure 3 (grape)), arsine partial pressure (Figure 3 ( b)), the partial pressure of trimethyl gallium (Fig. 3 (C)) shows exactly 55 degrees. From this, the side surface of the trapezoid is a (111) B plane, and this plane is an atomically flat surface. , and also has trapezoidal sides, i.e. (111
) It can be seen that no growth occurs on the 8th surface.

Here, the A side is the Ga side, and the B side is the As side. To confirm this, we investigated the dependence of growth rate on plane orientation. The results are shown in FIG.

From the figure it is clear that no growth occurs on the (111)8 plane. Therefore, the trapezoidal superlattice shown by @ in FIG. 2(c) can be easily produced by organometallic vapor phase epitaxy.

As explained above, according to the manufacturing method of this example, it can be manufactured only by the growth process without any processing process.
There is no etching contamination or processing damage, and the quantum wire has flat sides on the order of single atoms.

In this example, the explanation was given using ^IGa^s/GaAs-based materials, but m-v group semiconductors such as Ga1nP/GaAs, GafAs/IaP and their mixed crystal systems, Zn5e/GaAs
It can also be realized using II-Vl group semiconductors such as and mixed crystal materials thereof.

(Effects of the Invention) According to the manufacturing method of the present invention, since quantum wires are formed only in the growth process, not only are they completely free from processing damage and contamination, but also the steepness of the lateral interface can be easily reduced. It can be controlled on the atomic order, and it is possible to create high-quality one-dimensional quantum wires.

[Brief explanation of the drawing]

Figure 1 shows the basic structure of the quantum wire produced by the method of the present invention, Figure 2 shows the manufacturing procedure of the present invention, Figure 3 shows the relationship between the angle of the growth sidewall and growth conditions, and Figure 4 shows the growth rate and substrate surface. 5 is a cross-sectional view of a conventionally proposed quantum wire structure, and FIG. 6 is a diagram illustrating a conventionally proposed manufacturing method. 1... Semi-insulating GaAa substrate 2... Non-doped AlGaAs growth layer 3...
- Non-doped Ga^3 growth layer 4...Non-doped AlGaAs spacer layer 5...St-doped Al
GaAs growth layer 6... Etching mask Fig. 1 5--5i doped AI GaAsA long layer Fig. 2 growth! & (@C) Prusin →) Ning (K Tatsu) Trimekel potassium partial pressure (Kikihi) Figure 4 1 island, FLi side Eve L

Claims (1)

[Scope of Claims] (001) A step of forming stripes having steps in the [@1@10] direction on the surface of a compound semiconductor substrate, and two or more types of stripes formed on the semiconductor substrate by an organometallic vapor phase epitaxy method. The superlattice stripes are grown in a trapezoidal shape by alternately stacking semiconductor layers with low impurity concentration, and the thickness of at least one of the growth layers of the same type is approximately 10%.
forming a semiconductor with a low impurity concentration to a thickness of approximately 50 nanometers or less on at least the upper surface of the trapezoidal stacked layer; 1. A method for manufacturing a one-dimensional quantum wire, comprising the step of subsequently embedding the trapezoidal superlattice with a semiconductor having a high impurity concentration.