JP2699401B2 - Complementary semiconductor device and method of manufacturing the same - Google Patents

Description

The present invention relates to an active matrix type liquid crystal display, a thin film transistor applied to an image sensor, a three-dimensional integrated circuit, and the like. More specifically, the present invention relates to a complementary semiconductor device having a complementary MOS structure (CMOS structure) formed by thin film transistors and a method of manufacturing the same.

[Conventional technology]

Conventional CMOS thin film transistors are, for example, INTERNAT
As shown in IONAL DISPLAY RESEARCH CONFERENCE 1985, pages 9 to 13, p-type thin film transistors have been formed by doping ions serving as acceptors such as boron into the source and drain regions by ion implantation using a gate electrode as a mask. Next, an n-type thin film transistor is formed by selectively doping ions serving as donors such as phosphorus by ion implantation using a photoresist or the like.

[Problems to be solved by the invention]

However, the conventional thin film transistor has the following problems.

Since an ion implantation method is used to form the source and drain regions, the use of an expensive ion implantation device is indispensable, and two ion implantations are required, thus reducing the processing capability of the device. In addition, when applied to a liquid crystal display, it is essential to increase the size of the substrate, but it is difficult to increase the diameter of the ion beam, and it takes a lot of time to process a single substrate. For board (30cm ^□
) Ion implantation system has not been realized. Further, it is necessary to keep the substrate at a high temperature in order to activate the dopant after the ion implantation, and the substrate to be used is limited.

The present invention solves such a problem,
An object of the present invention is to provide a CMOS thin film transistor which can be formed on a large substrate at a low process temperature.

[Means for solving the problem]

The present invention relates to a method for manufacturing a complementary semiconductor device having a first conductivity type thin film transistor and a second conductivity type thin film transistor on a substrate, wherein a first silicon thin film containing a first conductivity type impurity is formed on the substrate. Forming a region to be a source / drain of the first conductivity type thin film transistor in an island shape by forming a second silicon thin film on the substrate;
Third impurity containing second conductivity type impurity on silicon thin film
Forming a silicon thin film and patterning the same to form regions that become the source and drain of the second conductivity type thin film transistor in an island shape.

The present invention relates to a complementary semiconductor device having a first conductivity type thin film transistor and a second conductivity type thin film transistor formed on a substrate, wherein the first conductivity type thin film transistor is formed in an island shape on the substrate. A first source / drain region formed of a first silicon thin film containing one conductivity type impurity, wherein the second conductivity type thin film transistor is formed as an island-shaped second silicon thin film on the substrate; And a second source / drain region formed of a third silicon thin film containing impurities of the second conductivity type, which is formed in an island shape on the second silicon thin film.

〔Example〕

Hereinafter, the present invention will be described in detail based on examples. FIG. 1 shows an example of a thin film transistor according to the present invention.
(A) is a top view, (b) is a cross-sectional view at AA '.

An n-type silicon thin film 102 made of a silicon thin film such as polycrystalline silicon amorphous silicon doped with an impurity serving as a donor is formed on an insulating substrate 101 such as glass, quartz, or sapphire.
They are formed at intervals L ₁ of the channel length of the mold the thin-film transistor. Whereas the non-doped polycrystalline silicon on an insulating substrate 101, a silicon thin film 103 such as amorphous silicon is formed at an interval of the channel length L ₂ of the p-type thin film transistor, and an acceptor in the same shape on the silicon thin film 103 A p-type silicon thin film 104 of polycrystalline silicon, amorphous silicon, or the like to which an impurity is added is formed. Contact with the two upper n-type silicon thin film 102, the line connecting both the width of the channel width W ₁ of the n-type transistor, polycrystalline silicon, the semiconductor layer made of silicon thin film such as amorphous silicon
105 are formed. Similarly, two p-type silicon thin films 1
04, the channel width W _{2 of the} p-type thin film transistor
A semiconductor layer 105 made of a silicon thin film such as polycrystalline silicon or amorphous silicon is formed so as to connect the two with a width of. The input electrode 106 made of metal, a transparent conductive film, or the like is
n-type thin film transistor such as n-type thin film transistor and p-type thin film transistor through gate insulating film such as iO ₂ , SiN, SiON
The n-type thin film transistor and the p-type thin film transistor 104 are formed so as to overlap with the p-type silicon thin film 104 so as to cover the semiconductor layer 105 in the channel portion. SiO ₂ , SiOn, SiON to cover this and the whole
And the like, and an n-type silicon thin film 102
A contact hole 110 is provided for making electrical contact on the p-type silicon thin film 103, and a metal, an output electrode 108 made of a conductive material such as a transparent conductive film,
The power supply electrode 109 is wired and forms a CMOS structure.

 FIG. 2 is a sectional view showing a manufacturing process.

Step of FIG. 2A An n-type silicon thin film 202 to which an impurity serving as a donor is added in contact with the insulating substrate 201 is formed by a low-pressure CVD method, a plasma CVD method, a vacuum evaporation method, or the like. The film thickness is desirably 500 to 5000 mm.

Step of FIG. 2B A non-doped silicon thin film 203 and a p-type silicon thin film 204 doped with impurities serving as acceptors are formed by a low pressure CVD method, a plasma CVD method, a vacuum evaporation method or the like so as to cover the entire insulating substrate 201. I do. The non-doped silicon thin film 203 and the p-type silicon thin film 204 may be formed continuously by the same device or by different devices. The film thickness of both is 50
0-5000mm is desirable. This non-doped silicon thin film prevents impurities serving as acceptors in the p-type silicon thin film 204 from diffusing into the n-type silicon thin film 202. This is particularly effective when the p-type silicon thin film 204 is formed at a high temperature such as a low pressure CVD method.

FIG. 2 (c) Step Non-doped silicon thin film 203 and p-type silicon thin film 2
04 is simultaneously processed into an island shape using photolithography. The p-type silicon thin film 204 and the non-doped silicon thin film 203 can be etched simultaneously without changing the etching method; The n-type silicon thin film 202 forming the source and drain regions of the n-type thin film transistor and the p-type silicon thin film 204 forming the source and drain regions of the p-type thin film transistor are formed by the film forming process shown in FIG. 2 and the photolithography process shown in FIG. This is formed without affecting the impurities serving as donors or acceptors.

Step (d) of FIG. 2 A semiconductor layer 205 is formed by a low pressure CVD method, a plasma CVD method, a vacuum evaporation method or the like so as to connect the two n-type silicon thin films 202 and the two p-type silicon thin films 204. The gate insulating film 207 is formed by a low pressure CVD method, a plasma CVD method,
It is formed by a sputtering method or the like. Its film thickness is 1000-5000
Å is desirable. Further, the input electrode 2 contacts the gate insulating film 207.
06 is formed by a CVD method, a sputtering method, or the like.

Step (e) of FIG. 2 An insulating film 211 is formed by a low-pressure CVD method, a plasma CVD method, a sputtering method, or the like so as to cover the whole thereof, and contact holes are formed on the n-type silicon thin film 202 and the p-type silicon thin film 204.
The output electrode 208 and the power supply electrode 209 are formed by a CVD method, a sputtering method, or the like.

Through the above steps, a semiconductor device having the structure shown in FIG. 1 was obtained.

The n-type silicon thin film 20 doped with an impurity serving as a donor
2 was first formed, but a p-type silicon thin film to which an impurity serving as an acceptor was added was first formed, then a non-doped silicon thin film, and then n to which an impurity serving as a donor was added.
A type silicon thin film may be formed.

FIG. 3A shows the characteristics of an n-type thin film transistor formed according to the present invention, and FIG. 3B shows the characteristics of a p-type thin film transistor. As is clear from these, a large ON current and a small OFF current can be simultaneously realized, and impurities serving as acceptors in the p-type silicon thin film 204 diffuse into the n-type silicon thin film 202 by the non-doped silicon thin film 203. Is hindering.

 This embodiment has the following excellent effects.

First, an n-type thin film transistor and a p-type thin film transistor can be realized at the same time without using an ion implantation apparatus on the same insulating substrate.

The second n-type thin film transistor can be formed without affecting the source and drain regions serving as donors and the p-type thin film transistor as source and drain regions serving as acceptors.

Third, it can be formed only by a CVD method, a sputtering method, or a vacuum evaporation method, which is highly mass-producible, and can be easily applied to a large substrate.

Fourth, since the impurities of the n-type thin film transistor and the p-type thin film transistor do not affect each other, a large ON current and a small OFF current can be simultaneously realized.

Fifth, the source and drain regions of the n-type thin film transistor and the p-type thin film transistor can be formed in a short process of forming the film shown in FIG. 2 and performing two photolithography processes.

Sixth, since there is no step of keeping the substrate at a high temperature, an inexpensive glass substrate can be used as the substrate, and the cost can be reduced.

〔The invention's effect〕

 The present invention has the following excellent effects.

(A) Impurities serving as source / drain regions of an n-type thin film transistor and impurities serving as source / drain regions of a p-type thin film transistor can be formed without affecting each other.

(B) Since the impurities of the n-type thin film transistor and the p-type thin film transistor do not affect each other, a large ON current and a small OFF current can be simultaneously realized.

[Brief description of the drawings]

1 (a) and 1 (b) show the structure of a thin film transistor according to the present invention, wherein (a) is a top view and (b) is a sectional view. 2 (a) to 2 (e) are cross-sectional views showing steps for manufacturing a thin film transistor according to the present invention. FIG. 3A is a characteristic diagram of an n-type thin film transistor according to the present invention, and FIG. 3B is a characteristic diagram of a p-type thin film transistor. 101, 201 ... insulating substrate 102, 202 ... n-type silicon thin film 103, 203 ... silicon thin film 104, 204 ... p-type silicon thin film 105, 205 ... semiconductor layer 106, 206 ... input electrode 107, 207 ... ... insulating layers 108, 208 ... output electrodes 109, 209 ... power supply electrodes 110, 210 ... contact holes 207 ... gate insulating film

Claims (2)

(57) [Claims] 1. A method for manufacturing a complementary semiconductor device having a first conductivity type thin film transistor and a second conductivity type thin film transistor on a substrate, comprising: forming a first silicon thin film containing a first conductivity type impurity on the substrate; By forming and patterning, the first
Forming a source / drain region of the conductive type thin film transistor in an island shape; forming a second silicon thin film on the substrate; forming a second conductive thin film on the second silicon thin film; By forming and patterning a third silicon thin film containing impurities,
Forming a region to be a source and a drain of the second conductivity type thin film transistor in an island shape. 2. A complementary semiconductor device having a first conductivity type thin film transistor and a second conductivity type thin film transistor formed on a substrate, wherein the first conductivity type thin film transistor is formed in an island shape on the substrate. A first source / drain region comprising a first silicon thin film containing a first conductivity type impurity, wherein the second conductivity type thin film transistor is formed on the substrate in the form of an island-shaped second silicon film; Complementary, characterized in that it has a thin film and a second source / drain region made of a third silicon thin film containing a second conductivity type impurity formed in an island shape on the second silicon thin film. Type semiconductor device.