JPH01272146A - Complementary semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor applied to active matrix type liquid crystal displays, image sensors, three-dimensional integrated circuits, and the like. More specifically, the present invention relates to a complementary MO3 structure (CMO3m structure) thin film transistor formed of thin film transistors.

[Conventional technology]

A conventional CMO3 structure thin film transistor is, for example, IN
TERNATIONAL DISPLAY RES
EARCHC0NFERENCE1985 P9~1
3, a p-type thin film transistor was formed by doping acceptor ions such as boron into the source and drain regions using the gate electrode as a mask using a photoresist. It was formed by selectively doping donor ions such as phosphorus using an ion implantation method.

[Problem to be solved by the invention]

However, conventional thin film transistors have the following problems.

Since the source and drain regions are formed using ion implantation, it is essential to use an expensive ion implantation device, and two additional ion implantations are required, reducing the processing capacity of the device. In addition, when applying to liquid crystal displays, it is essential to increase the size of the substrate, but it is difficult to increase the diameter of the ion beam, and it takes a lot of time to process one substrate. Compatible with substrates (30μm
An ion implantation device of approximately Furthermore, it is necessary to maintain the substrate at a high temperature to activate the dopant after ion implantation, which limits the types of substrates that can be used.

The present invention is intended to solve these problems, and its purpose is to provide a CMO3 structure thin film transistor that can be formed on a large substrate at a low process temperature.

[Means to solve the problem]

The semiconductor device of the present invention includes an n-type thin film transistor in which a source region and a drain region are a silicon thin film doped with donor impurities on an insulating substrate, and a non-doped silicon thin film doped with acceptor impurities on the insulating substrate. The present invention is characterized in that it includes a P-type thin film transistor that serves as a source region and a drain region through a thin film.

Further, the semiconductor device of the present invention includes an n-type thin film transistor in which a silicon thin film doped with an impurity as an acceptor is formed on an insulating substrate as a source region and a drain region, and a silicon thin film doped with an impurity as a donor is formed on the insulating substrate. n-type Nll! with source and drain regions via a non-doped silicon thin film. It is characterized by being equipped with a transistor.

〔Example〕

The present invention will be described in detail below based on Examples. 1st
An example of a thin film transistor according to the present invention is shown in the figure (a
) is a top view, and (b) is a cross-sectional view at AA'.

An n-type silicon thin film 102 made of a silicon thin film such as polycrystalline silicon or amorphous silicon doped with donor impurities is placed on an insulating substrate 101 made of glass, quartz, sapphire, etc. with an interval L1 equal to the channel length of an n-type thin film transistor. It is formed. - Silicon thin film 10 of non-doped polycrystalline silicon, amorphous silicon, etc. on the insulating substrate 101
A p-type silicon thin film 104 of polycrystalline silicon, amorphous silicon, etc. having the same shape and doped with an acceptor impurity is formed on the silicon #JIi 103 at an interval of 2, which is the channel length of an n-type thin film transistor. is formed. A semiconductor layer 105 made of a silicon thin film such as polycrystalline silicon or amorphous silicon is formed on a line that contacts the upper sides of two n-type silicon i[102 and connects them with a width equal to the channel width Wl of the n-type transistor. There is. Similarly, a semiconductor layer 105 made of a silicon thin film such as polycrystalline silicon or amorphous silicon is formed so as to touch the two p-type silicon thin films 111104 on their upper sides and connect them with a width equal to the channel width W2 of the n-type thin film transistor. There is.

In addition, the input electrode 106 made of metal, transparent conductive film, etc.
n via a gate insulating film such as Oz, SiN, 5iON, etc.
It is formed so as to overlap the n-type silicon thin film 102 and the p-type silicon thin film 104 of the type thin film transistor and the n-type thin film transistor, and to cover the semiconductor layer 105 of the channel part, and the input electrode 106 of the n-type thin film transistor and the n-type thin film transistor is It is connected. An insulating layer 107 of SiO2, 5LOn, 5iON, etc. is formed to cover the entire surface, and a contact hole 110 is provided on the n-type silicon thin film 102 and the p-type silicon thin film 103 to make electrical contact. Output electrodes 108 and power supply electrodes 109 are wired with conductive materials such as metals and transparent conductive films, forming a CMO3 structure.

FIG. 2 is a sectional view showing the manufacturing process.

In the step of FIG. 2(a), n-type silicon thin II doped with an impurity to serve as a donor in contact with the insulating substrate 201! 202 is formed by a low pressure CVD method, a plasma CVD method, a vacuum evaporation method, or the like. Its film thickness is 50
Preferably 0 to 5,000 people.

Process of FIG. 2(b) A non-doped silicon thin film 203 and a p-type silicon thin film 204 doped with acceptor impurities are deposited by low pressure CVD, plasma CVD, and so on to cover the entire insulating substrate 201.
Formed by vacuum evaporation method, etc. Non-doped silicon thin H2
O3 and the p-type silicon thin film 204 may be formed successively in the same device or in separate devices.The thickness of both films is preferably 500 to 5000 A.This non-doped silicon thin film is This is effective in preventing impurities that serve as acceptors in the p-type silicon thin film 204 from diffusing into the n-type silicon thin film 202, especially when the p-type silicon thin film 204 is formed at high temperatures such as by low-pressure CVD.

Step of FIG. 2(c) The non-doped silicon thin film 203 and the p-type silicon thin film 204 are simultaneously processed into an island shape using photolithography. The p-type silicon thin film 204 and the non-doped silicon thin film 203 can be etched simultaneously without changing the etching gas or the like. N-type silicon that forms the source and drain regions of n-type thin film transistors ``Thin II!'' 202 and a ρ-type silicon thin film 204 forming the source and drain regions of the n-type thin film transistor.
is formed by the film forming process shown in FIG. 2 and the photolithography process shown in FIG. 2, and the impurities serving as donors or acceptors are formed without affecting each other.

Step of FIG. 2(d) A semiconductor layer 205 is formed by low pressure CVD, plasma CVD, vacuum evaporation, etc. so as to connect the two n-type silicon thin films 202 and the two p-type silicon thin films 204. A gate insulating film 207 is formed by low pressure CVD to cover all of these.
It is formed by a plasma CVD method, a sputtering method, or the like. The film thickness is preferably 1000 to 5000 Å. Furthermore, the input electrode 206 is formed in contact with the gate insulating film 207 by CVD, sputtering, or the like.

Step of FIG. 2(e) An insulating film 211 is formed by a low pressure CVD method, plasma CVD method, sputtering method, etc. so as to cover all of these, and a contact hole 210 is formed on the n-type silicon thin film 202 and the p-type silicon thin film 204. The output electrode 208 is provided with a power supply voltage f! 209 is formed by a CVD method, a sputtering method, or the like.

Through the above steps, a semiconductor device having the structure shown in FIG. 1 could be obtained.

In addition, an n-type silicon thin film 20 doped with an impurity to serve as a donor.
2 was formed first, but first a ρ-type silicon thin film was formed without doping impurities to serve as acceptors, then a non-doped silicon thin film, and then an n-type silicon thin film doped with impurities to serve as donors.
It does not matter if a type silicon thin film is formed.

Figure 3(a) shows the characteristics of the n-type thin film transistor formed according to the present invention, and Figure 3(b) shows the characteristics of the n-type thin film transistor.As is clear from these, a large ON current and a small OFF current can be generated at the same time. This has been realized, and the p-type silicon thin film 204 is formed by the non-doped silicon thin film 203.
The impurity that becomes the acceptor inside is n-type silicon thin pA20
2. This prevents it from spreading into the rest of the world.

〔Effect of the invention〕

The present invention has the following excellent effects.

First, an n-type thin film transistor and an n-type thin film transistor can be simultaneously realized on the same insulating substrate without using an ion implantation device.

impurities that serve as donors for the source and drain regions of the second n-type thin film transistor and the source of the n-type thin film transistor;
Impurities serving as acceptors for the drain region can be formed without influencing each other.

Thirdly, it can be formed only by CVD, sputtering, and vacuum evaporation methods, which are highly suitable for mass production, and can also be easily applied to large substrates.

Fourthly, the characteristics of the n-type thin film transistor and the n-type thin film transistor are such that respective impurities do not affect each other, so that a large ON current and a small OFF current can be realized at the same time.

Fifth, the n-type thin film transistor and the source and drain regions of the n-type thin film transistor can be formed in a short process of film formation as shown in FIG. 2 and photolithography twice.

Sixthly, since there is no step of holding the substrate at a high temperature, an inexpensive glass substrate can be used as the substrate, resulting in cost reduction.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) show the structure of a thin film transistor according to the present invention, in which FIG. 1(a) is a top view and FIG. 1(b) is a sectional view. FIGS. 2(a) to 2(e) are cross-sectional views showing the manufacturing process of a thin film transistor according to the present invention. FIG. 3(a) is a characteristic diagram of an n-type thin film transistor according to the present invention, and FIG. 3(b) is a characteristic diagram of a p-type thin film transistor. 101.201...Insulating substrate 102.202...N-type silicon thin film 103.203
...Silicon thin film 104.204...N-type silicon thin film 105.205
...Semiconductor layer 106,206...Input electrode 107,211...Insulating layer 108,208...Output electrode 109,209...Power supply electrode 110,210...Contact hole 207...・
...Gate insulating film and above Applicant Seiko Epson Co., Ltd. agent Patent attorney Masatoshi Kamiyanagi (1 other person) (α) (Tono,? I2 Vers (voj!t) (α) V, S (Scream ( b) Defense 3 old

Claims (2)

[Claims] (1) An n-type thin film transistor with a silicon thin film doped with an impurity as a donor on an insulating substrate as a source region and a drain region, and a non-doped silicon thin film with a silicon thin film doped with an impurity as an acceptor on the insulating substrate. 1. A semiconductor device comprising a p-type thin film transistor having a source region and a drain region via the p-type thin film transistor. (2) A silicon thin film doped with acceptor impurities is placed on an insulating substrate as a source region and a drain region.
1. A semiconductor device comprising: a n-type thin film transistor; and an n-type thin film transistor in which a silicon thin film doped with donor impurities is formed on the insulating substrate as a source region and a drain region via a non-doped silicon thin film.