JPH047877A - thin film transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to thin film transistors.

[Conventional technology]

Japanese Patent Publication No. 60-251667 proposes a staggered thin film transistor as shown in FIG. Polycrystalline silicon containing impurities serving as donors or acceptors is deposited on an insulating substrate 201 and patterned to form source/drain regions 202. Next, an intrinsic polycrystalline silicon film 203 is laminated and patterned, a gate insulating film 204 and a gate electrode 205 are laminated, contact holes are opened, and source/drain electrode terminals 206 are formed to complete the process.

[Problem to be solved by the invention]

However, in the above-mentioned thin film transistor, since the step at the end of the source/drain region is steep, cracks are likely to occur in the gate electrode and gate wire at the step portion when forming the gate electrode and gate wire. Furthermore, even if no cracks occur, if a voltage is applied to the gate electrode after the transistor is formed, electric field concentration occurs due to the sharp stepped portions of the source/drain regions, significantly lowering the gate breakdown voltage [7].

The present invention solves these conventional problems,
The aim is to provide a thin film transistor with high gate breakdown voltage and good reproducibility.

[Means to solve the problem]

In the thin film transistor of the present invention, the cross-sectional shape of the peripheral portion of the source region and the drain region is set at an angle of 45° with respect to the insulating substrate.
It is characterized by being smaller than the degree.

〔Example〕

FIGS. 1(a) to 1(f) are cross-sectional views of each manufacturing process of a thin film transistor in an example of the present invention.

A thin film transistor according to an embodiment of the present invention is shown in FIG.
It has the structure shown in f).

101 is an insulating substrate, 103 is a source/drain region, 1
04 is an intrinsic polycrystalline silicon thin film that becomes a channel region, 1
05 is a gate insulating film, 106 is a gate electrode, and 107 is a source/drain electrode terminal.

This will be explained in detail below.

First, a polycrystalline silicon thin film 102 containing impurities serving as donors or acceptors is formed on an insulating substrate 101 (FIG. 1(a)). In this example, a glass substrate was used as an insulating substrate, phosphorus was used as an impurity, and about 1,500 people deposited the polycrystalline silicon thin film on the glass substrate by low pressure vapor phase growth using a mixed gas of phosphine PH3 and silane SiH4. Not limited to this, but 100
A desirable film thickness is 0 to 3,000. Next, after forming a resist on the thin film, the thin film is patterned using plasma of a mixture of CF4 and 02 to form source/drain regions 103. At this time, CF for 02
By reducing the amount of 4 (FIG. 2), the slope of the step of the pattern is made to be 45 degrees or less (FIG. 1(b)).

This slope has the purpose of preventing cracks in the gate electrode that will occur during subsequent formation of the gate electrode. Cracks in the gate electrode largely depend on the angle of inclination of the stepped portions of the source/drain regions, and will disappear if the inclination is made gentler, but cracks will not occur at approximately 45 degrees. Next, approximately 250 layers of an intrinsic polycrystalline silicon thin film 104 containing no impurities are deposited by vapor phase growth and patterned (FIG. 1(C)) to form a channel region.

Next, a silicon oxide film is deposited by vapor phase growth to form a gate insulating film 105 (FIG. 1(d)).

Next, chromium, which will become the gate electrode, is laminated by sputtering to cover the source/drain regions and channel region, and is patterned to overlap the source/drain regions to form the gate electrode 106 (see Fig. 1). e)
). In general, even if the sputtered film has poor step coverage,
A slope of 45 degrees or less provides sufficient coverage. As a result, the gate breakdown voltage is significantly improved beyond 45 degrees. (3rd
figure). After that, contact holes are opened and source/drain electrode terminals 107 are formed to complete the process (Fig. 1(f)
)).

It should be noted that the example given here is just one example.

〔Effect of the invention〕

The thin film transistor of the present invention has the following excellent effects.

First, since the slope of the step at the end of the source/drain region is gentle, vapor phase growth 5i02 and sputtered Cr, which have poor step coverage, can be used for the gate oxide film and the gate electrode, respectively, and the process is easy. It can be manufactured at low temperatures and at low cost.

Second, cracks in the gate electrode at the stepped portions of the source/drain regions are completely eliminated, improving the reliability of the device.

Thirdly, since the gate breakdown voltage is improved and the transistor is resistant to dielectric breakdown due to static electricity, it becomes easy to handle during the manufacturing process and after transistor formation, and is excellent in mass production.

Fourth, since unnecessary electric field concentration does not occur, the thickness of the gate insulating film can be reduced, and the device can be miniaturized, that is, the device can be integrated.

If the thin film transistor of the present invention is applied, for example, to a liquid crystal driving element of an active matrix liquid crystal display device, which has recently attracted attention as a thin display, a display with low defects and high definition can be manufactured.

[Brief explanation of drawings]

FIGS. 1(a) to 1(f) are cross-sectional views showing the manufacturing process of a thin film transistor according to an embodiment of the present invention. FIG. 2 is a diagram showing the correlation between the ratio of gas used and the angle according to the present invention. FIG. 3 is a diagram showing an improvement in gate breakdown voltage. FIG. 4 is a cross-sectional view showing the structure of a conventional thin film transistor. 106・ ・ 107・ ・ 201 ・φ 202・ ・ 203 ・・ 204 ・ ・ 205・ ・ 206φ ・ Gate electrode Source/drain electrode terminal Insulating substrate Source/drain region Intrinsic polycrystalline silicon film Gate insulating film Gate electrode Source/drain electrode Applicant for terminals and above Seiko Epson Co., Ltd. agent Patent attorney Kizobe Suzuki (and 1 other person) 101...
- Insulating substrate 102... Polycrystalline silicon thin film 103 containing impurities... Source/drain region 104... Intrinsic polycrystalline silicon thin film 105... Gate insulating film ○2/CF4 (d> (f)th Figure 1 Angle] Figure 3

Claims (1)

[Claims] A source region and a drain region made of a semiconductor thin film doped with impurities to serve as a donor or acceptor on an insulating substrate, a channel region made of a semiconductor thin film provided to connect the source region and the drain, and a gate covering the channel region. A thin film transistor comprising an insulating film and a gate electrode provided through the gate insulating film, characterized in that a cross-sectional shape of a peripheral portion of the source region and the drain region is smaller than an angle of 45 degrees with the insulating substrate. thin film transistor.