KR0130372B1 - Manufacturing method of liquid crystal display device - Google Patents
Manufacturing method of liquid crystal display deviceInfo
- Publication number
- KR0130372B1 KR0130372B1 KR1019940013743A KR19940013743A KR0130372B1 KR 0130372 B1 KR0130372 B1 KR 0130372B1 KR 1019940013743 A KR1019940013743 A KR 1019940013743A KR 19940013743 A KR19940013743 A KR 19940013743A KR 0130372 B1 KR0130372 B1 KR 0130372B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- source line
- gate
- insulating film
- source
- Prior art date
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims description 9
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910000838 Al alloy Inorganic materials 0.000 claims 1
- 239000012535 impurity Substances 0.000 claims 1
- 230000008018 melting Effects 0.000 abstract description 5
- 238000002844 melting Methods 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 45
- 239000010409 thin film Substances 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 229910008814 WSi2 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical group 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
- H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
- H01B1/02—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors mainly consisting of metals or alloys
- H01B1/023—Alloys based on aluminium
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 액정표시장치의 제조방법에 관한 것으로, 게이트라인을 소오스라인과동일한 재료로 소오스라인 형성시에 동시에 형성하여 사용된 배선재료의 용융점에관계없이 저저항의 배선재료를 사용할 수있도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal display device, wherein gate lines are formed of the same material as source lines at the same time so that low resistance wiring materials can be used regardless of the melting point of wiring materials used. .
본 발명은 투명 절연기판위에 활성층을 형성하는 단계, 상기 활성층을포함한 기판 상부에 게이트절연막을 형성하는 단계, 상기 게이트절연막위에 게이트전극과 제1소오스라인을 동시에 형성하는 단계, 상기 활성층의 소정영역에 소오스 및 드레인영역을 형성하는 단계, 기판 전면에층간절연막을 형성하는 단계, 상기 층간절연막 및 게이트절연막을 선택적으로 식각하여 상기 제1소오스라인과 게이트전극, 소오스 및드레인영역을 노출시키는 콘택홀을 형성하는 단계, 화소전극을 형성하는 단계, 상기 콘택홀을 통해 상기 게이트전극과 연결되는 게이트라인과 상기 제1소오스라인 및 소오스영역에 연결되는 제2소오스라인, 상기 드레인영역에 연결되는 드레인전극을 동시에 형성하는 단계로 구성되는 액정표시장치의 제조방법을 제공한다.The present invention provides a method of forming an active layer on a transparent insulating substrate, forming a gate insulating film on the substrate including the active layer, simultaneously forming a gate electrode and a first source line on the gate insulating film, and forming a predetermined region of the active layer. Forming a source and drain region, forming an interlayer insulating film over the substrate, and selectively etching the interlayer insulating film and the gate insulating film to form a contact hole exposing the first source line and the gate electrode, the source and drain regions. Forming a pixel electrode; simultaneously forming a gate line connected to the gate electrode through the contact hole, a second source line connected to the first source line and a source region, and a drain electrode connected to the drain region; It provides a method of manufacturing a liquid crystal display device comprising the step of forming.
Description
[발명의 명칭][Name of invention]
액정표시장치의 제조방법Manufacturing method of liquid crystal display device
[도면의 간단한 설명][Brief Description of Drawings]
본 발명은 액정표시장치의 제조방법에 관한 것으로, 게이트라인을 소오스라인과동일한 재료로 소오스라인 형성시에 동시에 형성하여 사용된 배선재료의 용융점에관계없이 저저항의 배선재료를 사용할 수있도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal display device, wherein gate lines are formed of the same material as source lines at the same time so that low resistance wiring materials can be used regardless of the melting point of wiring materials used. .
본 발명은 투명 절연기판위에 활성층을 형성하는 단계, 상기 활성층을포함한 기판 상부에 게이트절연막을 형성하는 단계, 상기 게이트절연막위에 게이트전극과 제1소오스라인을 동시에 형성하는 단계, 상기 활성층의 소정영역에 소오스 및 드레인영역을 형성하는 단계, 기판 전면에층간절연막을 형성하는 단계, 상기 층간절연막 및 게이트절연막을 선택적으로 식각하여 상기 제1소오스라인과 게이트전극, 소오스 및드레인영역을 노출시키는 콘택홀을 형성하는 단계, 화소전극을 형성하는 단계, 상기 콘택홀을 통해 상기 게이트전극과 연결되는 게이트라인과 상기 제1소오스라인 및 소오스영역에 연결되는 제2소오스라인, 상기 드레인영역에 연결되는 드레인전극을 동시에 형성하는 단계로 구성되는 액정표시장치의 제조방법을 제공한다.The present invention provides a method of forming an active layer on a transparent insulating substrate, forming a gate insulating film on the substrate including the active layer, simultaneously forming a gate electrode and a first source line on the gate insulating film, and forming a predetermined region of the active layer. Forming a source and drain region, forming an interlayer insulating film over the substrate, and selectively etching the interlayer insulating film and the gate insulating film to form a contact hole exposing the first source line and the gate electrode, the source and drain regions. Forming a pixel electrode; simultaneously forming a gate line connected to the gate electrode through the contact hole, a second source line connected to the first source line and a source region, and a drain electrode connected to the drain region; It provides a method of manufacturing a liquid crystal display device comprising the step of forming.
[도면의 간단한 설명][Brief Description of Drawings]
제1도는 종래의 액정표시장치의 평면도 및 단면도.1 is a plan view and a cross-sectional view of a conventional liquid crystal display device.
제2도는 본 발명에 의한 액정표시장치의 평면도 및 단면도.2 is a plan view and a cross-sectional view of a liquid crystal display device according to the present invention.
제3도는 본 발명에 의한 액정표시장치의 제조방법을도시한 공정순서도.3 is a process flowchart showing a method of manufacturing a liquid crystal display device according to the present invention.
제4도는 본 발명의 다른 실시에에 의한 액정표시장치의 단면구조도.4 is a cross-sectional structure diagram of a liquid crystal display device according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 투명 절연기판 2 : 버퍼층1: transparent insulating substrate 2: buffer layer
3 : 활성층 4 : 게이트절연막3: active layer 4: gate insulating film
5 : 게이트전극 5' : 제1 소오스라인5: gate electrode 5 ': first source line
6 : 층간절연막 7 : 화소전극6 interlayer insulating film 7 pixel electrode
8 : 제2 소오스라인 9 : 드레인전극8: second source line 9: drain electrode
10 : 게이트라인10: gate line
[발명의 상세한 설명]Detailed description of the invention
본 발명은 액정표시장치의 제조방법에 관한 것으로, 특히 액정표시장치의박막 트랜지스터 어레이부를 제조하는 방법에 관한 것이다. 종래 기술에 의해제조된 액정표시장치의 박막트랜지스터 어레이부의 평면도 및 단면도를 제1도에도시한 바, 이를 참조하여 종래의 액정표시장치 제조방법을 설명하면 다음과 같다. 제1도 (a)는 액정표시장치의 박막트랜지스터 어레이부의평면도이고, (b)와 (c)는 각각 제1도 (a)의 A-A' 및 B-B'선에 따른 단면도이다. 유리나 석영과 같은 절연성 투명기판(1)위에절연막을 증착하여 버퍼층(2)을 형성하고, 이위에 반도체층을 증착하고 패터닝하여 아일랜드(island)형태의 활성층(3)을 형성한 다음 그 위에 산화막 또는 질화막등의 절연막을 증착하여 게이트절연막(4)을 형성한다. 이어게이트절연막(4)상에도우프드(doped)폴리실리콘이나 실리사이드와 같은 막을증착한 후 패터닝하여 게이트라인(5)을형성하고,N형 또는 P형의도판트(dopant)를 주입하고 활성화시켜 상기 활성층(3)의 소정부분에 소오스 및 드레인영역(S/D)을 형성하고, 이위에 층간절연막(6)을 증착하고 이를 선택적으로 식각하여 콘택홀을 형성한 다음, 그위에 ITO(Indium Tin Oxide)와 같은 투명전도막을 증착하고 패터닝하여 화소전극(7)을 형성한다. 이어 기판 전면에 금속이나 실리사이드와 같은 막을 증착하고 패터닝하여 소오스라인(8)과 드레인전극(9)을 형성한다. 상술한 바왁 같이 종래기술에서는 액정표시장치의 박막트랜지스터 어레이부의 게이트라인으로 N형 또는 P형의도판트가 주입된도우프드 폴리실리콘이나 WSi2등의 실리사이드가 많이 사용되고 있다.그러나 이와 같은 재료는 저항이 비교적높아 화소수가 증가하거나 게이트라인이 길어질 경우 게이트신호를 지연시키는 문제가 발생하게 된다. 한편, A1합금은 저항은 아주 작지만 용융점(melting poi nt)이 낮아 고온에서 견디지 못하기 때문에 게이트라인으로 사용할 경우 차후의 공정온도를 500℃이상으로 증가시킬 수 없다. 따라서본 발명은 상기 종래기술의 문제점을 해결하기 위해 게이트라인을 소오스라인과 동일한 재료로 소오스라인 형성시에 동시에 형성하여 사용된 배선재료의 용융점에 관계없이 저저항의 배선재료를 사용할 수 있도록 한 액정표시장치의 제조방법을제공하는 것을 그 목적으로 한다. 상기 목적을 달성하기 위한 본 발명의액정표시장치 제조방법은 투명 절연기판위에 활성층을 형성하는 단계, 상기 활성층을 포함한 기판 상부에 게이트절연막을 형성하는 단계, 상기 게이트절연막위에 게이트전극과 제1 소오스라인을 동시에 형성하는 단계, 상기 활성층의 소정영역에소오스 및 드레인영역을 형성하는 단계, 기판 전면에 층간절연막을 형성하는 단계, 상기 층간절연막 및 게이트절연막을 선택적으로 각하여 상기 제1 소오스라인과 게이트전극, 소오스 및 드레인영역을 노출시키는 콘택홀을 형성하는 단계, 그위에 화속전극을 형성하는 단계, 상기 콘택홀을 통해 상기 게이트전극과 연결되는게이트라인과 상기 제1 소오스라인 및 소오스영역에 연결되는 제2 소오스라인, 상기 드레인영역에 연결되는 드레인전극을 동시에 형성하는 단계로 구성된다.The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor array portion of a liquid crystal display device. A plan view and a cross-sectional view of a thin film transistor array unit of a liquid crystal display device manufactured according to the related art are shown in FIG. 1. Referring to this, a conventional method of manufacturing a liquid crystal display device is as follows. FIG. 1A is a plan view of a thin film transistor array unit of a liquid crystal display, and (b) and (c) are cross-sectional views taken along the lines A-A 'and B-B' of FIG. Depositing an insulating film on an insulating transparent substrate 1 such as glass or quartz to form a buffer layer 2, depositing and patterning a semiconductor layer thereon to form an island-like active layer 3, and then forming an oxide film or An insulating film such as a nitride film is deposited to form a gate insulating film 4. A film such as doped polysilicon or silicide is deposited on the ear gate insulating film 4, and then patterned to form a gate line 5, and an N-type or P-type dopant is injected and activated. Source and drain regions (S / D) are formed in a predetermined portion of the active layer 3, an interlayer insulating film 6 is deposited thereon, and selectively etched to form contact holes, and thereafter, ITO (Indium Tin) is formed thereon. The pixel electrode 7 is formed by depositing and patterning a transparent conductive film such as oxide. Subsequently, a film such as metal or silicide is deposited on the entire surface of the substrate and patterned to form a source line 8 and a drain electrode 9. As described above, in the prior art, silicides such as doped polysilicon or WSi2 into which the N-type or P-type dopant is injected into the gate line of the thin film transistor array portion of the liquid crystal display are widely used. If the number of pixels is relatively high or the gate line is lengthened, the gate signal may be delayed. On the other hand, A1 alloy is very small resistance, but the melting point (melting pont) is not able to withstand the high temperature can not increase the subsequent process temperature above 500 ℃ when used as a gate line. Therefore, in order to solve the problems of the prior art, the gate line is formed of the same material as the source line at the same time to form the source line so that a low-resistance wiring material can be used regardless of the melting point of the wiring material used. It is an object of the present invention to provide a method for manufacturing a display device. The liquid crystal display device manufacturing method of the present invention for achieving the above object comprises the steps of forming an active layer on a transparent insulating substrate, forming a gate insulating film on the substrate including the active layer, a gate electrode and a first source line on the gate insulating film Simultaneously forming, forming a source and a drain region in a predetermined region of the active layer, forming an interlayer insulating film on the entire surface of the substrate, selectively selecting the interlayer insulating film and the gate insulating film, respectively, and forming the first source line and the gate electrode. Forming a contact hole exposing the source and drain regions, forming a fire electrode thereon, a gate line connected to the gate electrode through the contact hole, and a first source line connected to the first source line and the source region; Simultaneously forming a source line and a drain electrode connected to the drain region; It is composed.
이하, 첨부된도면을 참조하여 본 발명을상세히 설명한다. 제2도에 본 발명에 의해 제조된 액정표시장치의 박막트랜지스터 어레이부의 평면도 및 단면도를도시하였다. 제2도 (a)는 액정표시장치의 박막트랜지스터 어레이부의 평면도이고, (b)와 (c)는 각각 제2도 (a)의 A-A' 및 B-B'선에 따른 단면도이다. 제2도에도시된 바와 같이 본 발명의 액정표시장치는 게이트전극(5)과 게이트라인(10)으로 분리되고, 소오스라인을 제1 소오스라인(5')과 제2 소오스라인(8)으로 분리되어 형성된다.상기 게이트전극(5)과 게이트라인(10)은 층간절연막(6)울 개재하여 형성되며 소정영역에서 콘택홀을 통해 연결되며, 상기 제1 소오스라인(5')은 소오스라 과게이트라인이 교차되는 부분을 포함한 영역에 형성되고 제2 소오스라인(8)과는 소정영역에서 콘택홀을 통해 연결된다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention. 2 is a plan view and a cross-sectional view of a thin film transistor array unit of a liquid crystal display device manufactured according to the present invention. FIG. 2A is a plan view of a thin film transistor array unit of a liquid crystal display, and FIGS. 2B and 3C are cross-sectional views taken along the lines A-A 'and B-B' of FIG. 2A, respectively. As shown in FIG. 2, the liquid crystal display of the present invention is divided into a gate electrode 5 and a gate line 10, and the source line is divided into a first source line 5 ′ and a second source line 8. The gate electrode 5 and the gate line 10 are formed through the interlayer insulating layer 6 and are connected through a contact hole in a predetermined region, and the first source line 5 'is a source. The second gate line 8 is formed in a region including an intersection portion of the overgate line and is connected to the second source line 8 through a contact hole in a predetermined region.
제3도를 참조하여 본 발명에 의한 액정표시장치의 제조방법을 설명하면 다음과 같다. 먼저, 제3도 (a)에도시된 바와 같이 유리나 석영과 같은 절연성 투명기판(1)위에절연막을 증착하여 버퍼층(2)을 형성한 후, 제3도 (b)에도시된 바와 같이 상기 버퍼층(2)상에 반도체증을증착하고 패터닝하여 아일랜드(island)형태의 활성층(3)을 형성한다. 이어서 제3도(c)에도시된 바와 같이 기판 전면에 산화막 또는 질화막등의절연막을 증착하여 게이트절연막(4)을 형성하고, 이위에도우프드(doped)폴리실리콘이나 실리사이드와 같은도전막(5)을 증착한다. 다음에 제3도 (d)에도시된 바와 같이 상기도전막(5)을 포토레지스트(PR)를 이용한 사진식각공정에 의해 패터닝하여 게이트전극(5)과 제1 소오스라인(5')을 형성한 후, N형 또는 P형의도판트(dopant)를 이온주입하고 활성화시켜 상기 활성층(3)의 소정영역에 소오스 및 드레인영역(S/D)을형성한다. 이어서 제3도 (e)에 도시된 바와 같이 기판 전면에 층간절연막(6)을 증착한후, 상기층간절연막(6) 및 게이트절연막(4)을 선택적으로 식각하여 상기 제1 소오스라인(5')과 소오스 및 드레인영역(S/D)을 노출시키는 콘택홀을 형성한다. 다음에 제3도(f)에도시된 바와 같이 기판상에ITO(Indium Tin Oxide)와 같은 투명전도막을 증착하고 패터닝하여 화소전극(7)을 형성한다. 이어서 제3도 (g)에도시된바와 같이 기판 전면에 A1과 같은 금속이나 실리사이 같은 막을 증착한 후, 패터닝하여 상기 콘택홀을 통해 게이트전극(5)과 연결되는 게이트라인(10)과 제1 소오스라인(5')과 소오스영역(S/D)에 연결되는제2 소오스라인(8) 및 드레인영역(S/D)에 연결되는 드레인전극(9)을 동시에 형성한다. 상기 공정에서 제3도 (d)의 제1소오스라인(5')형성시 제2도(a) 및 (b)에도시된바와 같이 게이트라인(10)과 교차되는 부분을 포함한 일부분만 남도록 패터닝할 수도 있으며, 또한 제2소오스라인(8)의 아래부분에까지 전부 남도록 패터닝할 수도 있는데 이 경우에는 소오스라인의 단선에의한 결함을 제1 소오스라인과 제2 소오스라인의 상호보완에 의해 감소시킬 수 있게 된다. 한편, 본 발명의 다른 실시예에 의한 액정표시장치 제조방법을 제4도를 참조하여 설명하면 다음과 같다. 상기 실시예에서와 같이 제1 소오스라인을 게이트전극과 동일한 막으로 형성하는 방법대신에제4도에도시된 바와같이 박막트랜지스터의활성층으로 사용되는 반도체층(3)과동일한 막으로 제1 소오스라인(5')을 형성한다. 즉, 유리나 석영과 같은 절연성 투명기판(1)위에 절연막을 증착하여 버퍼층(2)을 형성한후, 상기 버퍼층(2)상에 반도체층을 증착하고 패터닝하여 아일랜드(island)형태의 활성층(3)과제1 소오스라인패턴을 형성한 다음 기판전면에 산화막 또는 질화막등의 절연막을 증착하여 게이트절연막(4)을 형성하고 이위에도우프드(doped)폴리실리콘이나 실리사이드와 같은도전막(5)을 증착하고 패터닝하여 게이트전극을 형성한 후, N형 또는 P형의도판트(dopant)를 이온주입하고 활성화시켜 기 활성층(3)의 소정영역에 소오스 및 드레인영역(S/D)을 형성함과 동시에 제1 소오스라인(5')을 형성한다.Referring to FIG. 3, the manufacturing method of the liquid crystal display device according to the present invention will be described. First, as shown in FIG. 3 (a), an insulating film is deposited on an insulating transparent substrate 1 such as glass or quartz to form a buffer layer 2, and then as shown in FIG. 3 (b), the buffer layer. Deposition and patterning the semiconductor deposition on (2) to form the island-like active layer (3). Subsequently, as shown in FIG. 3 (c), an insulating film such as an oxide film or a nitride film is deposited on the entire surface of the substrate to form a gate insulating film 4, and a conductive film 5 such as doped polysilicon or silicide is formed. E). Next, as illustrated in FIG. 3D, the conductive film 5 is patterned by a photolithography process using a photoresist PR to form the gate electrode 5 and the first source line 5 ′. Subsequently, an N-type or P-type dopant is ion-implanted and activated to form a source and drain region S / D in a predetermined region of the active layer 3. Subsequently, as shown in FIG. 3E, an interlayer insulating film 6 is deposited on the entire surface of the substrate, and then the interlayer insulating film 6 and the gate insulating film 4 are selectively etched to form the first source line 5 '. ) And a contact hole exposing the source and drain regions S / D. Next, as illustrated in FIG. 3F, a transparent conductive film such as indium tin oxide (ITO) is deposited and patterned on the substrate to form the pixel electrode 7. Subsequently, as shown in FIG. 3 (g), a metal such as A1 or a silicide is deposited on the entire surface of the substrate, and then patterned to form a gate line 10 and a gate electrode connected to the gate electrode 5 through the contact hole. A first source line 5 'and a second source line 8 connected to the source region S / D and a drain electrode 9 connected to the drain region S / D are simultaneously formed. In the process, when forming the first source line 5 'of FIG. 3 (d), patterning is performed so that only a portion including a portion intersecting the gate line 10 remains as shown in FIGS. 2A and 2B. In addition, the patterning may be performed so that the lower portion of the second source line remains all the same. In this case, defects due to disconnection of the source line may be reduced by complementary complementation of the first source line and the second source line. It becomes possible. Meanwhile, a method of manufacturing a liquid crystal display device according to another embodiment of the present invention will be described with reference to FIG. 4. Instead of forming the first source line with the same film as the gate electrode as in the above embodiment, as shown in FIG. 4, the first source line is the same as the semiconductor layer 3 used as the active layer of the thin film transistor. To form 5 '. That is, an insulating film is deposited on an insulating transparent substrate 1 such as glass or quartz to form a buffer layer 2, and then a semiconductor layer is deposited and patterned on the buffer layer 2 to form an island-like active layer 3. Task 1 After the source line pattern is formed, an insulating film such as an oxide film or a nitride film is deposited on the entire surface of the substrate to form a gate insulating film 4, and a conductive film 5 such as doped polysilicon or silicide is deposited. After patterning to form a gate electrode, an N-type or P-type dopant is ion implanted and activated to form a source and a drain region (S / D) in a predetermined region of the active layer 3, and simultaneously 1 source line 5 'is formed.
이어서 기판 전면에 층간절연막(6)을 증착한 후, 상기 층간절연막(6)및 게이트절연막(4)을 선택적으로 식각하여 상기 제1 소오스라인(5')과 소오스및 드레인영역(S/D)을 노출시키는콘택홀을 형성한다음 기판상에 ITO(Indium Tin Oxide)와 같은 투명전도막을 증착하고 패터닝하여 화소전극(7)을 형성하고, 기판전면에A1과 같은 금속이나 실리사이드 같은 막을 증착한 후, 패터닝하여 싱기 콘택홀을 통해 게이트전극(5)과 연결되는 게이트라인(10)과 제1 소오스라인(5')과 소오스영역(S/D)에 연결되는 제2 소오스라인(8)및 드레인영역(S/D)에 연결되는 드레인전극(9)을 동시에 형성한다. 이와 같이 본 발명에서는 게이트전극을 먼저 형성한후,소오스라인형성시에 게이트라인을 동시에 형성하므로 게이트전극 형성후의 차후 공정온도에 의해 게이트라인의 재질이 영향받지 않으므로 용융점이 낮아 사용이 불가능했던 A1합금등과 같은 저저항의 재료를 이용하여 게이트라인을 형성할 수 있기 때문에 게이트라인의 RC 시간지연을 감소시킬 수 있다. 따라서 화소수가많은 HD급 액정표시장치나 게이트라인이 길어지는 대화면 직시형 액정표시장치에 적용할 경우 좋은화질을 얻을 수 있게 된다.Subsequently, after the interlayer insulating film 6 is deposited on the entire surface of the substrate, the interlayer insulating film 6 and the gate insulating film 4 are selectively etched to form the first source line 5 'and the source and drain regions S / D. After forming a contact hole exposing the contact hole, a transparent conductive film such as indium tin oxide (ITO) is deposited and patterned on the substrate to form a pixel electrode 7, and then a metal such as A1 or a silicide film is deposited on the front surface of the substrate. And the gate line 10 connected to the gate electrode 5 through the singer contact hole, the second source line 8 connected to the first source line 5 ', and the source region S / D, and the drain. A drain electrode 9 connected to the region S / D is formed at the same time. Thus, in the present invention, since the gate electrode is formed first and then the gate line is formed at the time of source line formation, the material of the gate line is not affected by the subsequent process temperature after the formation of the gate electrode. Since the gate line can be formed using a material having a low resistance such as or the like, the RC time delay of the gate line can be reduced. Therefore, when applied to an HD-class liquid crystal display device having a large number of pixels or a large-screen direct view liquid crystal display device having a long gate line, a good picture quality can be obtained.
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| KR1019940013743A KR0130372B1 (en) | 1994-06-17 | 1994-06-17 | Manufacturing method of liquid crystal display device |
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| US6323932B1 (en) | 1996-04-12 | 2001-11-27 | Semiconductor Energy Laboratory Co., Ltd | Liquid crystal display device and method for fabricating thereof |
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| JPH1048610A (en) * | 1996-07-31 | 1998-02-20 | Furontetsuku:Kk | Liquid crystal display element |
| KR100266216B1 (en) * | 1997-10-15 | 2000-09-15 | 구본준; 론 위라하디락사 | Thin Film Transistor Structure and Manufacturing Method |
| KR100267995B1 (en) * | 1997-10-30 | 2000-10-16 | 구자홍 | LCD and its manufacturing method |
| KR100267993B1 (en) * | 1997-11-26 | 2000-10-16 | 구자홍 | liquid crystal display and method of the same |
| KR100267994B1 (en) * | 1997-11-26 | 2000-10-16 | 구자홍 | method for manufacturing of Liquid Crystal Display |
| KR100265567B1 (en) * | 1997-12-29 | 2000-09-15 | 김영환 | Lcd and its fabrication method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6323932B1 (en) | 1996-04-12 | 2001-11-27 | Semiconductor Energy Laboratory Co., Ltd | Liquid crystal display device and method for fabricating thereof |
| US7095478B2 (en) | 1996-04-12 | 2006-08-22 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and method for fabricating thereof |
| US7196749B2 (en) | 1996-04-12 | 2007-03-27 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and method for fabricating thereof |
| US7636136B2 (en) | 1996-04-12 | 2009-12-22 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and method for fabricating thereof |
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