JPH08181319A - Thin-film transistor and its manufacture - Google Patents

Abstract

PURPOSE: To enhance the characteristic of a TFT by a method wherein a conductive layer at the edge part of a channel protective film is cut surely and a leakage current between a source electrode and a drain electrode is prevented. CONSTITUTION: A lower gate electrode 103 which has been patterned to a prescribed shape is formed on an insulating substrate 101. An Si3 N4 film 105, a semiconductor film 106 and an Si3 N4 film 107 are formed continuously. While the gate electrode 103 is used as a mask, the rear is exposed from the side of the transparent insulating substrate 101, the Si3 N4 film 107 is patterned to a prescribed shape by a photolithographic process, and a channel protective film 107 is formed. Then, the semiconductor film 106 is doped with impurity ions, and an n<+> silicon layer 108 is formed. A conductive layer region 109 as a cause to generate a leakage current between a source electrode and a drain electrode is etched and removed together with the channel protective film 107 so that the conductive layer region can be cut by a patterning operation. A source electrode and a drain electrode 110 are formed by patterning to a prescribed shape.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly, to a liquid crystal display (TFT: Thin Film Transistor) using a thin film transistor.
TECHNICAL FIELD The present invention relates to a structure of a semiconductor device applied to an er-LCD (Liquid Crystal Display) and a manufacturing method thereof.

[0002]

2. Description of the Related Art As a known document describing a conventional thin film transistor, for example, Japanese Patent Laid-Open No. 63-16805.
There is No. 2 publication. This publication discloses a self-aligned thin film transistor that can be stably manufactured without a lift-off process in manufacturing an amorphous silicon thin film transistor in order to reduce parasitic capacitance and realize high performance of a device, and a manufacturing method thereof. It provides a method. That is, a method for manufacturing a fully self-aligned thin film transistor using an ion doping method is shown. US Pat. No. 5,241,192 also discloses a thin film transistor structure for reducing edge leakage.

FIG. 5 is a block diagram of a conventional thin film transistor, in which 201 is an insulating substrate, 202 is a gate electrode, and
203 is a gate insulating film, 204 is an amorphous silicon thin film,
Reference numeral 205 is a channel protective film, 206 is an n + type amorphous silicon thin film, 207 is a source / drain electrode, and 208 is a pixel electrode.

In this case, the channel protective film is formed in a self-aligned manner by backside exposure using the gate electrode as a mask,
The amorphous silicon thin film 206 is formed by using a patterned channel protective film as a mask to decompose a gas containing impurities such as phosphine diluted with hydrogen by discharge, and accelerating and injecting the generated ions. Then source
A completely self-aligned TFT by forming a drain metal electrode and a pixel electrode having electrical connection with the drain electrode
Is completed.

[0005]

As described above, in the conventional thin film transistor, the formation of the n + layer is achieved by implanting impurity ions by the ion doping method using the channel protective film 205 as a mask. At the time of this ion doping, the edge portion of the channel protection film 205 serving as a mask for the ion doping is, as shown in FIG.
Due to its processing characteristics, it has a certain taper angle, and in the region below the taper of the channel protection layer 205, there are at least some implanted impurity ions, and the conductive layer formed by the impurity ions has some degree of difference. 209 is formed (FIG. 7). If the conductive layer 209 is not completely removed, a leak current occurs between the source and drain electrodes of the transistor due to the conductive layer formed at the edge of the channel protective film 205, and good transistor characteristics cannot be obtained.

The present invention has been made in view of the above circumstances, and in a thin film transistor in which an n + layer is formed by an ion doping method, the conductive layer at the edge portion of the channel protective film is reliably cut off to form a source / drain. An object of the present invention is to provide a thin film transistor and a method for manufacturing the same that solve the problem of leakage current between electrodes and reliably remove the n + conductive layer region generated at the edge of an ion implantation mask to improve thin film transistor characteristics. I am trying.

[0007]

In order to solve the above problems, the present invention provides (1) a gate electrode 103 formed on a transparent insulating substrate 101, and a first electrode formed so as to cover the gate electrode 103. First insulating film 105 and the first insulating film 1
05, the second insulating film 107 formed on the semiconductor layer 106 is self-aligned with the gate electrode 103 using the gate electrode 103 as a mask. A thin film transistor having an inverted staggered structure in which the second insulating film 107 or the resist pattern of the second insulating film 107 is used as a mask to dope the semiconductor layer 106 with impurities to form the n + layer 108. The second insulating film 1
Of the region in which impurities are ion-implanted into the semiconductor layer 106 below 07, the part connected between the source and the drain is cut, or (2) the transparent insulating substrate 12
1. An amorphous or microcrystalline or polycrystalline semiconductor layer 123 formed on the first insulating film 124, a first insulating film 124 formed so as to cover the semiconductor layer 123, and a first insulating film 124 formed on the first insulating film 124. The gate electrode 125 and the gate electrode 125 or the resist pattern of the gate electrode 125 is used as a mask to dope the semiconductor layer 123 with impurities, and n +
A positive staggered or top-gate thin film transistor forming the layer 122, wherein a region of the semiconductor layer 123 below the gate electrode 125 is ion-implanted with impurities.
The portion connecting between the source and the drain is cut off, and further, (3) in the thin film transistor having the inverted stagger structure, the gate electrode 103 formed on the transparent insulating substrate 101 and the gate electrode 103 are covered. The first insulating film 105 formed as described above, and the first insulating film 1
05, a step of forming an amorphous semiconductor layer or a microcrystalline semiconductor layer 106 and a second insulating film 107, and the second insulating film 107 formed on the semiconductor layer 106 using the gate electrode 103 as a mask. A step of patterning the gate electrode 103 in a self-aligned manner, and using the second insulating film 107 or the resist pattern of the second insulating film 107 as a mask, the semiconductor layer 106 is doped with impurities to form an n + layer 108. And cutting the part of the region where impurities are ion-implanted into the semiconductor layer 106 under the second insulating film 107, which is connected between the source and the drain, or (4) In a positive stagger or top gate type thin film transistor, an amorphous or microcrystalline or polycrystalline semiconductor layer 123 formed on a transparent insulating substrate 121. Forming, the semiconductor layer 12
And a gate electrode 125 on the first insulating film 124.
And a gate electrode 125 or a resist pattern on the gate electrode 125 is used as a mask to dope the semiconductor layer 123 with impurities to form an n + layer 122.
And a step of cutting a portion of the region where impurities are ion-implanted into the semiconductor layer 123 below the gate electrode 125, a portion connecting between the source and the drain is cut.

[0008]

According to the thin film transistor of the present invention having the above structure and the method for manufacturing the same, after the ion doping step in the thin film transistor manufacturing step, the edge portion of the channel protective film and the semiconductor layer formed below the edge portion are separately removed by etching. A process is added to prevent leakage current of the transistor.

(1) In the invention described in claim 1, the gate electrode is formed on a transparent insulating substrate, and the first insulating film is formed so as to cover the gate electrode. The amorphous semiconductor layer or the microcrystalline semiconductor layer is formed over the first insulating film, and the second insulating film is formed over the semiconductor using the gate electrode as a mask. The second insulating film is patterned in a self-aligned manner with the gate electrode, and the n + layer is the second insulating film.
Is formed by doping the semiconductor layer with an impurity using the resist pattern of the insulating film or the second insulating film as a mask. In the region where impurities are ion-implanted into the semiconductor layer under the second insulating film, the portion connected between the source and the drain is cut off, so that the leak current of the transistor can be prevented.

(2) In the invention of claim 2, the amorphous, microcrystalline or polycrystalline semiconductor layer is formed on a transparent insulating substrate, and the first insulating film is formed so as to cover the semiconductor layer. . The gate electrode is formed on the first insulating film, and the n + layer is formed by doping impurities on the semiconductor layer using the gate electrode or the resist pattern of the gate electrode as a mask. Of the region in which impurities have been ion-implanted into the semiconductor layer under the gate electrode, the part connected between the source and drain is cut off,
Leakage current of the transistor can be prevented.

(3) In the invention according to claim 3, a gate electrode formed on a transparent insulating substrate, a first insulating film formed so as to cover the gate electrode, and a first insulating film on the first insulating film. An amorphous semiconductor layer or a microcrystalline semiconductor layer and a second insulating film are formed on the substrate, and the second insulating film formed on the semiconductor layer is patterned in a self-aligned manner with the gate electrode using the gate electrode as a mask. The semiconductor layer under the second insulating film is doped with impurities by using the second insulating film or the resist pattern of the second insulating film as a mask to dope the semiconductor layer with impurities. Since the part of the injected region that is connected between the source and the drain is cut off, it is possible to prevent a leak current that occurs between the source and the drain and to realize good transistor characteristics with excellent leak characteristics.

(4) In the invention described in claim 4, an amorphous or microcrystalline or polycrystalline semiconductor layer formed on a transparent insulating substrate is formed, and the first semiconductor layer is formed so as to cover the semiconductor layer. Forming an insulating film, forming a gate electrode on the first insulating film, using the gate electrode or the resist pattern on the gate electrode as a mask, doping impurities on the semiconductor to form an n + layer, Of the region where impurities are ion-implanted in the semiconductor layer below the gate electrode, the source
Since the part connected between the drains is cut off, it is possible to prevent a leak current generated between the source and the drain and to realize good transistor characteristics with excellent leak characteristics.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2A and 2B are configuration diagrams for explaining an embodiment of a thin film transistor according to the present invention, which is a TFT (Thin Film Transistor) -LCD (Li.
FIG. 3 is a cross-sectional view of a TFT matrix type substrate for quid crystal display). In the figure, 101 is an insulating substrate, 102 is a base coat insulating film, 103 is a tantalum thin film, 104 is an anodic oxide film, 105 is a Si ₃ N ₄ film, 106 is a semiconductor film, 107
Is a Si ₃ N ₄ film, 108 is an n + silicon layer, 109 is a conductive layer region, 110 is a source / drain electrode, and 111 is a pixel electrode (indium oxide transparent conductive film: ITO).

In this embodiment, a glass substrate is used as the insulating substrate 101. Next, a base coat insulating film 102 made of Ta ₂ O _{5 is} formed on one surface of the substrate to a thickness of 3000 Å. On top of this, a film thickness of 300 is formed on the base coat insulating film by a sputtering device.
The tantalum thin film 103 is formed so as to be 0Å. Then, the tantalum thin film 103 is patterned into a predetermined shape by a photolithography process to form a lower gate electrode 103.
To form. Then, the tantalum thin film 103 is anodized to form an anodized film 104. Next, PC
A Si ₃ N ₄ film 105 as a gate insulating film is formed by VD (Chemical Vapor Deposition) method at 3000 Å,
The amorphous silicon (a-Si) semiconductor film 106 is set to 300.
Å, Si ₃ N ₄ film 107 is 2000 Å, and three layers are continuously formed.

Next, using the gate electrode 103 as a mask, backside exposure is performed from the transparent insulating substrate 101 side, and the Si ₃ N ₄ film 107 is patterned into a predetermined shape by a photolithography process to form a channel protective film 107. . Next, using the channel protection film 107 as a mask, the a-Si semiconductor film 106 is doped with an acceleration voltage of 10 ke as a doping condition.
v, a dose amount of 5 × 10 ¹⁵ / cm ² was doped with impurity ions, and then annealed at 250 ° C. for 1 hour, and n +
A silicon layer 108 is formed.

After that, patterning is performed by a photolithography process so that the conductive layer region 109 that causes a leak current between the source and drain electrodes can be cut by patterning, and is removed by etching together with the upper channel protection film 107. Next, the semiconductor layer is patterned into an island shape to form a Ti film 3000Å. A source / drain electrode 110 is formed by patterning into a predetermined shape by a photolithography process. The removal of the conductive layer region 109 is sufficient as long as the source side and the drain side are not connected, and the shape is arbitrary. In addition, the conductive layer region 109
Alternatively, the step of patterning the semiconductor film into an island shape may be combined with one step. Then, the ITO transparent conductive film 111 is formed by sputtering to a thickness of 1000 liters. Then, a pixel electrode 111 is formed by patterning into a predetermined shape by a photolithography process. As a result, a TFT can be realized.

As described above, the gate electrode 103 is formed on the transparent insulating substrate 101, and the first insulating film 105 is formed so as to cover the gate electrode 103. The amorphous semiconductor layer or the microcrystalline semiconductor layer 106 is the first insulating film 10
The second insulating film 107 is formed on the semiconductor 106 by using the gate electrode 103 as a mask. The second insulating film 107 is patterned in a self-aligned manner with the gate electrode 103, and the n + layer 108 is masked with the second insulating film 107 or the resist pattern of the second insulating film 107 as a mask. It is formed by doping impurities. Of the region where impurities are ion-implanted into the semiconductor layer 106 under the second insulating film 107,
Since the part connected between the source and the drain is cut off, leakage current of the transistor can be prevented.

The amorphous, microcrystalline or polycrystalline semiconductor layer 106 is formed on the transparent insulating substrate 101, and the first insulating film 105 is formed so as to cover the semiconductor layer 106. A gate electrode is formed on the first insulating film 105, and the n + layer 108 is formed on the semiconductor layer 10 using the gate electrode or the resist pattern of the gate electrode as a mask.
6 is formed by doping impurities. Of the region in which impurities are ion-implanted into the semiconductor layer 106 under the gate electrode, the part connected between the source and the drain is cut off, so that the leak current of the transistor can be prevented.

Further, the gate electrode 103 formed on the transparent insulating substrate 101, the first insulating film 105 formed so as to cover the gate electrode 103, and the first insulating film 10
Forming an amorphous semiconductor layer or a microcrystalline semiconductor layer 106 and a second insulating film 107 on the semiconductor layer 5; and using the gate electrode 103 as a mask, the second insulating film 107 formed on the semiconductor layer 106 is removed. A step of patterning the gate electrode 103 in a self-aligned manner, and using the second insulating film 107 or the resist pattern of the second insulating film 107 as a mask, the semiconductor layer 106 is doped with impurities to form an n + layer 108. And a step of cutting a portion of the region where impurities are ion-implanted into the semiconductor layer 106 under the second insulating film 107, which is connected between the source and the drain, between the source and the drain. It is possible to prevent a leak current that occurs and to realize good transistor characteristics with excellent leak characteristics.

A step of forming an amorphous, microcrystalline or polycrystalline semiconductor layer formed on the transparent insulating substrate 101, and a step of forming an eleventh insulating film formed to cover the semiconductor layer. A step of forming a gate electrode on the first insulating film, a step of forming an n + layer 108 by doping impurities on the semiconductor using the gate electrode or a resist pattern on the gate electrode as a mask, A step of cutting a portion of the semiconductor layer below the gate electrode where the impurities are ion-implanted, the portion being connected between the source and the drain. Good transistor characteristics with excellent characteristics can be realized.

When the semiconductor layer is doped with impurities, a step of forming a cap layer for doping, a step of separately forming a mask for defining a doping region on the cap layer, and then impurities are ion-implanted. Since the process has a step of cutting a portion of the region which is connected between the source and the drain, it is possible to prevent a leak current generated between the source and the drain and to realize a good transistor characteristic having an excellent leak characteristic.

In the above description, the channel protection film 107 is formed and the semiconductor film 106 is doped with impurity ions using the mask as a mask. However, instead of the channel protection film 107, a photoresist or other material having a similar shape is used. It is also possible to form a mask pattern with and use this as a mask to dope the semiconductor layer with impurity ions. Although the example in which a-Si is used as the semiconductor layer is shown, of course, microcrystalline silicon may be used.

FIG. 3 is a constitutional view for explaining another embodiment of the thin film transistor according to the present invention, in which 121 is an insulating substrate, 122 is an n + semiconductor layer, 123 is a semiconductor layer,
Reference numeral 124 is a first insulating film, and 125 is a gate electrode. The semiconductor layer 123 is an amorphous, microcrystalline, or polycrystalline semiconductor layer formed over the insulating substrate 121. The first insulating film 124 is formed so as to cover the semiconductor layer 123. The gate electrode 125 is the first insulator film 1
It is formed on 24. Using the gate electrode 125 or the resist pattern of the gate electrode 125 as a mask, the semiconductor layer 123 is doped with impurities, and the n + layer 12
In the positive staggered or top gate type thin film transistor forming 2, the region where the source and drain are connected is cut off in the region where the impurity is ion-implanted into the semiconductor layer 123 under the gate electrode 125.

In the positive stagger or top gate type thin film transistor, the amorphous or microcrystalline or polycrystalline semiconductor layer 12 formed on the transparent insulating substrate 121.
3, a step of forming a first insulating film 124 formed so as to cover the semiconductor layer 123, and a step of forming the first insulating film 124.
Forming the gate electrode 125 on the insulating film 124, and using the gate electrode 125 or the resist pattern on the gate electrode 125 as a mask to dope impurities on the semiconductor layer 123 to form the n + layer 122. And a step of cutting a portion, which is connected between the source and the drain, of a region where impurities are ion-implanted into the semiconductor layer 123 under the gate electrode 125.

FIG. 4 is a constitutional view for explaining still another embodiment of the thin film transistor according to the present invention. In FIG.
Reference numeral 6 denotes an n + layer (gap layer), and other parts having the same functions as those in FIG. 3 are designated by the same reference numerals. Semiconductor layer 123
A cap layer for doping is used when impurity doping is performed. That is, the n + layer 126 is formed as a gap layer on the semiconductor layer 123. In addition, the semiconductor layer 12
3 when doping impurities into the third layer, a step of forming a cap layer 126 for doping, and a step of separately forming a mask for defining a doping region on the cap layer 126,
Then, there is a step of cutting a part of the region into which the impurities are ion-implanted, which is connected between the source and the drain.

[0026]

As is apparent from the above description, the present invention has the following effects. (1) Effects corresponding to claims 1 to 4: In a thin film transistor in which impurity ions are implanted into a semiconductor layer to form an n-type contact layer, a conductive region underneath an edge portion of a channel protective film caused by ion doping is completely removed. Then
It is characterized by solving the problem of leakage current generated between the source and drain. As a result of the above, a good transistor characteristic having an excellent leak characteristic as compared with the conventional manufacturing method is realized. (2) Effect corresponding to claim 1: A gate electrode formed on a transparent insulating substrate, a first insulating film formed so as to cover the gate electrode, and formed on the first insulating film With the amorphous semiconductor layer or the microcrystalline semiconductor layer and the gate electrode as a mask, the second insulating film formed on the semiconductor is patterned in self-alignment with the gate electrode,
Using the resist pattern of the insulating film or the second insulating film as a mask, the semiconductor layer is doped with impurities to form an n + layer. In the region where impurities are ion-implanted into the semiconductor layer under the second insulating film, the portion connected between the source and the drain is cut off, so that the leak current of the transistor can be prevented. (3) Effect corresponding to claim 2: An amorphous or microcrystalline or polycrystalline semiconductor layer formed on a transparent insulating substrate,
A first insulating film formed so as to cover the semiconductor layer, a gate electrode formed on the first insulating film, and the gate electrode or a resist pattern of the gate electrode as a mask, and the semiconductor layer is formed on the semiconductor layer. Are doped with impurities to form an n + layer. Of the region in which impurities are ion-implanted into the semiconductor layer under the gate electrode, the part connected between the source and the drain is cut off, so that the leak current of the transistor can be prevented. (4) Effect corresponding to claim 3: A gate electrode formed on a transparent insulating substrate, a first insulating film formed so as to cover the gate electrode, and amorphous on the first insulating film. Forming a high-quality semiconductor layer or a microcrystalline semiconductor layer and a second insulating film, and patterning the second insulating film formed on the semiconductor layer in a self-aligned manner with the gate electrode using the gate electrode as a mask And, using the second insulating film or the resist pattern of the second insulating film as a mask, doping the semiconductor layer with impurities to form an n + layer, and forming a n + layer on the semiconductor layer below the second insulating film. Since a step of cutting a portion of the region where the impurities are ion-implanted is connected between the source and the drain, a leak current generated between the source and the drain is prevented, and a good transistor having an excellent leak characteristic is provided. Data characteristics can be realized. (5) Effect corresponding to claim 4: A step of forming an amorphous or microcrystalline or polycrystalline semiconductor layer formed on a transparent insulating substrate, and a first step formed so as to cover the semiconductor layer.
Forming a first insulating film, forming a gate electrode on the first insulating film, and using the gate electrode or the resist pattern on the gate electrode as a mask to dope the semiconductor with impurities, Since the step of forming a layer and the step of cutting a portion of the region where impurities are ion-implanted into the semiconductor layer under the gate electrode are connected to each other between the source and the drain, a leak generated between the source and the drain is included. It is possible to prevent current and realize good transistor characteristics with excellent leakage characteristics.

[Brief description of drawings]

FIG. 1 is a configuration diagram illustrating an embodiment of a thin film transistor according to the present invention.

FIG. 2 is a plan view of FIG.

FIG. 3 is a configuration diagram for explaining another embodiment of the thin film transistor according to the present invention.

FIG. 4 is a configuration diagram for explaining still another embodiment of the thin film transistor according to the present invention.

FIG. 5 is a configuration diagram of a conventional thin film transistor.

FIG. 6 is a diagram showing an edge portion of a conventional channel protective film.

FIG. 7 is a plan view of FIG.

[Explanation of symbols]

101 ... Insulating substrate, 102 ... Base coat insulating film, 10
3 ... Tantalum thin film, 104 ... Anodized film, 105 ... Si
₃ N ₄ film, 106 ... Semiconductor film, 107 ... Si ₃ N ₄ film, 10
8 ... N + silicon layer, 109 ... Conductive layer region, 110 ... Source / drain electrodes, 111 ... Picture element electrodes (indium oxide transparent conductive film: ITO), 121 ... Insulating substrate, 122 ...
n + semiconductor layer, 123 ... Semiconductor layer, 124 ... First insulating film, 125 ... Gate electrode, 126 ... N + layer (gap layer).

Claims (4)

[Claims] 1. A gate electrode formed on a transparent insulating substrate, a first insulating film formed so as to cover the gate electrode, and an amorphous semiconductor layer formed on the first insulating film. Alternatively, by using the microcrystalline semiconductor layer and the gate electrode as a mask, the second insulating film formed on the semiconductor layer is patterned in a self-aligned manner with the gate electrode to obtain the second insulating film or the second insulating film. What is claimed is: 1. A thin film transistor having an inverted stagger structure in which an impurity is doped into the semiconductor layer to form an n + layer by using a resist pattern of the film as a mask.
A thin film transistor, characterized in that, of the region in which impurities are ion-implanted into the semiconductor layer under the insulating film, the part connected between the source and the drain is cut. 2. An amorphous or microcrystalline or polycrystalline semiconductor layer formed on a transparent insulating substrate, a first insulating film formed so as to cover the semiconductor layer, and a first insulating film on the first insulating film. A positive stagger or top gate type thin film transistor in which an n + layer is formed by doping an impurity on the semiconductor layer by using the gate electrode formed on the gate electrode and the resist pattern of the gate electrode or the gate electrode as a mask, A thin film transistor, characterized in that, of a region in which impurities are ion-implanted into a semiconductor layer under an electrode, a portion connected between a source and a drain is cut. 3. A thin film transistor having an inverted stagger structure, comprising: a gate electrode formed on a transparent insulating substrate;
A first insulating film formed to cover the gate electrode,
A step of forming an amorphous semiconductor layer or a microcrystalline semiconductor layer and a second insulating film over the first insulating film; and a second insulating film formed over the semiconductor layer using the gate electrode as a mask. Patterning in a self-aligned manner with the gate electrode,
With the second insulating film or the resist pattern of the second insulating film as a mask, the semiconductor layer is doped with impurities,
The method further includes a step of forming an n + layer and a step of cutting a portion of the region in which impurities have been ion-implanted into the semiconductor layer below the second insulating film, the portion being connected between the source and the drain. Method of manufacturing thin film transistor. 4. In a positive stagger or top gate type thin film transistor, a step of forming an amorphous or microcrystalline or polycrystalline semiconductor layer formed on a transparent insulating substrate, and a step of covering the semiconductor layer. Forming a first insulating film, forming a gate electrode on the first insulating film, and using the gate electrode or the resist pattern on the gate electrode as a mask to dope the semiconductor layer with impurities. , N + layer and a step of disconnecting a portion of the region where impurities are ion-implanted into the semiconductor layer under the gate electrode, which is connected between the source and the drain, of the thin film transistor. Production method.