JPH1012882A - Thin film transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a thin film transistor of superior productivity and a structure thereof wherein resistance of a gate electrode wiring can be made low, ohmic connection of an active layer with a source/drain electrode is possible, and the number of masks required in a manufacturing process is small. SOLUTION: An amorphous silicon layer 12 and a first insulating film 15 are continuously accumulated on an insulating substrate 11 by plasma CVD method. The first insulating film 15 is worked into an island shape together with the amorphous silicon layer 12. A second insulating film 16 and a metal wiring layer are accumulated on the first insulating film 15. After the metal wiring layer is etched to form a gate electrode 17, the second insulating film 16 and the first insulating film 15 are etched to form a gate insulating film. The part of the amorphous silicon layer which has been exposed in the preceding process is doped with ions and irradiated with laser with the gate electrode 17 as a mask, and the part is polycrystallized to form a source region 13 and a drain region 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a structure of a thin film transistor used as a switching element of a liquid crystal display element and a method of manufacturing the same. Further, the present invention relates to a structure of a thin film transistor array using the thin film transistor having the above structure and an active matrix liquid crystal display element.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device using a twisted nematic (TN) type liquid crystal,
It has excellent characteristics such as large capacity and high density, and is widely used for television displays, graphic displays, and the like.

In such an active matrix type liquid crystal display device, a method of driving and controlling each pixel by a semiconductor switch is adopted so that high contrast display without crosstalk can be performed. This semiconductor switch has an active layer (channel, source and drain regions) made of amorphous silicon on a glass substrate because a transmission type display is possible and the area can be relatively easily increased. The formed thin film transistor (TFT) is used.

The structure of such an amorphous silicon TFT is such that an inverted staggered TFT in which a gate electrode is disposed below an amorphous silicon layer as an active layer, or a gate electrode is disposed in an upper layer. Forward staggered TFTs and the like are generally known.

[0005] Of these, the inverted staggered TFT easily obtains good transistor characteristics, but has a structure in which a gate electrode is arranged on the lower layer side, so that it is not easy to reduce the gate wiring resistance. When applied to an active matrix type liquid crystal display element, the element requiring the lowest resistance among the constituent elements of the TFT is the gate electrode wiring (scanning line), and this problem becomes more serious as the LCD becomes larger. Become. Regarding productivity, in the inverted staggered structure, usually,
Since six or more masks are required, there is a problem that cost reduction is not easy.

On the other hand, in a forward staggered type TFT, the gate electrode is disposed on the upper side of the amorphous silicon layer (top gate type), and the source / drain electrode layers are disposed on the lower side. It is possible to reduce the number to one, which is advantageous in terms of productivity and manufacturing cost. Also,
Since it is a top gate type, it is possible to use Al as a gate electrode wiring, and it is easy to increase the film thickness.

However, conventionally, this forward staggered structure also has the following problems. First, ohmic contact between n + a-Si formed on the source / drain electrodes and a-Si of the active layer is difficult, and a sufficient on-current cannot be obtained in the TFT. There is an idea of using ITO (Indium Tin Oxide) for the source / drain electrodes and performing a plasma treatment of PH _{3 on} the ITO surface before forming the a-Si. Adversely affected by the contamination of Also, the overlap between the source / drain electrode and the gate electrode is large,
The parasitic capacitance between the source and the gate / drain increases.

US Pat. No. 4,727,044 discloses a method of manufacturing a top gate type TFT as described below.
That is, an amorphous silicon layer is formed on a glass substrate, and a gate electrode is formed on the amorphous silicon layer via a gate insulating film. Next, using this gate electrode as a mask, the amorphous silicon layer corresponding to the source and drain regions is subjected to ion doping and laser irradiation,
The portion of the amorphous silicon layer is recrystallized. A portion of the amorphous silicon layer masked by the gate electrode forms a channel. When a co-planar TFT, which is a kind of top gate TFT and similar to a single crystal silicon LSI, is formed by using this process, an insulating protective film is formed on the gate electrode, source and drain regions. After forming a contact hole in the insulating protective film, a source electrode and a drain electrode are formed.

However, the TFT structure described in the above-mentioned US Pat. No. 4,727,044 has the following problems. First, considering application to a liquid crystal display element,
It is necessary to process an amorphous silicon layer into an island shape and to separate a semiconductor layer between adjacent TFTs. In this case, the amorphous silicon layer is processed into an island shape before forming the gate insulating film, but it is difficult to clean the interface (channel interface) between the amorphous silicon layer and the gate insulating film. Therefore, a TFT excellent in mobility, reliability, and the like cannot be obtained.

In performing ion doping on the amorphous silicon layer corresponding to the source and drain regions,
To dope the source and drain amorphous silicon layers under the gate insulating film through the gate insulating film, a very high accelerating voltage is required. In a single-crystal silicon LSI process, ion implantation is usually performed through a gate insulating film. Ion implantation through the gate insulating film is possible only when the thickness of the gate insulating film is 50
This is because the thickness is as thin as nm or less. On the other hand, in a TFT used for a liquid crystal display element, an interlayer insulating film between a scanning line and a data line is commonly used as a gate insulating film in order to reduce the number of steps. From the viewpoint of reducing the capacitance at the intersection with the data line, a 200-500 nm thick film is used for the gate insulating film. With this film thickness, even if the acceleration voltage for ion doping is set to 100 kV, ions do not reach the amorphous silicon layer.
Substantially no ion doping through the gate insulating film is possible.

Further, in the recrystallization of the amorphous silicon layer by laser irradiation, the laser irradiation from above the gate insulating film causes the amorphous silicon layer to become amorphous due to the release of gas such as hydrogen from the amorphous silicon layer. Induced phenomena (ablation) in which high quality silicon is scattered are likely to occur. In addition to the induced phenomenon (ablation), if an insulating film is present on the amorphous silicon layer, the insulating film causes laser light interference. There is also a problem that the intensity of the laser beam incident on the silicon layer changes. Thus, it is difficult to stably recrystallize the amorphous silicon layer by laser irradiation from above the gate insulating film.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to reduce the resistance of a gate electrode wiring (scanning line) easily, It is an object of the present invention to provide a method and a structure for manufacturing a thin film transistor in which ohmic connection between a layer and a source electrode and a drain electrode is reliably performed, and the number of masks required in a manufacturing process can be reduced, and thus productivity is excellent. is there.

[0013]

[Means for Solving the Problems]

(Method of Manufacturing Thin Film Transistor) In a method of manufacturing a thin film transistor of the present invention, a step of depositing an amorphous silicon layer on an insulating substrate by a plasma CVD method, and a step of precedingly depositing an amorphous silicon layer on the amorphous silicon layer Continuously depositing a first insulating film by a plasma CVD method,
Processing the first insulating film, together with the amorphous silicon layer thereunder, into an island shape, and depositing a second insulating film on the island-shaped first insulating film A step of depositing a metal wiring layer on the second insulating film, using a resist pattern, etching the metal wiring layer to form a gate electrode, and using the resist pattern,
Forming a gate insulating film by etching the second insulating film and the first insulating film; and using a gate electrode as a mask in a portion of the amorphous silicon layer exposed in the preceding etching step. A step of doping with impurity ions and a step of using the gate electrode as a mask to polycrystallize the portion by laser irradiation.

Preferably, the first insulating film and the second insulating film are both made of silicon nitride, and the etching of these insulating films is performed by using a mixed gas containing CHF ₃ and O ₂ as main components, or , using a reactive ion etching method using a mixed gas mainly composed of CF ₄ and H _2.

In the above manufacturing method, the gate insulating film is composed of the two layers of the first and second insulating films, and the amorphous silicon layer, which is the semiconductor layer, is formed at the same time as the first insulating film. After being processed into a shape, they are entirely covered with a second insulating film. By adopting such a process, a patterning process is not interposed between the deposition of the amorphous silicon layer and the deposition of the first insulating film (gate insulating film). An insulating film can be continuously deposited by a plasma CVD method while maintaining a vacuum state in the same reaction chamber. As a result, it is easy to obtain a clean interface (channel interface) between the amorphous silicon layer and the gate insulating film, and it is possible to manufacture a TFT having excellent characteristics such as mobility and reliability. it can.

Since the amorphous silicon layer is processed into an island shape before forming the gate electrode, the semiconductor layers are completely separated from each other between adjacent TFTs when forming a TFT array. No field TFT is formed.

The source and drain regions formed in a self-aligned manner using the gate electrode as a mask are formed by a conventional CVD method because the doping element is sufficiently activated by polycrystallization by laser irradiation. n + a-Si
The electric resistance is smaller than that of (n-type amorphous silicon). Therefore, a sufficient ohmic contact can be secured between the source region and the source electrode and between the drain region and the drain electrode. As a result, in a TFT having a dop gate structure using amorphous silicon for an active layer,
It is possible to simultaneously improve the TFT characteristics and reduce the parasitic capacitance, which have conventionally been problems.

Before the ion doping, the gate insulating film is etched in advance with the same pattern as the gate electrode to expose the surface of the amorphous silicon layer. Ion doping becomes possible. Note that if an insulating film is present on the amorphous silicon layer, the amorphous silicon layer is likely to be ablated (ablated) during laser irradiation. It is important to keep the

When silicon nitride is used as the gate insulating film, the same resist pattern as that used for etching the gate electrode is used for the etching. At this time, if side etching occurs with respect to the gate electrode, interlayer short-circuit between the gate electrode and the source or drain region is likely to occur, or the gate electrode protruding in an eaves-like shape will be shaded during ion doping or laser irradiation. Make TF
T characteristics may be degraded. Therefore, it is necessary to prevent side etching. Furthermore, in order to leave the underlying amorphous silicon layer, it is necessary to employ an etching method having a high selectivity. As a method satisfying both conditions, reactive ion etching using a mixed gas containing at least C, H and F, such as a mixed gas of CHF ₃ and O ₂ or a mixed gas of CF ₄ and H ₂ is effective. It is. (Structure of Thin Film Transistor) Therefore, the structure of the thin film transistor according to the present invention based on the above-described manufacturing method comprises an amorphous silicon layer formed in an island shape on an insulating substrate, and a gate formed on the amorphous silicon layer. A first insulating film formed in a strip shape with a width corresponding to the length, a second insulating film formed with the width on the first insulating film, and the width on the second insulating film; Wherein the channel region of the thin film transistor is formed by a region corresponding to a portion of the amorphous silicon layer covered by the gate electrode, wherein the thin film transistor The source region and the drain region are formed by doping impurity ions using the gate electrode as a mask and subsequently irradiating a part of the amorphous silicon layer by laser irradiation. Thus it is formed, characterized in that is. (Connection between source and drain electrodes) Regarding connection of the source electrode and the drain electrode to the thin film transistor having the above structure, preferably, the source electrode is connected between the source region and the insulating substrate, and the drain electrode is similarly connected to the drain. It is arranged between the region and the insulating substrate, respectively.

In this case, prior to the deposition of the amorphous silicon layer, the source electrode and the drain electrode are formed so that the distance between them is wider than the width of the gate electrode formed in a subsequent step. Then, the amorphous silicon layer is
By performing polycrystallization by ion doping and laser irradiation using the gate electrode as a mask, the channel length is determined in a self-aligned manner with respect to the gate electrode, and at the same time, the source region and the source electrode with reduced resistance, and The drain region and the drain electrode are respectively connected.

In this case, before ion doping,
It is particularly important that the gate insulating film is etched in advance in the same pattern as the gate electrode to expose the surface of the amorphous silicon layer. The reason is that, in order to connect the source electrode and the drain electrode to the lower surface of the low-resistance polycrystalline silicon layer, it is necessary to implant impurities deeply when ion-doping the amorphous silicon layer.

The material of the source electrode and the drain electrode needs to be a material having a low melting point and a high melting point that can withstand high temperatures during laser irradiation. In this regard,
MoW alloys and MoTa alloys are materials that satisfy both requirements and are desirable. In particular, MoW alloys are more preferable because they have lower resistance than MoTa alloys. (Structure of Thin Film Transistor Array-Part 1) With respect to the structure of a thin film transistor array using a thin film transistor having the above structure as a switching element, it is possible to arrange pixel electrodes on either the lower side or the upper side of the thin film transistor. .

When the pixel electrodes are arranged on the lower layer side of the thin film transistor, the structure of the thin film transistor array of the present invention is such that the pixel electrodes arranged two-dimensionally on the insulating substrate and the pixel electrodes arranged between the adjacent pixel electrodes are arranged. And a scanning line that intersects with the data line and is disposed on the upper layer side of the data line via the second insulating film. The source electrode of the thin film transistor is provided on the upper surface of the pixel electrode. Connected, the drain electrode of the thin film transistor is formed integrally with the data line, the gate electrode of the thin film transistor is formed integrally with the scanning line, and the upper surfaces of the thin film transistor, the data line and the scanning line are Characterized by being covered with an insulating protective film.

The thin film transistor array having the above structure is manufactured by the following process. After depositing a transparent conductive thin film (for example, ITO) on an insulating substrate, a metal thin film is deposited thereon, and the metal thin film and the transparent conductive thin film are simultaneously patterned to be laminated on the transparent conductive thin film. The data line, the drain electrode integrated with the data line, and the pixel electrode covered with the metal thin film are simultaneously formed. next,
A thin film transistor having the above-described structure and a scanning line are formed thereon. After depositing an insulating protective film thereon, the insulating protective film in the pixel electrode region is removed by etching, and further, the metal thin film in the region is etched and removed to form a source electrode. According to the above process, the number of patterning steps required for forming a TFT array can be reduced by one.

It should be noted that the simultaneous processing of the pixel electrode and the data line can be achieved by an inverted staggered TFT having a bottom gate structure or a conventional forward staggered TFT. The contact portion of the drain region has a structure in which ITO is connected on the n + a-Si layer, and it is difficult to obtain good contact characteristics in such a system. On the other hand, in the conventional forward staggered TFT, if the source / drain electrode surfaces are metal films as described above, the effect of the plasma treatment of PH ₃ is small, and it is also difficult to obtain good contact characteristics.
In contrast, the thin film transistor having the structure of the present invention uses polycrystalline silicon formed by laser irradiation as a contact layer with the source and drain electrodes, so that a good contact can be easily obtained and the pixel electrode And the data line can be processed simultaneously. (Structure of Thin Film Transistor Array—Part 2) On the other hand, when the pixel electrode is arranged on the upper layer side of the thin film transistor, the structure of the thin film transistor array of the present invention is such that the data lines arranged on the insulating substrate intersect with the data lines. A scanning line arranged on the upper layer side of the data line via the second insulating film, an insulating substrate, an insulating protective film deposited so as to cover the upper surface of the data line and the scanning line, On the top surface of the protective film,
A pixel electrode arranged in a portion corresponding to each area divided by a data line and a scanning line, and a drain electrode of the thin film transistor is formed integrally with the data line on the insulating substrate; A source electrode is formed on the insulating substrate, a gate electrode of the thin film transistor is formed integrally with the scanning line, and the pixel electrode is a first contact formed on the insulating protective film. It is characterized by being connected to the source electrode via a hole.

The thin film transistor array having the above structure is manufactured by the following process. Data lines are arranged on the insulating substrate. The drain electrode is formed integrally with the data line on the insulating substrate in the same step as the data line, and at the same time, the source electrode is formed on the insulating substrate. A thin film transistor having the above-described structure is formed on the drain electrode and the source electrode thus formed. Note that the scan line is formed integrally with the gate electrode in the same step as the gate electrode. Note that the above-described second insulating film is also used as an interlayer insulating film between the scanning line and the data line. Next, an insulating protective film is deposited so as to cover the upper surfaces of the insulating substrate, the thin film transistor, the data lines, and the scanning lines. A first contact hole is formed in the insulating protective film to expose a part of the source electrode. A pixel electrode is formed on the upper surface of the insulating protective film corresponding to each area (pixel area) separated by the data lines and the scanning lines. The pixel electrode is connected to the source electrode via a first first contact hole.

In the case of a thin film transistor array having a structure in which such pixel electrodes are arranged on the upper layer side of the thin film transistor, it is possible to increase the aperture ratio of the LCD.
Further, a transparent conductive thin film (for example, IT
O), the data line and the gate line can be connected to form a short ring for preventing static electricity.

In the case where the pixel electrode is arranged on the upper layer side of the thin film transistor, the thin film transistor array is preferably configured as follows. That is, a lower capacitor electrode is formed on the insulating substrate in the same step as the data line, and the pixel electrode is connected to the lower capacitor electrode via a second contact hole formed in the insulating protective film. An auxiliary capacitance is formed between the lower capacitance electrode and the scanning line. In the thin film transistor array having the above structure, the source electrode and the lower capacitance electrode are connected by using the pixel electrode. In this way, by connecting the two electrodes to the pixel electrode which is a transparent conductive thin film, it is possible to increase the aperture ratio of the LCD.

Further, when the pixel electrodes are arranged on the upper layer side of the thin film transistor, preferably, the thin film transistor array is constituted as follows. That is, the data line is formed so that the edge of the pixel electrode overlaps the data line via the insulating protective film, and the data line functions as a black matrix. As a result, it is not necessary to provide a margin for mask alignment accuracy as compared with the case where a black matrix is separately provided conventionally, so that it is possible to further increase the aperture ratio of the LCD.

However, when such a structure is simply used, the coupling capacitance between the pixel electrode and the data line may become excessive due to the overlap between the pixel electrode and the data line. This coupling capacitance causes a problem such as crosstalk on the display of the LCD.

To solve this problem, the thin film transistor array is configured as follows. That is, the shield electrode is arranged above the data line via the above-mentioned second insulating film. Note that the shield electrode is formed integrally with the scanning line in the same step as the scanning line. A pixel electrode is formed so that its edge overlaps the shield electrode via the insulating protective film, so that the shield electrode functions as a black matrix, and an auxiliary capacitor is provided between the shield electrode and the pixel electrode. Is configured.

In this manner, the electric field is shielded by interposing the shield electrode between the pixel electrode and the data line, thereby preventing the potential change of the data line from affecting the pixel potential. In the thin film transistor having the structure of the present invention, this shield electrode can be used also as an auxiliary capacitance line formed in the same step as the scanning line (and thus the gate electrode) or the scanning line itself of the adjacent pixel.
The shield structure can be manufactured without increasing the number of special steps. Note that the formation of the black matrix by wiring is preferably performed by overlapping the edge of the pixel electrode with the shield electrode. In this case, it is preferable not to overlap the pixel electrode above the data line from the viewpoint of yield.

Further, the pixel electrode is made of ITO (Indium Tin).
Oxide), the insulating protective film is preferably made of silicon oxide or silicon oxynitride.
In particular, when the edge of the pixel electrode made of ITO overlaps above the data line, or when ITO overlaps above the shield electrode.
In the case where the edge portions of the pixel electrodes made of are overlapped with each other, high processing accuracy is required for the etching of ITO, and therefore, it is desirable to dry the etching. As a dry etching method of ITO, for example, reactive ion etching using hydrogen iodide (HI) gas, hydrogen bromide (HBr) gas, and hydrogen chloride (HCl) gas is known. Is used, an etching selectivity of only about 3 can be obtained even if the most selective HI gas is used, and the film of silicon nitride is reduced. By using a combination of silicon oxide or silicon oxynitride as a base and using HI as an etching gas, a selectivity of about 10 can be obtained, and a reduction in the thickness of the protective film can be suppressed to a level that does not hinder it.
Dry etching of ITO becomes possible. (Arrangement of Light Shielding Film) Preferably, in the above thin film transistor, a light shielding film made of an amorphous silicon carbide layer is arranged below the thin film transistor. In this case, a third insulating film layer is disposed between the insulating substrate and the amorphous silicon layer, and the light shielding film is provided between the insulating substrate and the third insulating film layer. Alternatively, the light shielding film can be disposed directly between the insulating substrate and the amorphous silicon layer.

Conventionally, the idea of using an amorphous silicon film as a light shielding film has been known. However, an amorphous silicon film has a low electric resistance and, in particular, becomes conductive when irradiated with light. TFTs, such as shift of threshold voltage due to back gate effect due to the influence of charge of light shielding film
The characteristics will be affected. In the present invention, since the silicon carbide film (SiCx) is used as the light shielding layer, the photoconductivity is reduced by two digits or more as compared with the amorphous silicon film, and the light shielding film with high resistance can be obtained. Since the band gap is wider than that of the amorphous silicon film, the light shielding ability is slightly inferior.
An appropriate film can be obtained by adjusting the content of.

In particular, the semiconductor film forming the active layer is composed of two layers, the upper part of which is amorphous silicon, and the lower part is SiC.
x, and using lower SiCx as a light shielding film,
Even if light is applied to the SiCx, the lifetime of the photogenerated carriers is short, so that the leakage current of the TFT can be suppressed to a level that does not cause any problem, and a TFT with high light resistance can be obtained. (Other Manufacturing Method of Thin Film Transistor) Instead of the above-described method of manufacturing a thin film transistor, a source region and a drain region can be formed by the following method.

That is, after the gate electrode, the second insulating film layer, and the first insulating film layer are formed by etching in the same manner as in the above-described manufacturing method, the amorphous silicon layer corresponding to the source region and the drain region is formed. Doping with impurity ions is performed using the gate electrode as a mask. After depositing a metal thin film on the region, heat treatment is performed, and furthermore, the metal thin film is removed by etching, so that part of the amorphous silicon layer is turned into metal silicide to form source and drain regions. You.

In this manufacturing method, a metal silicide is formed on the surface of a portion of the amorphous silicon layer doped with impurity ions to reduce the resistance. Also in this case, the self-aligned T
An FT can be formed, and a sufficient ohmic contact can be obtained at the connection between the source region and the source electrode and between the drain region and the drain electrode. Therefore, it is possible to simultaneously improve the TFT characteristics and reduce the parasitic capacitance, which are problems in the conventional top gate TFT using amorphous silicon as the active layer. In addition, as a metal which forms silicide, Mo,
Ti or W is suitable. Note that, in the case of a thin film transistor according to this manufacturing method, the source electrode and the drain electrode are connected above the source region and the drain region, respectively.

[0038]

Embodiments of the present invention will be described below with reference to the drawings. (Example 1) FIG. 1 is a sectional view showing the structure of a thin film transistor of the present invention. The manufacturing method and structure of the thin film transistor will be described with reference to the cross-sectional view.

An a-Si layer (amorphous silicon layer) having a thickness of 0.1 μm is formed on one main surface of an insulating substrate 11 made of quartz glass (1737 made by Corning) by a plasma CVD method.
Then, while maintaining a vacuum state in the same reaction chamber, a silicon nitride layer 15 (first insulating film) having a thickness of 0.05 μm is continuously deposited by a plasma CVD method. The a-Si layer 12 is patterned into islands by photolithography together with the silicon nitride layer 15 thereon. Next, a thickness of 0.3
A 5 μm silicon nitride layer 16 (second insulating film) is deposited. Further, Al having a thickness of 0.3 μm and Mo having a thickness of 0.1 μm are sequentially laminated, and the gate electrode 17 is formed by patterning by photolithography.

Next, using the same resist pattern as that used for etching the gate electrode 17, the silicon nitride films 16 and 15 are etched to form a gate insulating film, and at the same time, the silicon nitride films 16 and 15 are not covered with the gate electrode 17. The a-Si layer corresponding to the portion is exposed. After the resist pattern is stripped, a-S
The i layer is doped with P (phosphorus). This ion doping is performed by a method in which PH ₃ gas diluted to 5% with H ₂ is plasma-decomposed, and the generated ion species are collectively accelerated by an electric field without performing mass separation, and are implanted into an a-Si layer. Will be If mass separation is not performed in this way, processing on a large-area substrate becomes easy.

Next, XeCl excimer laser is irradiated from above. In addition, for laser irradiation, ArF, K
An excimer laser such as rF or XeF, a YAG laser, an Ar laser, or the like can also be used. Since the gate electrode 17 is used as a mask, only the exposed portion, that is, the a-Si layer in the portion doped with P is crystallized, whereby P is activated and the low-resistance N-type polycrystal is formed. Turns into silicon. As a result, the source region 13 and the drain region 14 are self-aligned with the gate electrode.
Is formed. As described above, the thin film transistor of the present invention is obtained.

The distribution of the thickness of each of the first insulating film 15 and the second insulating film 16 constituting the gate insulating film has an appropriate range. First, the lower limit of the first insulating film is about 5 nm from the viewpoint of TFT characteristics. Also, considering the step of patterning into an island at the same time as the a-Si layer, it is difficult to control the shape if the thickness is too large. On the other hand, the thickness of the second insulating film must be equal to or greater than the total thickness of the a-Si layer and the first insulating film because it is necessary to cover the a-Si layer processed into an island shape and the first insulating film. Is desirable.

As described above, by using Al in which a barrier metal is laminated on the gate electrode, the resistance of the gate electrode wiring (scanning line) can be reduced, and a large LCD can be manufactured.

On Al, a barrier metal (M in this example)
One of the purposes of stacking o) is to block the implantation of hydrogen into the channel region in a subsequent ion doping step. When hydrogen is implanted into the a-Si layer in the channel portion, it causes deterioration of TFT characteristics. Another object is to prevent generation of hillocks in Al in a thermal process such as laser irradiation or deposition of an insulating protective film. Therefore, as the material of the barrier metal, W and Ta having a high melting point and high density are suitable in addition to Mo.
Among them, W has the maximum melting point and density,
Most suitable. The thickness of the barrier metal is suitably in the range of 0.03 to 0.2 μm in consideration of heat resistance performance, ion block performance, and shape controllability at the time of processing a laminated film.

Regarding the order of ion doping and laser irradiation, when laser irradiation is performed after ion doping as in the above example, the activation rate of ions increases,
On the other hand, when ion doping is performed after laser irradiation, a-Si is less likely to be melted during laser irradiation. Therefore, considering the process window in mass production, it can be said that the latter is preferable, but in the latter case, the accelerating voltage is set so that the polycrystallized source and drain regions are not re-amorphized by ion doping. In addition, it is necessary to adjust the dose. (Example 2) FIG. 2 is a cross-sectional view showing an example in which a source electrode and a drain electrode are connected to a thin film transistor having the above structure (FIG. 1).

In FIG. 2, first, a Mo—W (molybdenum-tungsten) alloy is formed on one main surface of the glass substrate 11 by lamination and patterned by photolithography to form a source electrode 18 and a drain electrode 19. I do. The interval between these two electrodes is formed to be wider than the width (gate length) of the gate electrode 17 formed in the subsequent step and narrower than the width of the island-shaped a-Si layer formed in the subsequent step. . A thin film transistor is formed thereon according to the above-described manufacturing method. When ion doping and laser irradiation are performed on the a-Si layer using the gate electrode 17 as a mask to form the source region 13 and the drain region 14 of the thin film transistor, the low resistance forming the source region 13 and the drain region 14 is simultaneously formed. Of the polycrystalline silicon layer,
It is connected to the source electrode 18 and the drain electrode 19 arranged below.

As described above, the source and drain electrodes 18,
In the case where 19 is connected to the lower layer of the source and drain regions 13 and 14, the dopant (P in this example) is
Since it is necessary to drive deeply in the thickness direction of the a-Si layer,
The acceleration voltage at the time of ion doping is 50 to 80.
kV is appropriate. Example 3 FIG. 3 shows an example of a TFT array (thin film transistor array) using the thin film transistor of the present invention (FIG. 2) as a switching element. (A) is a plan view,
(B) is an AA section view.

As shown in FIG. 3, ITO is deposited on one main surface of the glass substrate 11, a Mo-W alloy is deposited thereon, and then patterned by photolithography to form a drain electrode 19 and a drain electrode. One data line 41,
And the pixel electrode 32 is formed. The drain electrode 19
The data line 41 is formed on the ITO layer, and the upper surface of the pixel electrode 32 is covered with the Mo-W alloy layer at this stage. A thin film transistor is formed thereon according to the above-described manufacturing method. The scanning line 42 is formed integrally with the gate electrode 17 simultaneously with the gate electrode 17. Next, the whole is covered with an insulating protective film 31 (for example, silicon nitride), and is patterned by photolithography.
The insulating protective film on the upper surface of the substrate 2 is removed except for the edge of the pixel electrode and the upper part of the source electrode 18. Next, the pixel electrode 32
The Mo-W film on the edge 18a and the source electrode 1
Except for 8, it is removed by etching.

As described above, the TFT array shown in FIG. 3 is obtained. The number of photolithography masks in the above process is four in total. (Example 4) FIG. 4 shows another example (cross-sectional view) of a TFT array using the thin film transistor of the present invention (FIG. 2) as a switching element.

In this example, first, a thin film transistor is formed on one main surface of the glass substrate 11 according to the above-described manufacturing method. The data line is formed integrally with the drain electrode at the same time as the drain electrode 19, and the scanning line is formed as the gate electrode 1
7 and simultaneously with the gate electrode. Next, the whole is covered with an insulating protective film 21 made of silicon nitride, patterned by photolithography to provide a contact hole 43 (first contact hole), and a part of the surface of the source electrode 18 of the thin film transistor is exposed. After depositing ITO thereon by sputtering, the ITO is patterned to form a pixel electrode 22. The pixel electrode 22 is connected to the source electrode 18 via a contact hole 43 provided in the insulating protective film 21.

In the TFT array having the above-described structure, the data lines, the scanning lines, and the pixel electrodes 22 are arranged on different layers via the second insulating film 16 or the insulating protective film 21. Therefore, the probability of short-circuiting with each other is reduced, and the distance between the data line and the pixel electrode and the distance between the scanning line and the pixel electrode can be reduced. Therefore, an LCD having a large aperture ratio can be manufactured with a high yield. The number of photolithography masks in the above manufacturing process is five in total. Example 5 FIG. 5 shows another example of a TFT array using the thin film transistor of the present invention (FIG. 2) as a switching element. (A) is a plan view, (b) is a BB section sectional view.

In this example, the lower capacitance electrode 51 is arranged below the scanning line 42 so as to face the scanning line 42 with the above-mentioned second insulating film interposed therebetween. Other structures are the same as those of the TFT array shown in FIG.

In FIG. 5, the lower capacitance electrode 51 forming the auxiliary capacitance is formed in the same step as the data line 41, the drain electrode 19 and the source electrode 18. Further, the scanning lines 42 of the adjacent pixels function as upper capacitance electrodes.

Insulating protective film 21 covering thin film transistor
Are provided with two openings for each pixel, that is, a first contact hole 43 and a second contact hole 53. The source electrode 18 and the pixel electrode 22 are connected to each other through the first contact hole 43. Are connected, and the pixel electrode 22 and the lower capacitance electrode 51 are connected via the second contact hole 53.

Further, the edge of the pixel electrode 22 is
2 are arranged so as to overlap with each other with the insulating protective film 21 interposed therebetween, and the data line 42 functions as a black matrix. By adopting such a structure, it is not necessary to provide a dedicated black matrix on the data line side, and it is possible to make an effective display area up to the boundary of the data line. Can be greatly increased. Example 6 FIG. 6 shows another example (plan view) of a TFT array using the thin film transistor of the present invention (FIG. 2) as a switching element.

In this example, the shield electrode 56 is disposed above the data line 41 so as to face the data line 41 via the second insulating film 16 (FIG. 5). The shield electrode 56 has an edge portion of the pixel electrode 22 via the insulating protective film 21 (FIG. 5).
6 so as to overlap. This shield electrode 5
6 is formed simultaneously with the scanning line 41 and integrally with the scanning line. Other structures are the same as those of the TFT array shown in FIG.

In this example, the shield electrode 56 functions as an upper capacitance electrode forming an auxiliary capacitance, and since the shield electrode 56 is arranged so as to overlap the edge of the pixel electrode 22, it can be used as a black matrix. It is functioning. Further, since the shield electrode 56 has a shielding effect and prevents the potential fluctuation of the data line 41 from affecting the pixel electrode 22, the data line 41 and the pixel electrode 2
2 to prevent the display performance from deteriorating due to the coupling with
An LCD with a high aperture ratio can be obtained.

In this example, the insulating protective film 21
Is made of silicon oxide, and the pixel electrode 22 is
It is formed by dry etching ITO using HI. Example 7 FIG. 7 shows an example in which a light shielding layer is provided on the thin film transistor of the present invention (FIG. 2).

In this example, a third insulating film 62 is disposed on the glass substrate 11, a thin film transistor is disposed thereon, and an optical signal is disposed below the thin film transistor via the third insulating film 62. A shielding layer 61 is provided.

The light shielding layer 61 is made of amorphous silicon carbide (S
iCx) and, like the a-Si layer, the plasma CV
Deposited by D method. The source gas is SiH
Generally, a mixed gas of ₄ , CH ₄ and H ₂ is used. By adjusting the flow rates of CH ₄ and SiH ₄ ,
The C / Si composition ratio in SiCx is adjusted. Even if a small amount of C is added, the photoconductivity of the SiCx layer is reduced. Therefore, the band gap of SiCx is adjusted to be higher by about 0.05 to 0.20 eV than the band gap of a-Si. Specifically, the band gap of a-Si is set to 1.75.
Assuming eV, the band gap of SiCx is 1.80 to
It is good to make it about 1.95 eV. The C / S composition ratio in SiCx is about 1 to 10 at%. SiCx is processed into an island shape so as to block the light leak path of the thin film transistor, and the surface thereof is covered with an insulating film made of, for example, silicon nitride or silicon oxide. (Example 8) FIG. 8 shows another example in which a light shielding layer is provided on the thin film transistor of the present invention (FIG. 2).

In this example, a light shielding layer 63 made of amorphous silicon carbide (SiCx) is formed on a glass substrate 11, and a thin film transistor is directly formed thereon. That is, the semiconductor active layer has a two-layer structure of SiCx and a-Si, the lower side of which functions as a light shielding layer 63, and the channel 12, the source 13, and the drain of the thin film transistor are formed in the upper a-Si layer. 14 are formed.

Preferably, in order to obtain a clean interface between the SiCx layer and the a-Si layer, these layers are continuously deposited by plasma CVD while maintaining a vacuum state. Specifically, while the plasma discharge is maintained, the SiCx layer and the a-Si layer are continuously deposited only by switching the source gas (for example, turning on / off the CH ₄ gas). S
The composition of iCx is the same as the example (Example 7) shown earlier.

In the case of such a structure in which the a-Si layer is laminated on the SiCx layer, as the a-Si layer becomes thinner,
The light leakage current of the TFT decreases, but if it is too thin, Si
The bending of the band is affected by the defect level of the Cx layer, and TF
The mobility of T decreases. Therefore, the thickness of the a-Si layer
The thickness is 10 nm to 50 nm, preferably 15 nm to 30 nm. (Example 9) FIG. 9 is a sectional view of a transmission light type liquid crystal display device using the thin film transistor array (FIG. 4) of the present invention.

The opposing substrate is a glass substrate 76, an opposing electrode 7
5. It is composed of an alignment film 74, a polarizing plate 77 and the like. A counter electrode 75 made of ITO is provided on the inner side of the glass substrate 76.
Is formed, and the surface of the counter electrode 75 is covered with an alignment film 74 made of low-temperature curing type polyimide.
A polarizing plate 77 is attached to the outer surface side of 6.

On the other hand, the array substrate includes the thin film transistor array of the present invention (including the glass substrate 11, the gate electrode 17, the source electrode 18, the drain electrode 19, the pixel electrode 22, etc.), the alignment film 72, the polarizing plate 71 and the like. You. The surface of the pixel electrode 22 is covered with an alignment film 72 made of a low-temperature curing type polyimide, and a polarizing plate 71 is attached to the outer surface of the glass substrate 11.

The array substrate and the opposing substrate are arranged so as to oppose each other, and a liquid crystal 73 is held between them. Each of the alignment films 72 and 74 is subjected to an alignment process so that the alignment directions are orthogonal to each other.

As the insulating protective film 21 disposed below the pixel electrode 22, a transparent organic insulating film is used. As described above, the coupling capacitance between the data line 41 (FIG. 5A) and the pixel electrode 22 degrades the display characteristics of the liquid crystal display element, so it is necessary to suppress the coupling capacitance. Therefore, it is desirable to apply a transparent organic insulating film having a dielectric constant of 4 or less to a thickness of 1 μm or more. Specifically, an acrylic resin, a polyimide resin, a benzocyclobutene resin, or the like can be used, and if there is photosensitivity such as a photoresist, processing is easy. Preferably, an inorganic insulating film such as silicon nitride is further laminated on these organic insulating films in order to improve the protection function of the TFT.

The organic protective film can be colored to form a color filter. In this case, a color filter function can be built into the array substrate,
This is advantageous when manufacturing a high aperture ratio LCD at low cost.

These inventions can be applied not only to the active matrix type liquid crystal display device but also to a-Si contact sensors and the like. (Example 10) FIG. 10 is a sectional view showing a second structure of the thin film transistor of the present invention. The manufacturing method and structure of the thin film transistor will be described with reference to the cross-sectional view.

An a-Si layer (amorphous silicon layer) having a thickness of 0.1 μm is formed on one main surface of an insulating substrate 11 made of quartz glass (1737 made by Corning) by a plasma CVD method.
Then, while maintaining a vacuum state in the same reaction chamber, a silicon nitride layer 15 (first insulating film) having a thickness of 0.05 μm is continuously deposited by a plasma CVD method. The a-Si layer 12 is patterned into islands by photolithography together with the silicon nitride layer 15 thereon. Next, a thickness of 0.35
A μm silicon nitride layer 16 (second insulating film) is deposited. Al having a thickness of 0.3 μm and Mo having a thickness of 0.1 μm are sequentially laminated, and the gate electrode 17 is formed by patterning by photolithography.

Next, using the same resist pattern as that used for etching the gate electrode 17, the silicon nitride films 16 and 15 are etched to form a gate insulating film, and at the same time, the silicon nitride films 16 and 15 are not covered with the gate electrode 17. The a-Si layer corresponding to the portion is exposed. After removing the resist pattern, using the gate electrode 17 as a mask, a
Doping the Si layer with P;

Next, Mo is sputtered on the exposed a-Si layer, and the a-Si layer and the M
Mo silicide is formed at the interface with the o layer. Thereafter, when the Mo layer is removed by wet etching, a-S
Mo silicide remains on the surface layer of the i-layer. As a result, the source region 13 and the drain region 14 are formed so as to be self-aligned with the gate electrode. As described above, the thin film transistor of the present invention is obtained. (Example 11) FIG. 11 shows a thin film transistor having the above structure (FIG. 10) in which a source electrode 88 and a drain electrode 89 are provided.
FIG. 6 is a cross-sectional view showing an example of connecting the two.

The connection between the source electrode 88 and the drain electrode 89 is performed simultaneously with the formation of the source region 85 and the drain region 86 in the last stage of the process of forming a thin film transistor on the glass substrate 11. That is, Mo is sputtered on the exposed a-Si layer, and Mo silicide is formed at the interface between the a-Si layer and the Mo layer by a heat treatment at 250 ° C. Next, the source electrode 88 and the drain electrode 89 are formed by patterning the Mo layer by wet etching. The distance between these two electrodes is larger than the width of the gate electrode 17 already formed, and the a-Si island 1
It is formed narrower than 2. As a result, the source region 85 and the drain region 86 are formed so as to be self-aligned with the gate electrode 17, and at the same time, the source electrode 88 and the drain electrode 89 are formed.

[0074]

According to the structure and the manufacturing method of the thin film transistor of the present invention, the gate insulating film is composed of two layers of the first and second insulating films. A first insulating film is deposited on an amorphous silicon layer which is a semiconductor active layer, and the amorphous silicon layer is processed into an island shape at the same time as the first insulating film. Cover with. By adopting such a process, a patterning process is not interposed between the deposition of the amorphous silicon layer and the deposition of the first insulating film (gate insulating film). An insulating film can be continuously deposited by a plasma CVD method while maintaining a vacuum state in the same reaction chamber. As a result, it is easy to obtain a clean interface between the amorphous silicon layer and the gate insulating film, and the mobility, reliability, and the like of the thin film transistor can be improved.

The source and drain regions formed in a self-aligned manner using the gate electrode as a mask are sufficiently activated by doping elements by polycrystallization by laser irradiation. N +
The electric resistance is smaller than that of a-Si (n-type amorphous silicon), and a sufficient ohmic contact can be formed between the source and drain regions and the source and drain electrodes. As a result, it is possible to simultaneously improve the TFT characteristics and reduce the parasitic capacitance, which are problems in the conventional TFT having a dop gate structure using amorphous silicon for the active layer. Before the ion doping, the gate insulating film is etched in the same pattern as the gate electrode in advance to expose the surface of the amorphous silicon layer, so that the ion to the amorphous silicon layer can be formed even at a low acceleration voltage. Doping becomes possible.

According to the method of manufacturing a thin film transistor of the present invention, the number of masks used during the manufacturing process is 4 to 5 when the light shielding layer is not provided, and 5 to 6 when the light shielding layer is provided. It is possible to manufacture a thin film transistor in a smaller number of steps than in a conventional manufacturing method. As described above, according to the method for manufacturing a thin film transistor of the present invention, a large LCD can be manufactured at low cost.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a thin film transistor of the present invention.

FIG. 2 is a cross-sectional view illustrating a structure of a thin film transistor of the present invention.

3A and 3B show a structure of a thin film transistor array of the present invention, FIG. 3A is a plan view, and FIG.

FIG. 4 is a cross-sectional view illustrating a structure of a thin film transistor array of the present invention.

5A and 5B show a structure of a thin film transistor array of the present invention, FIG. 5A is a plan view, and FIG. 5B is a sectional view taken along the line BB.

FIG. 6 is a plan view showing a structure of a thin film transistor array of the present invention.

FIG. 7 is a cross-sectional view illustrating a structure of a thin film transistor of the present invention.

FIG. 8 is a cross-sectional view illustrating a structure of a thin film transistor of the present invention.

FIG. 9 is a cross-sectional view of a liquid crystal display device using the thin film transistor array of the present invention.

FIG. 10 is a sectional view showing a second structure of the thin film transistor of the present invention.

FIG. 11 is a sectional view showing a second structure of the thin film transistor of the present invention.

[Explanation of symbols]

11: glass substrate, 12: channel region, 13
... source region, 14 ... drain region, 15 ...
A first insulating film (gate insulating film), 16: a second insulating film (gate insulating film), 17: a gate electrode, 18.
..Source electrode, 19 ... Drain electrode, 21 ...
Insulating protective film, 22: pixel electrode, 31: insulating protective film, 32: pixel electrode, 41: data line, 4
2 ... scanning line, 43 ... first contact hole,
51: Lower capacitance electrode, 53: Second contact hole, 56: Shield electrode, 61: Light shielding film, 62: Third insulating film, 63: Light shielding film , 7
DESCRIPTION OF SYMBOLS 1 ... Polarizer, 72 ... Alignment film, 73 ... Liquid crystal,
74: alignment film; 75: counter electrode; 76: glass substrate; 77: polarizing plate.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 29/78 616V 627G

Claims (22)

[Claims] A first insulating film is formed on an insulating substrate by depositing an amorphous silicon layer by a plasma CVD method. Depositing the first insulating film by plasma CVD, processing the first insulating film into an island shape together with the amorphous silicon layer thereunder, and forming the first insulating film on the island-processed first insulating film. Depositing a second insulating film, depositing a metal wiring layer on the second insulating film, etching the metal wiring layer using a resist pattern to form a gate electrode. Forming a gate insulating film by etching the second insulating film and the first insulating film using the resist pattern; and forming a portion of the amorphous silicon layer exposed in the preceding etching process. Using the gate electrode as a mask , And performing doping with impurity ions using the gate electrode as a mask, a method of manufacturing the thin film transistor, characterized in that the portion and a step of polycrystalline by laser irradiation. 2. The method according to claim 1, wherein both the first insulating film and the second insulating film are made of silicon nitride. 3. A mixed gas mainly composed of CHF ₃ and O ₂ or a mixed gas mainly composed of CF ₄ and H ₂ is used for etching the second insulating film and the first insulating film. 3. The method according to claim 2, wherein the reactive ion etching method is used. 4. An amorphous silicon layer formed in an island shape on an insulating substrate, and a first insulating film formed in a band shape with a width corresponding to a gate length on the amorphous silicon layer. A thin film transistor comprising: a second insulating film formed with the width on a first insulating film; and a gate electrode formed with the width on a second insulating film, A channel region of the thin film transistor is formed of a region corresponding to a portion of the amorphous silicon layer covered with the gate electrode, and a source region and a drain region of the thin film transistor are formed using impurities using the gate electrode as a mask. A thin film transistor formed by polycrystallizing a part of the amorphous silicon layer by ion doping and subsequent laser irradiation. 5. The semiconductor device according to claim 1, wherein a source electrode is arranged between the source region of the thin film transistor and the insulating substrate, and a drain electrode is arranged between the drain region of the thin film transistor and the insulating substrate. The thin film transistor according to claim 4. 6. The semiconductor device according to claim 1, wherein the source electrode and the drain electrode
The thin film transistor according to claim 5, comprising an oW alloy or a MoTa alloy. 7. A thin film transistor array using the thin film transistor according to claim 5 as a switching element, wherein the pixel electrodes are two-dimensionally arranged on an insulating substrate and arranged between pixel electrodes adjacent to each other. And a scanning line that intersects with the data line and is arranged on the upper layer side of the data line via the second insulating film. The source electrode of the thin film transistor is connected to the upper surface of the pixel electrode. Wherein a drain electrode of the thin film transistor is formed integrally with the data line, a gate electrode of the thin film transistor is formed integrally with the scan line, and upper surfaces of the thin film transistor, the data line and the scan line are A thin film transistor array covered with an insulating protective film. 8. A thin film transistor array using the thin film transistor according to claim 5 as a switching element, comprising: a data line arranged on an insulating substrate; Scanning lines arranged on the upper layer side of the data lines, an insulating substrate, an insulating protective film deposited so as to cover the upper surfaces of the data lines and the scanning lines, and a data line and an upper surface of the insulating protective film. A pixel electrode arranged in a portion corresponding to each area divided by a scanning line, wherein a drain electrode of the thin film transistor is formed integrally with the data line on the insulating substrate; and a source electrode of the thin film transistor Is formed on the insulating substrate, the gate electrode of the thin film transistor is formed integrally with the scanning line, and the pixel electrode is formed on the insulating protective film. Thin-film transistor array first through one of the contact hole, characterized in that it is connected to the source electrode. 9. A semiconductor device comprising: a lower capacitor electrode formed on the insulating substrate in the same step as the data line; and the pixel electrode is connected via a second contact hole formed in the insulating protective film. 9. The thin film transistor array according to claim 8, wherein an auxiliary capacitance is connected between the lower capacitance electrode and the scanning line. 10. The data line, wherein an edge of the pixel electrode is formed so as to overlap the data line via the insulating protective film, and the data line functions as a black matrix. Item 9. A thin film transistor array according to item 8. 11. A shield electrode integrally formed with the scan electrode is disposed on an upper layer side of the data line with the second insulating film interposed therebetween, and the shield electrode is provided at an edge of the pixel electrode. Is formed so as to overlap with the shield electrode via the insulating protective film, the shield electrode functions as a black matrix, and an auxiliary capacitance is formed between the shield electrode and the pixel electrode. 9. The thin film transistor array according to claim 8, wherein: 12. The thin film transistor array according to claim 8, wherein the insulating protective film is made of silicon oxide or silicon oxynitride, and the pixel electrode is made of ITO. 13. A third insulating film layer is disposed between the insulating substrate and the amorphous silicon layer, and a third insulating film layer is provided below the amorphous silicon layer via the third insulating film layer. 5. The thin film transistor according to claim 4, further comprising a light shielding film made of an amorphous silicon carbide layer. 14. The thin film transistor according to claim 4, wherein a light shielding film made of an amorphous silicon carbide layer is disposed between the insulating substrate and the amorphous silicon layer. 15. An array substrate provided with the thin film transistor array according to claim 8, a counter substrate disposed to face the array substrate, and a liquid crystal layer held between the array substrate and the counter substrate. Liquid crystal display. 16. A first insulating film, comprising: a step of depositing an amorphous silicon layer on an insulating substrate by a plasma CVD method; Depositing the first insulating film by plasma CVD, processing the first insulating film into an island shape together with the amorphous silicon layer thereunder, and forming the first insulating film on the island-processed first insulating film. Depositing a second insulating film, depositing a metal wiring layer on the second insulating film, etching the metal wiring layer using a resist pattern to form a gate electrode. Forming a gate insulating film by etching the second insulating film and the first insulating film using the resist pattern; and forming a portion of the amorphous silicon layer exposed in the preceding etching process. , Using gate electrode as mask Doping with impurity ions, depositing a metal thin film on the portion, heat-treating the metal thin film, etching the metal thin film to form a portion of the amorphous silicon layer with a metal. And a step of silicidation. 17. The method according to claim 16, wherein both the first insulating film and the second insulating film are made of silicon nitride. 18. A mixed gas mainly composed of CHF ₃ and O ₂ or a mixed gas mainly composed of CF ₄ and H ₂ is used for etching the second insulating film and the first insulating film. 18. The method according to claim 17, wherein the reactive ion etching method is used. 19. An amorphous silicon layer formed in an island shape on an insulating substrate, and a first insulating film formed in a band shape with a width corresponding to a gate length on the amorphous silicon layer. And a second insulating film formed with the width on the first insulating film; and a gate electrode formed with the width on the second insulating film, A channel region of the thin film transistor is formed by a region corresponding to a portion of the amorphous silicon layer covered with the gate electrode, and a source region and a drain region of the thin film transistor use the gate electrode as a mask. The amorphous silicon layer is formed by metal silicidation of a part of the amorphous silicon layer by doping of impurity ions and subsequent deposition, heat treatment and etching of a metal thin film. Thin film transistor. 20. The thin film transistor according to claim 19, wherein a source electrode is connected to an upper surface of a source region of the thin film transistor, and a drain electrode is connected to an upper surface of a drain region of the thin film transistor. 21. A third insulating film is arranged between the insulating substrate and the amorphous silicon layer, and below the amorphous silicon layer via the third insulating film. 20. The thin film transistor according to claim 19, wherein a light shielding film made of an amorphous silicon carbide layer is provided. 22. The thin film transistor according to claim 19, wherein a light shielding film made of an amorphous silicon carbide layer is disposed between the insulating substrate and the amorphous silicon layer.