JP2585505B2 - Conduction modulation type MOSFET - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a conduction modulation type MOSFET.

[Technical background of the invention and its problems]

The conductivity modulation type MOSFET is obtained by changing the drain region of a normal power MOSFET to the conductivity type opposite to that of the source region. FIG. 7 shows the structure of a conventional conduction modulation type MOSFET. 41 p ⁺ drain layer, 42 the n ^- is the type high-resistance layer, the p-type base diffusion layer 43 on the surface of the high resistance layer 42 is formed, further n ⁺ -type source to the p-type base diffusion layer 43 A diffusion layer 44 is formed. Then, a portion of the p-type base layer 43 sandwiched between the source diffusion layer 44 and the high resistance layer 42 exposed on the surface is formed into a channel region 49.
As a gate electrode 46 over the gate insulating film 45.
Are formed, and a source electrode 47 that contacts both the source diffusion layer 44 and the base diffusion layer 43 is formed. On the surface of the drain layer 41, a drain electrode 48 is formed.

In this conduction modulation type MOSFET, when a positive voltage is applied to the gate electrode 46 and to the source electrode 47, an inversion layer is formed in the channel region 49, and electrons from the source diffusion layer 44 pass through the channel region 49 and n ⁻ Is injected into the mold high-resistance layer 42. The injected electrons diffuse through the high-resistance layer 42 and escape to the drain electrode 48. At this time, holes are injected from the drain layer 41. Due to the injection of holes, conductivity modulation due to accumulation of carriers occurs in the high-resistance layer 42, and the resistance of the high-resistance layer 42 decreases. As a result, a MOSFET having a lower on-resistance than a normal power MOSFET can be obtained.

Incidentally, in such a conduction modulation type MOSFET, the four layers of the p ⁺ -type drain layer 41-n ^-- type high resistance layer 42-p-type base diffusion layer 43-n ⁺ -type source diffusion layer 44 constitute a thyristor. When the parasitic thyristor conducts, the element cannot be turned off even if the gate-source voltage is reduced to zero, which often leads to element destruction. The reason that the parasitic thyristor is turned on is that holes injected from the p ⁺ -type drain layer 41 pass through the p-type base diffusion layer 43 when they escape to the source electrode 47. That is, such a hole current flows, and the base diffusion layer 43
If the voltage drop due to the resistor immediately below the gate exceeds the built-in voltage between the base and the source, electrons are injected from the source layer 44, and the parasitic thyristor is turned on.

In order to prevent such a parasitic thyristor latching phenomenon, a high-concentration p ⁺ -type base diffusion layer 50 is formed in the p-type base diffusion layer 43 as shown in FIG. 8 to reduce the resistance of the p-type base diffusion layer. That is being done. However, even in this case, there is a problem that the conventional conductive modulation type MOSFET can turn off only a current of at most about 200 A / cm ² . As a result of pursuing the fundamental reason, it became clear that the conventional conduction modulation type MOSFET uses the same source and gate pattern as a normal power MOSFET. This will be described in detail below.

FIG. 9 shows a diffusion layer pattern of the conduction modulation type MOSFET shown in FIG. As shown in the figure, a plurality of p-type base diffusion layers 43 are diffused and formed in a hexagonal shape, and have a pattern in which a channel region 49 is formed in each peripheral portion. Such a pattern is effective for a power MOSFET in terms of increasing the gate area and decreasing the on-resistance. However, in the conductive modulation type MOSFET which requires that the parasitic thyristor not be turned on, such a pattern has the following disadvantages.

First, in order to prevent the parasitic thyristor operation, that is, to prevent latch-up, it is desirable that the resistance from the channel region 49 to the opening of the p ⁺ -type base diffusion layer 50 be as small as possible. However, in the pattern of FIG. 9, the contact with the source electrode of the p ⁺ -type base diffusion layer 50 is formed at the center of the p-type base diffusion layer 43, and its peripheral length is around the p-type base diffusion layer 43. It is smaller than the length of a certain channel region 49, and because of its spreading resistance, the channel region 49 and p ⁺
The resistance between the mold base diffusion layer 50 and the contact with the source electrode cannot be sufficiently reduced. For this reason, latch-up could not be effectively prevented.

Second, in the pattern of FIG. 9, the thyristor indicates that the width L _{G of the} opening of the n ⁻ -type high resistance layer 42 exposed on the surface of the substrate wafer, that is, the approximate width of the portion where the gate electrode is provided, is large. Research by the present inventors has revealed that the operation is facilitated.

The drain current at the time of latching of the parasitic thyristor is inversely proportional to L _G are shown as follows. Since a substantially uniform current flows under the gate insulating film which flows into the p-type base layer, the next current I _P flowing in under the gate insulating film of the horizontal width of the unit length of the channel region 49.

_{I P = S G · J P} / T ...... (1) where J _P is the hole current density, S _G is per unit area n ^-
The area of the opening of the type high resistance layer, T is the perimeter of the p-type base diffusion layer per unit area. Flows the current to the base diffusion layer below the source diffusion layer, the voltage drop due to the resistance R _B under the source diffusion layer is higher than the built-in voltage Vbi between the base and source, the parasitic thyristor is turned on. Denoting this formula, the _{Vbi = I P · R B /} T = S G · J P · R B / T ...... (2). However R _B is the resistance of the channel of the p-type base layer per peripheral length of the unit to the p ⁺ contact. Solving this for J _P gives J _P = Vbi · T / (S _G · R _B ) (3) At the time of turn-off, the channel inversion layer disappears,
Since the current becomes almost a hole current, the latching current density J
_L is expressed by J _L = Vbi · T / (S _G · R _B ) (4) S _G / T is next outline L _G, J _L will be inversely proportional to L _G. This is based on the experimental data of the present inventors.
This is clear from FIG.

On the other hand, for example, as shown in the perspective view of FIG. 10, when the gate electrode 46 and the polycrystalline silicon film 46 ₁ and the Al film 46 ₂ of the laminated structure, when the 30μm width of the Al film 46 _2, polycrystalline silicon the width of film 46 ₁ is required 50-60. That, n ^- 50-60 required as the width L _G of the opening of the -type high resistance layer 42. In this case, as can be seen from FIG. 11, the latch-up current density J _L becomes low.

The above is the reason why latch-up of the conventional conduction modulation type MOSFET cannot be effectively prevented.

[Object of the invention]

As described above, the conventional conduction modulation type MOSFET has a problem that latch-up cannot be effectively prevented.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a conductive modulation type MOSFET in which latch-up hardly occurs.

[Summary of the Invention]

To achieve the above object, a conductive modulation type MOSFET of the present invention
A semiconductor substrate wafer having a high-concentration, first-conductivity-type drain layer and a second-conductivity-type high-resistance layer; a first-conductivity-type base layer formed in the high-resistance layer portion; A high-concentration, second-conductivity-type source layer formed at
A gate electrode formed on the base layer serving as a channel region interposed between the source layer and the high-resistance layer via a gate insulating film; a source electrode contacting both the source layer and the base layer; A conductive modulation type MOSF having a drain electrode contacting the drain layer
In the ET, an opening portion of the high-resistance layer exposed on the wafer surface has a plurality of islands completely surrounded by the base layer.

〔The invention's effect〕

According to the present invention, the portion of the high-resistance layer exposed on the wafer surface surrounds the base diffusion layer, and the portion of the high-resistance layer exposed on the wafer surface is surrounded by the base diffusion layer, thereby forming a plurality of islands. Is adopted.

When such a pattern is employed, the resistance of the base layer under the channel region becomes smaller than in the conventional case, so that the current density at which the latch-up occurs increases, and the latch-up can be effectively prevented.

(Example of the invention)

 Hereinafter, embodiments will be described with reference to the drawings.

FIG. 1 is a plan view of a conductive modulation type MOSFET showing an embodiment of the present invention.

An n ^-- type high resistance layer (not shown) is provided on the p ⁺ -type drain layer (not shown), and a p-type base diffusion layer 13 is formed on the surface of the n ^-- type high resistance layer. An n ⁺ type source diffusion layer 14 is formed therein. Then, the n ⁺ type source diffusion layer 14
A gate electrode 17 made of a polycrystalline silicon film is formed on a channel region 21 between the substrate and the opening of the wafer surface of the n ⁻ -type high resistance layer via a gate insulating film (not shown). A source electrode 18 that contacts both the source diffusion layer 14 and the base diffusion layer 13 is provided, and a drain electrode (not shown) is provided on a drain layer on the back surface of the wafer. The polycrystalline silicon film gate electrode 17 is continuously disposed on the entire surface of the substrate wafer so as to cover the channel region 21 and the rectangular opening of the high resistance layer, and a stripe-shaped Al is formed on a portion where the source electrode 18 does not run. Gate electrodes 20 are arranged. A high-concentration p ⁺ -type base diffusion layer (not shown) is formed under the Al electrode 20 overlying the polycrystalline silicon film gate electrode 17, and the p-type base diffusion layer 13 and the p ⁺ -type base diffusion layer Surrounds the rectangular opening of the n ^- type high resistance layer.

Here, FIG. 2 is a schematic plan view showing a characteristic portion of the present invention that is not visible in FIG. 1, that is, a rectangular opening of the n ⁻ -type high-resistance layer, which has a plurality of islands. 3 to 5 are sectional views taken along line AA 'of FIG.
It is a sectional view taken along the line -B 'and CC'. 1 and FIGS. 3 to 5 have slightly different element structures.

An n ⁻ -type high-resistance layer 12 is provided on the p ⁺ -type drain layer 11, a p-type base diffusion layer 13 is formed on the surface of the high-resistance layer 12, and an n ⁺ -type source diffusion layer 4 are formed. A high concentration p ⁺ -type base diffusion layer 15 is formed in the p-type base diffusion layer 13. A channel region 21 is formed between the source diffusion layer 14 and the opening on the wafer surface of the high-resistance layer 12.
On this, a gate electrode 17 of a polycrystalline silicon film is formed via a gate insulating film 16. A source electrode 18 that contacts both the source diffusion layer 14 and the base diffusion layer 15 is provided, and a drain electrode 19 is provided on the drain layer 11 on the back surface of the wafer. Further, the p ⁺ -type base layer 15 is formed also in the portion as shown in FIGS.

Features of these embodiments, the first, first view a portion of the high-resistance layer 12 which opens under the gate electrode 17, a plurality matrix in sequence as substantially rectangular represented by the width L _G in Figure 2 And
That is, the channel region 21 is formed at least along the long side. The reason for using the rectangle is that the n ^- type high resistance layer
This is because the width of the channel region 21 can be maximized when the islands 12 are formed. A second feature is that such a plurality of rectangular openings are completely surrounded by the base diffusion layer so as to form an island shape.

Note that the actual element structure is, for example, p ⁺
Using a silicon substrate as a starting substrate, a wafer on which an n ⁻ -type high resistance layer 12 is epitaxially grown is used, and impurity diffusion and electrode formation are sequentially performed on the wafer. Of course, the n ^- type high resistance layer 12 may be used as a starting substrate.

As is apparent from these examples, the entire width of the channel region 21 around the rectangular high-resistance layer 12 opening below the gate electrode 17 and the area around the opening of the base diffusion layer in contact with the source electrode 18. It is almost equal to length. For this reason,
Since there is no spreading resistance as compared with the conventional structure as shown in FIG. 9, the resistance of the base diffusion layer under the source diffusion layer 14 is small.
In each of FIGS. 1 to 5, only the gate electrode 17 of the polycrystalline silicon film is present above the portion where the high-resistance layer 12 is opened on the wafer surface, and there is no Al gate electrode. L _G can be made sufficiently small. The L _G is inversely proportional to the current density latching as previously described. In an actual prototype, L _G = 15 μm. Therefore, according to these embodiments, it is possible to prevent the latch-up phenomenon more effectively than before, and the current density of the latch-up is 750 A / cm ²
Has been obtained. Also it was possible to turn off the current to 150A as full operating area 20 mm ^2.

The present invention is not limited to the above embodiment. For example, the shape of the high resistance layer portion exposed on the wafer surface is not necessarily rectangular. In the embodiment in which the arrangement of the p ⁺ -type base diffusion layer for making contact with the source electrode and the n ^-- type high resistance layer opening under the gate electrode is reversed in accordance with the conventional pattern of FIG. The pattern is shown in FIG. In FIG. 6, parts corresponding to those in FIGS. 1 to 5 are denoted by the same reference numerals. If such a pattern is used, the effect of the present invention can be easily explained in comparison with FIG. Now, the width Ln of the source diffusion layer 14 is the same as in FIG.
And the width T (perimeter) is also the same as in FIG. In the case of FIG. 6, the current path of the hole current flowing from the high-resistance layer 12 under the gate electrode to the p ⁺ -type base diffusion layer 15 through below the channel region 21 is opposite to the conventional one in FIG. .
Accordingly, the base resistance under the channel region to the contact portion between the source electrode of the p ⁺ -type base diffusion layer of the high-resistance layer openings of the same peripheral length, p ⁺ -type base diffusion layer channel as FIG. 9 It is clearly smaller than in the center when surrounded by the area. As a result, the pattern of the present invention is less likely to latch up than in the past.

Further, the island-like high resistance layer portion may have a shape similar to a rectangle having at least two parallel sides, and a channel region may be formed along each of four sides or two long sides.

Further, in general formula (4), S _G is the area of the opening of the high-resistance layer, T is because the lateral width of the perimeter or channels of the openings, the T in FIG. 6 and FIG. 9 same , Then S _G
Since · R _B is is larger in FIG. 9, the current density J _L of the general public to FIG. 9 to latch-up is small. Conventional power MO
The pattern shown in FIG. 9 used in the SFET is not used at all at present. This is because it has been clarified that the on-resistance of the high voltage power MOSFET increases unless the area _SG and the perimeter T of the opening of the high resistance layer are increased. However, since the resistance of the n ^- type high resistance layer of the conductivity modulation type MOSFET is reduced due to the modulation of the conductivity, the opening area does not need to be widened as in the power MOSFET.

As is apparent from the above description, the present invention relates to a conductive modulation type.
When applied to a MOSFET, a great effect completely different from that when applied to a power MOSFET can be exhibited.

[Brief description of the drawings]

FIG. 1 is a plan view of a conductive modulation type MOSFET according to an embodiment of the present invention, FIG. 2 is a schematic plan view of a conductive modulation type MOSFET according to an embodiment of the present invention, and FIG. 3 is a conductive modulation type MOSFET of FIG. MOSFET A-
FIG. 4 is a sectional view taken along line A 'of FIG.
FIG. 5 is a sectional view taken along the line B 'of FIG.
FIG. 6 is a view showing a diffusion layer pattern of a conduction modulation type MOSFET according to another embodiment of the present invention, FIG. 7 is a sectional view of a conventional conduction modulation type MOSFET, and FIG. FIG. 9 is a cross-sectional view of another conduction modulation type MOSFET, and FIG. 9 is a conventional conduction modulation type MOSFET.
Fig. 10 shows the diffusion layer pattern of Fig. 10.
FIG. 11 is a perspective view of a MOSFET, and FIG. 11 is experimental data showing latching characteristics. 11 ...... p ⁺ -type drain layer, 12 ...... n ^- -type high resistance layer, 13 ...... p
Type base diffusion layer, 14 ...... n ⁺ -type source diffusion layer, 15 ...... p ⁺ base diffusion layer, 16 ...... gate insulating film, 17 ...... polycrystalline silicon film gate electrode, 18 ...... source electrode, 19 ...... Drain electrode, 20 ... Al gate electrode, 21 ... Channel region.

Continued on the front page (72) Inventor Kiminori Watanabe 1 Toshiba, Komukai Toshiba-cho, Kawasaki-shi Toshiba Research Institute, Inc. In-house (56) References JP-A-59-149058 (JP, A) JP-A-58-197771 (JP, A)

Claims (3)

(57) [Claims] A semiconductor substrate wafer having a high-concentration, first-conductivity-type drain layer and a second-conductivity-type high-resistance layer; a first-conductivity-type base layer formed on the high-resistance layer portion;
A high-concentration, second-conductivity-type source layer formed in the base layer and a gate insulating film formed on the base layer serving as a channel region sandwiched between the source layer and the high-resistance layer. In a conductive modulation type MOSFET including a gate electrode, a source electrode contacting both the source layer and the base layer, and a drain electrode contacting the drain layer, an opening exposed on the wafer surface of the high resistance layer A plurality of islands completely surrounded by the base layer.
T. 2. The conductive modulation type MOSFET according to claim 1, wherein said plurality of island-like high resistance layer portions have a shape having at least two parallel sides. 3. A plurality of island-shaped high-resistance layer portions are each formed in a rectangular shape and arranged in a matrix, and a channel region is formed along each long side. 2. The conductive modulation type MOSF according to claim 1,
ET.