JP2732495B2 - Insulated gate semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]   The present invention relates to an insulated gate semiconductor device, and more particularly to an insulated gate semiconductor device.
Gate resistance effective when applied to MISFET or IGBT for power
The present invention relates to an insulated gate semiconductor device with reduced resistance. [Conventional technology]   Power MOSFETs used in power semiconductor integrated circuits
As a conventional technology, for example, 1986 IEE
・ International Solid State Circuits
To Conference Digest of Technical
・ Papers Pages 22 to 23 (19861 IEEE Internati
onal Solid-State Circutis Conference DIGEST
OF TECHNICAL PAPERSpp22-23), Fuji Jiho Vol. 50, No. 1,
No. 1 (1986) pages 703 to 706, or electronic mail
IEICE Technical Report Vol. 86, No. 363 (1987), p. 23
The technique described on page 29 is known.   These conventional technologies are used for power MISFET or IGBT gates.
Gates are manufactured using a self-aligned process
The electrodes are formed of polycrystalline silicon. [Problems to be solved by the invention]   The above prior art is a power MISFET or IGBT gate.
Is formed by adopting a self-alignment process.
Is formed of polycrystalline silicon. Generally polycrystalline silicon
Since the sheet resistance of the recon is several tens of ohms / square,
The technology is used to increase the gate resistance of MISFET and IGBT
There is a problem that it is. In particular, power semiconductors
The device must reduce conduction loss, that is, reduce on-resistance.
It is important that the element area is large to secure the effective channel width.
It will be sharp. Therefore, the gate resistance is large.
Future technology problems will be more serious.   This problem is explained below using the power MISFET as an example.
You.   That is, a power MISF configured by a plurality of unit MISFETs
In ET, the unit near the gate electrode outlet
MISFET gate resistance compared to gate electrode outlet?
The gate resistance of the unit MISFET farther away is much higher.
And the gate input time constant also becomes a large value. Toes
The gate potential is MISFET for the same gate input signal.
Large difference in the time to reach the threshold voltage of
And Therefore, when switching the MISFET as a whole,
Is governed by the average value of the rise time of the gate potential
Will be done. In other words, variations in gate resistance
If the switching speed of MISFET is suppressed more
I can say.   Also, if the switching speed varies, it is safe.
It also reduces the operating area (ASO). That is, MISFE
Turns off the gate when T changes from on to off
When a signal is input, the part with low gate resistance is fast
Turns off, but high gate resistance is off
It is late to change to a state. Load of power element is inductive negative
Since the load is heavy, current concentrates on this delayed part
May lead to device destruction.   And in the power MISFET, in order to secure the element breakdown voltage,
Although it has a high-resistance drain layer, this resistance
Therefore, it is necessary to reduce the drain resistance.
You. In particular, when the element changes from the on state to the off state
The drain resistance must be reduced quickly.   An object of the present invention is to provide a power semiconductor device such as a power MISFET.
The gate switching resistance of the device to increase the switching speed of the device.
To increase the safe operating area and reduce the drain resistance.
To provide an insulating sheet type semiconductor device.   It is another object of the present invention to provide a semiconductor device comprising:
Minimizes cell operation variations and prevents current concentration
And equalize the current flowing through each unit cell.
Insulated gate capable of switching large current
A semiconductor device.   According to the present invention, the object is to provide a power MISFET or
On the gate electrode of the IGBT, the material constituting the gate electrode
By layering materials with small sheet resistance,
The gate electrode material has a lower sheet resistance than the gate electrode material.
Achieved by short-circuiting the material.   Further, the object is to provide a unit cell provided in a source region.
Electrodes formed so as to cover the surface of the semiconductor device
Connecting layers to the same electrode of adjacent unit cells
Is achieved by [Action]   The gate electrode material has a lower sheet resistance than the gate electrode material.
MISFET or power for power by short-circuiting with small material
Reduces the gate resistance of the IGBT and is close to the gate signal input.
Time delay of MISFETs far away compared to
As a result, power MISFET or IGBT switches
Can be speeded up.   Furthermore, since the gate resistance is reduced, the power MISFET
Or, reduce the variation in operating speed between IGBT unit cells.
Current concentration during turn-off.
Can be prevented, and as a result, the safe operation area can be expanded.   And since the gate resistance can be reduced, the gate electrode
The potential of the gate electrode can be quickly increased,
Change the high-resistance drain layer to a storage layer
Can be reduced, and as a result, the on-resistance can be reduced.   Furthermore, the electrode of the unit cell provided in the source region is
Next to the conductive layer formed to cover the surface of the semiconductor device
Since they are connected to the same electrode of the unit cell
This reduces the resistance between each unit cell and the source electrode.
And uniformity, so each unit cell
Make the flowing current uniform and perform high-current switching.
Can be. 〔Example〕   Hereinafter, of the power insulated gate semiconductor device according to the present invention
Embodiments will be described in detail with reference to the drawings.   In the following description, examples shown as reference examples are as follows:
It is for a better understanding of the invention. Reference Example 1   FIG. 1 is a sectional view taken along the line AA 'of FIG.
2 is a cross-sectional view taken along a line, and FIG. 2 is a unit cell 4 of a power MISFET.
FIG. In FIG. 2, the configuration is made easy to see.
Electrode, conductive layer for gate electrode short-circuit, source connection
Hole, source electrode, second source electrode source electrode, second saw
Only the electrode connection holes are shown.   In FIG. 1, 1 is N⁺Semiconductor made of single crystal silicon
Reference numeral 2 denotes an epitaxial layer on the semiconductor substrate 1.
Consisting of N^-Type semiconductor region. N-type semiconductor region 1 and
Reference numeral 2 denotes a drain region of the power MISFET. N^-Type
In the semiconductor region 2, the channel of the power MISFET and
A P-type semiconductor region 3 serving as an L region is formed. This
A source region of the power MISFET in a P-type semiconductor region of
N⁺A type semiconductor region 4 is formed. Epitaxy
Layer (N^-Oxide due to oxidation of the surface of the semiconductor region 2)
A gate oxide film 5 made of a silicon film and, for example, polycrystalline silicon
The gate electrode 6 made of a film constitutes a gate portion.
You. N^-Type drain region 2 is N^-Of the semiconductor region 2
And the lower part of the gate electrode 6. Paraphrase
For example, the gate electrode 6 is not only in the channel region but also in the drain region.
It is also provided on region 2. P-type channel region 3
The gate electrode side end is defined by the gate electrode 6, and
It extends around the lower part of the gate electrode 6. N⁺Type source area
4 is defined by the gate electrode 6 at its gate electrode side end.
And goes under the gate electrode 6. Get
The periphery other than the end on the side of the gate electrode 6 is, for example, a resist film.
This is defined by a mask made of such a material.   N⁺First aluminum is added to the source region 4 and the P-type well region 3.
The conductive layer 7b made of a silicon oxide film 5 and the insulating film 12
Are selectively removed through the connection hole 10b.
I have. In addition, a conductive layer 7a is formed on the gate electrode 6 by an insulating film 12a.
Are selectively removed through the connection hole 10a.
I have.   N⁺The conductive layer 7b connected to the source region 4
Conductor connecting between unit cells consisting of two aluminum layers
The conductive layer 9 passes through a connection hole 11 formed by selectively removing the insulating film 8.
Connected.   The connection connected to the gate electrode 6 through the connection hole 10a
The electrical layer 7a extends to the bonding pad for gate signal input.
It is extended and has the effect of reducing the gate resistance.   As described above, the power MISFET gaming
The gate electrode is a conductive layer with lower sheet resistance than the gate electrode material
Are overlapped and short-circuited. That is, the gate input signal
Part close to the bonding pad for the gate
And parts far from the gate bonding pad are delayed
It operates according to the gate signal. In addition, the gate
By changing the underlying high-resistance drain layer to a storage layer,
In-resistance can be reduced.   Further, the electrode provided in the source region of each unit cell is
It is connected to the electrodes of other unit cells by the conductive layer 9.
And reduce the resistance between each unit cell and the source electrode.
And can flow evenly in each unit cell
Making the current uniform and switching large currents
Can be.   In addition, such a configuration is compatible with the conventional power MISFET manufacturing process.
Process to form insulating layer, connection hole and second conductive layer
It can be configured just by doing. Example 1   FIG. 3 is a plan view of the first embodiment, and FIG. 4 and FIG.
3 along the line BB 'and the line CC', respectively.
FIG. FIG. 3 shows a unit cell 4 of the power MISFET.
FIG. In FIG. 3, the configuration is made easy to see.
Gate electrode, source electrode, source connection hole, gate electrode
Electrode for gate / electrode short-circuit
Only shows.   In this embodiment, the gate electrode 6 is formed of the second aluminum layer.
Short-circuited through the connection hole 11 using the conductive layer 9.   This will be described in detail below.   In the first embodiment, as shown in FIG.
10 and the conductive interlayer connection hole 11 for gate electrode / gate short circuit
Are arranged on a plane so that they do not overlap each other.
You.   4 and 5, 1 is N⁺Type single crystal silicon
The semiconductor substrate 2 is composed of
N consisting of a taxial layer^-Type semiconductor region. N-type semiconductive
Body regions 1 and 2 constitute the drain region of the power MISFET.
ing. N^-Of the power MISFET in the semiconductor region 2
And a P-type semiconductor region 3 serving as a well region is formed.
Have been. In this P-type semiconductor region, the power MISFET
N to be the source area⁺A type semiconductor region 4 is formed.
Epitaxial layer (N^-Oxidation of the surface of the semiconductor region 2)
A gate oxide film 5 made of a silicon oxide film
The gate portion is formed by the gate electrode 6 made of a crystalline silicon film.
It is configured. N^-Type drain region 2 is N^-Semiconductor region
2 mainly consists of the lower part of the gate electrode 6.
You. In other words, if the gate electrode 6 has only the channel region,
Instead, it is also provided on the drain region 2. P type chair
A gate electrode side end of the tunnel region 3 is defined by a gate electrode 6.
And goes under the gate electrode 6.
N⁺The gate electrode side end of the source region 4 is connected to the gate electrode 6.
Around the lower portion of the gate electrode 6.
It is crowded. Peripheral parts other than the end on the gate electrode 6 side are, for example,
For example, it is defined by a mask made of a resist film.
You.   N⁺First aluminum is added to the source region 4 and the P-type well region 3.
The conductive layer 7 composed of a silicon oxide film 5 and an insulating film 12
Are selectively removed through the connection hole 10.
You. An insulating film 8 is formed on the conductive layer 7. Gate electrode 6
A conductive layer 9 made of, for example, a second aluminum layer is formed thereon.
Through the connection hole 11 formed by selectively removing the insulating films 12 and 8
Connected.   Conductive layer connected to gate electrode 6 through connection hole 11
9 is extended to the bonding pad for the gate,
This has the effect of reducing the gate resistance.   Although not shown in the figure, it is the same as in the case of the prior art.
In addition, the semiconductor substrate acting as the drain region includes:
The drain electrode is connected.   As described above, the gate of the power MISFET of the present embodiment is
The gate electrode is a conductive layer with lower sheet resistance than the gate electrode material.
Short-circuited. That is, for the gate input signal,
The part close to the bonding pad for the gate should also be
Gate signals can be transmitted to the part far from the
It works according to the number. In addition, the high-resistance gate under the gate electrode
Reducing drain resistance by changing rain layer to accumulation layer
Can be achieved.   In addition, such a configuration is compatible with the conventional power MISFET manufacturing process.
Process to form insulating layer, connection hole and second conductive layer
It can be configured just by doing. Reference example 2   FIG. 6 is a sectional view taken along the line DD 'of FIG.
7 is a plan view of four IGBT unit cells.
The figure is shown. In FIG. 7, the game is
Electrode, cathode electrode, second source electrode, cathode connection
Hole, gate electrode / gate short circuit conductive interlayer connection hole, gate
Only the conductive layer for short circuit is shown.   This reference example is an example of an IGBT. This will be described in detail below.   In FIG. 6, 13 is P⁺Type single crystal silicon half
Reference numeral 14 denotes a conductor substrate, and 14 denotes N formed in the semiconductor substrate 13.⁺diffusion
15 is a layer from the epitaxial layer on the semiconductor substrate 13.
N^-Type semiconductor region. P⁺Type semiconductor region 13 is an IGBT
It constitutes the anode region. N⁺The diffusion layer 14 has an anode area.
Zone 13 and N^-When forward bias is applied between semiconductor regions
Anode region 13 to N^-Holes are injected into the semiconductor region 15
It works to suppress.   N^-IGBT channels and wafers in the semiconductor region 15.
A P-type semiconductor region 16 serving as a memory region is formed. this
N serving as a cathode region of the IGBT in the P-type semiconductor region 16⁺
A type semiconductor region 17 is formed. Epitaxy layer
(N^-Oxide by oxidation of the surface of the semiconductor region 15)
Film gate oxide film 18 and for example polycrystalline silicon film
A gate portion is constituted by the gate electrode 19 made of such a material.
N^-Type semiconductor region 15 is N^-Out of the semiconductor region 15
The lower part of the electrode 19 is formed. In other words, game
The electrode 19 is not only in the channel region, but also in N^-Semiconductor region 15
It is also provided above. Gate voltage of P-type channel region 16
The pole end is defined by the gate electrode 19, and
It goes around the lower part of the electrode 19. N⁺Mold cathode area 17
The end on the gate electrode side is defined by the gate electrode 19.
And goes under the gate electrode 19. Gate
The peripheral part other than the end on the electrode 19 side is made of, for example, a resist film.
This is defined by a mask.   N⁺First aluminum is applied to the cathode region 17 and the P-type substrate region 16.
The conductive layer 20b composed of a silicon oxide film 18 and the insulating film 2
3 is selectively removed through the connection hole 23b.
I have. On the gate electrode 19, the conductive layer 20a selects the insulating film 25.
Connected through the connection hole 23a that is selectively removed.
You.   N⁺The conductive layer 20b connected to the cathode region 17 and the second
The conductive layer 22 made of an aluminum layer selectively covers the insulating film 21.
The connection is made through the connection hole 24 that has been removed. Conductive layer
22 connects between the conductive layers 20b of each unit cell,
It extends to the cathode bonding pad.   The conductor connected to the gate electrode 19 through the connection hole 23a
The electric layer 20a is extended to the bonding pad for the gate.
This has the effect of reducing the gate resistance.   As described above, the gate of the IGBT of this reference example is
Shorted by a conductive layer with a lower sheet resistance than the electrode material.
You. That is, the gate input signal is
The part close to the opening pad is also used for the gate bonding pad.
The part far from the edge also moves according to the gate signal without time delay.
Make. In addition, the high resistance N under the gate electrode^-Layer to accumulation layer
, The on-resistance can be reduced.   In addition, such a configuration is insulated from the conventional IGBT manufacturing process.
Just add the steps of forming layers, contact holes and second conductive layer
Can be configured. Example 2   FIG. 8 is a plan view of the second embodiment, and FIG. 9 and FIG.
Are the EE 'section line and the FF' section line in FIG. 8, respectively.
FIG. Fig. 8 shows four IGBT unit cells.
FIG. In FIG. 8, in order to make the configuration easy to see,
Gate electrode, cathode electrode Second cathode electrode, cathode
Connection hole, gate electrode / gate short-circuit conductive interlayer connection hole,
Only the short-circuit conductive layer is shown.   In this embodiment, the gate electrode 19 of the IGBT is
Short-circuit through the connection hole 24 using the conductive layer 22 consisting of
This is the configuration. This will be described in detail below.   9 and 10, 13 is P⁺Type single crystal silicon
14 is formed in the semiconductor substrate 13
N⁺Reference numeral 15 denotes a diffusion layer.
N consisting of a dial layer^-Type semiconductor region. P⁺Semiconductor region
13 constitutes the anode region of the IGBT. N⁺The diffusion layer 14
Anode region 13 and N^-Forward bias between semiconductor regions
The anode region 13 to N^-Holes injected into semiconductor area
It works to prevent entry.   N^-IGBT channels and wafers in the semiconductor region 15.
A P-type semiconductor region 16 serving as a memory region is formed. this
N serving as a cathode region of the IGBT in the P-type semiconductor region 16⁺
A type semiconductor region 17 is formed. Epitaxy layer
(N^-Type semiconductor region 15) Silicon oxide film by oxidation of the surface
From a gate oxide film 18 composed of, for example, a polycrystalline silicon film.
And the gate electrode 19 constitute a gate portion. N^-
Type semiconductor region 15 is N^-Of the gate type semiconductor region 15
It consists of the lower part of the electrode 19. In other words, the gate
The electrode 19 is not only in the channel region, but also in N^-Above semiconductor region 15
Is also provided. Gate electrode of P-type channel region 16
The side end is defined by the gate electrode 19, and
It wraps around the bottom of pole 19. N⁺Type cathode region 17
The gate electrode side end is defined by the gate electrode 19.
And goes under the gate electrode 19. Gate
The peripheral part other than the end on the electrode 19 side is made of, for example, a resist film.
This is defined by a mask.   N⁺First aluminum is applied to the cathode region 17 and the P-type substrate region 16.
The conductive layer 20 composed of a silicon oxide film 18 and the insulating film 23
Connected through a connection hole 23 that is selectively removed.
You. An insulating layer 21 is formed over the conductive layer 20. Gate electrode 19
A conductive layer 22 made of a second aluminum layer is formed on the insulating film.
Connected through connection hole 24 which is selectively removed 21 and 25
Have been.   N⁺The conductive layer 20 connected to the cathode region 17 is
It has been extended to the padding pad.   A conductive electrode connected to the gate electrode 19 through the connection hole 24
Layer 22 extends to the bonding pad for the gate
This has the effect of reducing the gate resistance.   Although not shown in the figure, it is the same as in the case of the prior art.
In addition, the semiconductor substrate acting as the anode region includes:
The anode electrode is connected.   As described above, the gate of the IGBT of this embodiment is
Shorted by a conductive layer with a lower sheet resistance than the electrode material.
You. That is, the gate input signal is
The part close to the opening pad is also used for the gate bonding pad.
The part far from the edge also moves according to the gate signal without time delay.
Make. In addition, the high resistance N under the gate electrode^-Layer to accumulation layer
, The on-resistance can be reduced.   In addition, such a configuration is insulated from the conventional IGBT manufacturing process.
Just add the steps of forming layers, contact holes and second conductive layer
Can be configured. Reference Example 3   FIG. 11 is a plan view of Reference Example 3, and FIG.
It is sectional drawing in the GG 'cutting line. Fig. 11 is for electric power
FIG. 3 shows a plan view of four unit cells of the MISFET. In FIG. 11,
The gate electrode, the source electrode, and the second
For source electrode, source connection hole, gate electrode / gate short circuit
Only conductive layer connection holes and gate short-circuit conductive layer are shown.
You.   This reference example is a power MISFET with a structure that is easy to integrate.
You. This will be described in detail below.   In FIG. 12, 26 is P⁺Type single crystal silicon half
27 is a conductor substrate, and 27 is an N formed in the semiconductor substrate 26.⁺Semiconduct
28 is an epitaxial layer on the semiconductor substrate 26
Rara N^-Type semiconductor region. N-type semiconductor regions 27 and 28
Constitutes the drain region of the power MISFET. 39
Is N^-N formed in the epitaxial layer region 28⁺Type semiconductor
Area and N⁺Semiconductor region 27 on the surface of semiconductor substrate 26
It is for withdrawal.   N^-In the semiconductor region 28, the channel and the
And a P-type semiconductor region 29 serving as a well region is formed.
You. In this P-type semiconductor region 29, the power MISFET source
N that is the⁺A type semiconductor region 30 is formed. Epi
Taxi layer (N^-Oxidation of the surface of the semiconductor region 28)
A gate oxide film 31 composed of a silicon oxide film and, for example, polycrystalline
The gate part consists of the gate electrode 32 made of silicon film
Have been. N^-Type semiconductor region 28 is N^-Semiconductor region 28
That is, it mainly consists of the lower part of the gate electrode 32. Word
In other words, the gate electrode 32 is not only in the channel region but also in the N region.^-Half
It is also provided on the conductor region 28. P-type channel area
The gate electrode side end of 29 is defined by the gate electrode 32.
And goes under the gate electrode 32. N⁺Type
The gate electrode side end of the source region 30 is connected to the gate electrode 32.
Is defined, and wraps around the lower part of the gate electrode 32.
I have. The peripheral portion other than the end on the gate electrode 32 side is, for example, a resist.
This is defined by a mask made of a strike film.   N⁺First aluminum is added to the source region 30 and the P-type semiconductor region 29.
The conductive layer 33b made of a silicon oxide film 31 and the insulating film 3
8 is selectively removed through the connection hole 36b.
I have. On the gate electrode 32, a conductive layer 33a selects an insulating film 38.
The connection is made through the connection hole 36a that is selectively removed.
You.   N⁺The conductive layer 33b connected to the source region 30 and the second
The conductive layer 35a made of a luminium layer selectively covers the insulating film 34.
The connection is made through the connection hole 37 that has been removed. Conductive layer
35a extends outside the power MISFET as a source electrode
Have been.   N⁺N pulling out drain region 27 to the surface⁺Type semiconductor
The region 39 has a connection hole 36b formed by selectively removing the insulating film 38.
Is connected to the conductive layer 33 through the conductive layer 33.
Conductive layer 35 through connection hole 37 formed by selectively removing film 34
Connected to b. The conductive layer 35b is a drain electrode
As an extension to the outside of the power MISFET.   The conductor connected to the gate electrode 32 through the connection hole 36a
The conductive layer 33a extends to the outside of the power MISFET as a gate electrode.
And has the effect of reducing the gate resistance.   As described above, the gate of the power MISFET of this reference example
Is short-circuited in the conductive layer with lower sheet resistance than the gate electrode material
Have been. In other words, gate input signal
Both near and far parts respond to the gate signal without time delay.
It can be operated in the same way. In addition, the gate electrode
Lower high resistance N^-Turn on layer to storage layer to reduce on-resistance
Can be achieved.   In addition, such a configuration can be used in a conventional power MISFET manufacturing process.
Process to form insulating layer, connection hole and second conductive layer
It can be configured just by doing. Example 3   FIG. 13 is a plan view of the third embodiment, and FIGS.
The figures are taken along the line HH 'and the line II' in FIG. 13, respectively.
It is sectional drawing in a disconnection. Fig. 13 shows the power MISFET
FIG. 4 shows a plan view of four place cells. The configuration is easy to see in Fig. 13.
Gate electrode, source electrode, second source electrode,
Source connection hole, conductive layer connection for gate electrode and gate short circuit
Only the hole and the conductive layer for gate short circuit are shown.   In this embodiment, the present invention is applied to a power MISF having a structure that can be easily integrated.
Applied to ET. This will be described in detail below.   In FIGS. 14 and 15, 26 is P⁺Type single crystal silicon
27 is a semiconductor substrate composed of
N made⁺28 is a semiconductor layer, and 28 is an epitaxial layer on the semiconductor substrate 26.
N consisting of a xylar layer^-Type semiconductor region. N-type semiconductor
Regions 27 and 28 constitute the drain region of the power MISFET.
doing. 39 is N^-Formed in the epitaxial layer region 28.
T⁺Type semiconductor region, N⁺Semiconductor region 27
This is for drawing out to the surface of the plate 26.   N^-In the semiconductor region 28, the channel and the
And a P-type semiconductor region 29 serving as a substrate region is formed.
You. In this P-type semiconductor region 29, the power MISFET source
N that is the⁺A type semiconductor region 30 is formed. Epi
Taxi layer (N^-Oxidation of the surface of the semiconductor region 28)
A gate oxide film 31 composed of a silicon oxide film and, for example, polycrystalline
The gate part consists of the gate electrode 32 made of silicon film
Have been. N^-Type semiconductor region 28 is N^-Semiconductor region 28
That is, it mainly consists of the lower part of the gate electrode 32. Word
In other words, the gate electrode 32 is not only in the channel region but also in the N region.^-Half
It is also provided on the conductor region 28. P-type channel area
The gate electrode side end of 29 is defined by the gate electrode 32.
And goes under the gate electrode 32. N⁺Type
The gate electrode side end of the source region 30 is connected to the gate electrode 32.
Is defined, and wraps around the lower part of the gate electrode 32.
I have. The peripheral portion other than the end on the gate electrode 32 side is, for example, a resist.
This is defined by a mask made of a strike film.   N⁺First aluminum is added to the source region 30 and the P-type semiconductor region 29.
The conductive layer 33 composed of a silicon oxide film 31 and an insulating film 38
Are selectively removed through the connection hole 36.
You. An insulating film 34 is formed on the conductive layer 33. Gate electrode 32
A conductive layer 33 made of a second aluminum layer is formed on the insulating film.
Connection through connection hole 37 with 34 and 38 selectively removed
Have been.   N⁺The conductive layer 33 connected to the source region 30
The electrode extends outside the power MISFET.   N⁺N pulling out drain region 27 to the surface⁺Type semiconductor
The region 39 has a connection hole 36 formed by selectively removing the insulating film 38.
Connected to the conductive layer 33, and furthermore, the conductive layer 33 is an insulating film.
Conductive layer 35b through connection hole 37 formed by selectively removing 34
Connected to The conductive layer 35b is a drain electrode
As an extension to the outside of the power MISFET.   A conductive electrode connected to the gate electrode 32 through the connection hole 37
Layer 35a extends outside power MISFET as gate electrode
And has the effect of reducing the gate resistance.   As described above, the gate of the power MISFET of the present embodiment
Is short-circuited in the conductive layer with lower sheet resistance than the gate electrode material
Have been. In other words, gate input signal
Both near and far parts respond to the gate signal without time delay.
It can be operated in the same way. In addition, the gate electrode
Lower high resistance N^-Turn on layer to storage layer to reduce on-resistance
Can be achieved.   In addition, such a configuration can be used in a conventional power MISFET manufacturing process.
Process to form insulating layer, connection hole and second conductive layer
It can be configured just by doing. Reference example 4   FIG. 16 is a plan view of Reference Example 4, and FIG. 17 is a plan view of FIG.
It is sectional drawing in the JJ 'cutting line. Figure 16 shows the IGBT
A plan view of four unit cells is shown. FIG. 16 shows the configuration.
Gate electrode, cathode electrode, 2nd cathode
Electrode, cathode connection hole, gate electrode / gate shorting conductor
Only the inter-layer connection hole and the gate short-circuiting conductive layer are shown.   This reference example is a power IGBT with a structure that is easy to integrate.
You. This will be described in detail below.   In FIG. 17, reference numeral 40 denotes a half made of N-type single crystal silicon.
41 is a conductor substrate, and 41 is a P formed in the semiconductor substrate 40.⁺Semiconduct
42 is an epitaxial layer on the semiconductor substrate 40
Rara N^-Type semiconductor region. P⁺Type semiconductor region 41
It constitutes the anode region of IGBT. 53 is N^-Epitaxy
P formed in the shear layer region 42⁺Type semiconductor region, P⁺
For drawing the semiconductor region 41 to the surface of the semiconductor substrate 40.
It is.   N^-In the semiconductor region 42, the channel of the IGBT and the wafer
A P-type semiconductor region 43 serving as a memory region is formed. this
In the P-type semiconductor region 43, N serving as a cathode region of the IGBT is formed.⁺
A type semiconductor region 44 is formed. Epitaxy layer
(N^-Oxide by oxidation of the surface of the semiconductor region 42)
Film gate oxide film 45 and for example polycrystalline silicon film
A gate portion is constituted by the gate electrode 46 made of such a material.
N^-Type semiconductor region 42 is N^-Out of the semiconductor region 42
The lower electrode 46 has a lower portion. In other words, game
The electrode 46 is not only in the channel region, but also in N^-Of semiconductor region 42
It is also provided above. Gate voltage of P-type channel region 43
The pole end is defined by the gate electrode 46, and
It goes around the lower part of the electrode 46. N⁺Type cathode region 44
The gate electrode side end is defined by the gate electrode 46.
And goes around the lower part of the gate electrode 46. Gate
The peripheral part other than the end on the electrode 46 side is made of, for example, a resist film.
This is defined by a mask.   N⁺The first aluminum region is connected to the cathode region 44 and the P-type semiconductor region 43.
The conductive layer 47b made of a metal layer is insulated from the silicon oxide film 45.
The connection is made through a connection hole 50b formed by selectively removing the film 52.
Have been. On the gate electrode 46, a conductive layer 47a forms an insulating film 52.
It is connected through the connection hole 50a that is selectively removed.
You.   N⁺The conductive layer 47b connected to the cathode region 44 and the second
The conductive layer 49a made of an aluminum layer selectively uses the insulating film 48.
The connection is made through a connection hole 51 that has been removed. Conductive
The layer 49a is extended outside the IGBT as a cathode electrode.
I have.   P⁺P pulling out the anode region 41 to the surface⁺Type semiconductor
The region 53 has a connection hole 50 formed by selectively removing the insulating film 52.
Connected to the conductive layer 47, and furthermore, the conductive layer 47 is an insulating film.
Conductive layer 49b through connection hole 51 formed by selectively removing 48
Connected to The conductive layer 49b is a drain electrode
It has been extended outside the IGBT.   The conductor connected to the gate electrode 46 through the connection hole 50a
The electric layer 47a is extended to the outside of the IGBT as a gate electrode.
This has the effect of reducing the gate resistance.   As described above, the gate of the IGBT of this reference example
Shorted by a conductive layer with a lower sheet resistance than the electrode material.
You. That is, the portion near the gate for the gate input signal
Minutes and distant parts operate according to the gate signal without time delay
It is possible to do. In addition, the high resistance under the gate electrode
Anti-N^-Change the layer to a storage layer to reduce on-resistance.
Can be.   In addition, such a configuration is insulated from the conventional IGBT manufacturing process.
Just add the steps of forming layers, contact holes and second conductive layer
Can be configured. Example 4   FIG. 18 is a plan view of the fourth embodiment, and FIG. 19 and FIG.
At the KK 'section line and the LL' section line in FIG.
It is sectional drawing. Figure 18 shows a plan view of four IGBT unit cells.
Show. In FIG. 18, the gate voltage is set to make the structure easier to see.
Pole, cathode electrode second cathode electrode, cathode connection hole,
Conductive interlayer connection hole for gate electrode / gate short circuit, gate short circuit
Only the conductive layer is shown.   In this embodiment, the present invention is applied to an IGBT having an easily integrated structure.
It was done. This will be described in detail below.   In FIGS. 19 and 20, reference numeral 40 denotes an N-type single crystal silicon.
A semiconductor substrate 41 is formed in the semiconductor substrate 40.
P made⁺Reference numeral 42 denotes a semiconductor layer.
N consisting of a xylar layer^-Type semiconductor region. P⁺Type semiconductor
Region 41 constitutes the anode region of the IGBT. 53 is
N^-P formed in the epitaxial layer region 42⁺Type semiconductor area
Area and P⁺Semiconductor region 41 on the surface of the semiconductor substrate 40
It is for putting out.   N^-In the semiconductor region 42, the channel of the IGBT and the wafer
A P-type semiconductor region 43 serving as a memory region is formed. this
In the P-type semiconductor region 43, N serving as a cathode region of the IGBT is formed.⁺
A type semiconductor region 44 is formed. Epitaxy layer
(N^-Oxide by oxidation of the surface of the semiconductor region 42)
Film gate oxide film 45 and for example polycrystalline silicon film
A gate portion is constituted by the gate electrode 46 made of such a material.
N^-Type semiconductor region 42 is N^-Out of the semiconductor region 42
The lower electrode 46 has a lower portion. In other words, game
The electrode 46 is not only in the channel region, but also in N^-Of semiconductor region 42
It is also provided above. Gate voltage of P-type channel region 43
The pole end is defined by the gate electrode 46, and
It goes around the lower part of the electrode 46. N⁺Type cathode region 44
The gate electrode side end is defined by the gate electrode 46.
And goes around the lower part of the gate electrode 46. Gate
The peripheral part other than the end on the electrode 46 side is made of, for example, a resist film.
This is defined by a mask.   N⁺The first aluminum region is connected to the cathode region 44 and the P-type semiconductor region 43.
The conductive layer 47 made of a metal layer is a silicon oxide film 45 and an insulating film.
52 is selectively removed through a connection hole 50b.
ing. A gate electrode for forming an insulating film 48 on the conductive layer 47
A conductive layer 49a made of a second aluminum layer is formed on the pole 46.
Through the connection hole 51 formed by selectively removing the edge films 52 and 48
It is connected.   N⁺The conductive layer 47 connected to the cathode region 44 is a cathode
The electrode extends outside the IGBT.   P⁺P pulling out the anode region 41 to the surface⁺Type semiconductor
The region 53 has a connection hole 50 formed by selectively removing the insulating film 52.
Connected to the conductive layer 47, and furthermore, the conductive layer 47 is an insulating film.
Conductive layer 49b through connection hole 51 formed by selectively removing 48
Connected to The conductive layer 49b is a drain electrode
It has been extended outside the IGBT.   A conductive electrode connected to the gate electrode 46 through the connection hole 51
Layer 49a is extended outside the IGBT as a gate electrode.
This has the effect of reducing the gate resistance.   As described above, the gate of the IGBT of this embodiment is
Shorted by a conductive layer with a lower sheet resistance than the electrode material.
You. That is, the portion near the gate for the gate input signal
Minutes and distant parts operate according to the gate signal without time delay
It is possible to do. In addition, the high resistance under the gate electrode
Anti-N^-Change the layer to a storage layer to reduce on-resistance.
Can be.   In addition, such a configuration is insulated from the conventional IGBT manufacturing process.
Just add the steps of forming layers, contact holes and second conductive layer
Can be configured.   As described above, in the first to fourth embodiments, the first conductive layer and the second conductive layer
The description is made on the assumption that aluminum is used for the conductive layer.
However, the present invention is not limited to this.
When using conductive materials (eg copper or copper alloy)
It doesn't matter.   In the first to fourth embodiments, the N-channel power MI
SFET or N-channel IGBT was explained.
Ming is not limited to this, but for P-channel power
Applicable to MISFET or P-channel IGBT
Can be.   In Examples 1 to 4, the gate electrode was shortened.
The short-circuiting material shortens the gate electrode through a plurality of connection holes.
It may be provided to be entangled. 〔The invention's effect〕   As described above, according to the present invention, a power MISFET
Alternatively, the gate electrode of the IGBT is made of a material constituting the gate electrode.
Short-circuit with a material with lower sheet resistance than
Reduce the gate resistance of MISFET or IGBT, and as a result
Increase the switching speed of power MISFET or IGBT,
It is possible to expand the safe operation area and reduce the on-resistance
The effect can be achieved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view taken along the line AA 'of FIG. 2 showing the configuration of Reference Example 1, FIG. 2 is a plan view of a power MISFET of Reference Example 1, and FIG. Is a plan view of the power MISFET of the first embodiment, and FIG.
FIG. 5 and FIG. 5 are respectively a sectional view taken along the line BB ′ of FIG.
FIG. 6 is a cross-sectional view taken along the line C ′, FIG. 6 is a cross-sectional view taken along the line D-D ′ in FIG. 7, showing the configuration of Reference Example 2, FIG. 7 is a plan view of the IGBT of Reference Example 2, and FIG. FIG. 9 is a plan view of the IGBT of Example 2, and FIGS.
FIG. 11 is a cross-sectional view taken along line E ′ and line FF ′. FIG. 11 is a plan view of the power MISFET of Reference Example 3, and FIG.
13 is a sectional view taken along line G ', FIG. 13 is a plan view of the power MISFET of the third embodiment, and FIGS. 14 and 15 are HH' line and II 'line of FIG. 13, respectively. Sectional view at
FIG. 16 is a plan view of the IGBT of Reference Example 4, and FIG.
FIG. 18 is a cross-sectional view taken along the line J ′, FIG. 18 is a plan view of the IGBT of the fourth embodiment, and FIGS. 19 and 20 are KK ′ in FIG.
It is sectional drawing in the cutting line LL 'cutting line. 1 ...... N ⁺ -type semiconductor substrate (drain region), 2 ...... N ^- -type epitaxial layer (drain region), 3 ...... P-type semiconductor region, 4 ...... N ⁺ -type source region, 5 ...... gate insulating film (Silicon oxide film), 6 ... gate electrode (polycrystalline silicon film), 7a ... gate short-circuit conductive layer, 7b ... source connection conductive layer, 8 ... insulating film, 9 ... conductive layer, 10a ... ... connection hole for gate short-circuit, 10b ... connection hole for source connection, 11 ... connection hole, 12 ... insulating film.

   ────────────────────────────────────────────────── ─── Continuation of front page    (56) References JP-A-61-248475 (JP, A)                 JP-A-61-82477 (JP, A)                 JP-A-57-162359 (JP, A)                 JP-A-58-17676 (JP, A)                 JP-A-60-236265 (JP, A)                 JP-A-58-89864 (JP, A)                 JP-A-59-149058 (JP, A)                 JP-A-60-27170 (JP, A)

Claims (1)

(57) [Claims] A semiconductor substrate, a first region having a lower impurity concentration than the semiconductor substrate, a plurality of second regions formed in the first region and having a different conductivity type from the first region, and the plurality of second regions. A plurality of third regions formed in the region and having the same conductivity type as the first region, part or all of the surface of the first region, and part of the surface of the second region; Alternatively, an insulated gate semiconductor including a plurality of insulated gate electrodes provided entirely via a gate insulating film, a plurality of electrodes provided in the second and third regions, and an electrode connected to the semiconductor substrate In the device, a plurality of electrodes provided in the second and third regions are short-circuited to each other by a short-circuit portion extending from the plurality of electrodes onto an insulated gate electrode, and a short-circuit portion between the plurality of electrodes and the electrode is formed. An insulating film is provided on the The insulated gate electrode is provided on the insulating film so as to straddle a short-circuit portion of the plurality of electrodes, and is short-circuited to each other by a conductive layer having a lower sheet resistance than a material of the plurality of insulated gate electrodes. Is an insulated gate semiconductor device extending to a gate bonding pad. 2. The semiconductor device according to claim 1, wherein
And a region having the same conductivity type. 3. The semiconductor device according to claim 1, wherein
An insulated gate semiconductor device having a region of opposite conductivity type. 4. 2. The insulated gate semiconductor device according to claim 1, wherein the insulated gate electrode is made of polycrystalline silicon. 5. 2. The insulated gate semiconductor device according to claim 1, wherein the conductive layer is made of an aluminum alloy.