JPS6182477A - Conductivity modulation type MOSFET - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] (Technical field of invention) The present invention relates to a conductivity modulated MO3FET.

[Technical background of the invention and its problems]

Conductivity modulation type MO3FET is a normal power MO3FET
The conductivity type of the drain region is opposite to that of the source region. The structure of a conventional conductivity modulation type MO3FET is shown in FIG. 41 is a p+ drain layer, 42 is an n- type high resistance layer, and a p type base diffusion layer 4 is formed on the surface of this high resistance layer 42.
3 is formed and 1. Furthermore, in this p-type base diffusion layer 43,
A + type source diffusion layer 44 is formed. Then, a portion of the p-type base layer 43 sandwiched between the source diffusion 1144 and the high resistance layer 42 exposed on the surface is used as a channel region 49.
A gate electrode 46 is disposed on this via a gate insulating film 45, and a source electrode 47 is formed in contact with both the source diffusion 1i44 and the base diffusion layer 43.

A drain electrode 48 is formed on the surface of the drain layer 48.

In this conductivity modulation type MO3FET, when a positive voltage is applied to the gate electrode 46 with respect to the source electrodes 4 and 7, an inversion layer is formed in the channel region 49, and electrons from the source diffusion layer 44 pass through this channel region 49. n-type high resistance layer 4
Injected into 2. The injected electrons diffuse through the high resistance layer 42 and escape to the drain electrode 48, but at this time, holes are caused to be injected from the drain layer 41. Due to the injection of holes, conductivity modulation occurs in the high resistance layer 42 due to accumulation of carriers, and the resistance of the high resistance layer 42 at the mouth decreases.

As a result, a MOSFET with a lower on-resistance than a normal power MO8FET can be obtained.

By the way, in such conductivity modulation type MO8FET, p
The four layers of the + type drain layer 4l, the n- type high resistance layer 42, the p type base diffusion layer 43, and the n+ type source diffusion layer 44 constitute a thyristor. When this strange thyristor becomes conductive, the device cannot be turned off even if the gate-source voltage is reduced to zero, which often leads to device destruction. The reason why this parasitic thyristor turns on is that holes injected from the p + -type drain layer 41 pass through the p-type base diffusion layer 44 when exiting to the source electrode 47 . That is, when such a hole current flows and the voltage drop due to the resistance of the base diffusion layer 43 directly below the source diffusion layer 44 exceeds the built-in voltage between the base and source, electron injection from the source layer 44 is caused, and the parasitic thyristor turns on.

In order to prevent such a latching phenomenon of the parasitic thyristor, as shown in FIG. 5, a high concentration p1 type base diffusion layer 50 is formed in the p type base diffusion layer 43 to lower the resistance of the p type base diffusion layer. is being carried out. However, even with this method, the conventional conductivity modulation type MOSFET has a
There was a problem in that only a current of about OA/ci could be turned off. As a result of investigating the fundamental reason,
It has become clear that the conventional conductivity modulation type M, O, S, FET uses the same source and gate patterns as the normal power MO3FET. This point will be explained in detail below.

FIG. 6 shows a diffusion layer pattern of the conductivity modulation type MO3FET shown in FIG. 85. As shown in the figure, the p-type base diffusion layer 43 has a pattern in which 11 Wirs are diffused in a hexagonal shape, and a channel region 1149- is formed at the periphery of each. Such a pattern can be created using a power MO3FET.
This was effective in increasing the gate area and reducing the on-resistance.

However, in the conduction modulation type MO3FET, where there is a requirement that the parasitic thyristor should not be turned on, such a pattern has the following disadvantages.

First, in order to prevent parasitic thyristor operation, it is desirable that the resistance from the channel region 49 to the opening of the p1 type base diffusion layer 50 be as small as possible. However, in the pattern shown in FIG. 6, the contact with the source and electrode of the p+ type base diffusion layer 50 is formed at the center of the p type base diffusion M43, and its peripheral length is equal to the p type base diffusion layer 43.
is smaller than the length of the channel region 49 around the
Due to the spread resistance, the resistance between the channel region 1449 and the source electrode of the p4 type base diffusion layer 50 and the contact cannot be made sufficiently small.

Second, in the pattern of FIG. 6, the width La of the opening of the n-type high resistance layer 42 exposed on the surface of the substrate wafer, that is, the portion where the gate electrode is disposed, is large, which facilitates thyristor operation. are doing. The fact that the drain current during latching of the parasitic thyristor is inversely proportional to La is shown as follows. A current flows substantially uniformly under the gate insulating crotch and flows into the p-type base layer, so that the next current 1p flows under the gate insulating film having a width equal to the unit length of the four channel regions.

Ip -3a -Jp /T......■Here, Jp is the hole current density, and SG is n- per unit area.
The area of the opening of the high-resistance layer, and ■ is the peripheral length of the p-type base diffusion layer per unit area. This current flows into the base diffusion layer under the source diffusion layer, and the voltage drop due to the resistor R8 under the source diffusion layer increases the built-in voltage Vb between the base and source.
When it becomes higher than i, the parasitic thyristor turns on. Expressing this in a formula, Vl)i=Ip-Re/T=SG-JP-Rday/T...■. However, Ra is the resistance from the channel of the p-type base layer to the p+ contact per unit of peripheral length. Solving this for Jp yields Jp =Vbi-T/Sa-Ra =-■. At turn-off, the channel inversion layer disappears and the current becomes mostly hole current, so the latching current density Jt is: JL-Vbi-T/'SG -RB ・・・・・・■
becomes. Sa/T is approximately La, and JL is inversely proportional to La. This is also clear from FIG. 8, which is the experimental data of the present inventors.

On the other hand, as shown in the perspective view of FIG. 7, the gate electrode 46 is made of polycrystalline silicon. J:I>film 46t and Aff#j! 46
2 (7) In the case of a laminated structure, if the width of Affil 1462 is 30 μm, the width of polycrystalline silicon film 461 is 5 μm.
0 to 60 μm is required. That is, when a conventional pattern as shown in FIG. 6 is used, the width G of the opening of the n-type high resistance layer 42 is required to be 50 to 60 μm. This was the reason why it was not possible to effectively prevent latch-up in conventional conduction modulation type MOSFETs.

[Purpose of the invention]

The present invention was developed as a result of the above considerations, and it is an object of the present invention to provide a conduction modulation type MOSFET that does not latch up to a much larger current than conventional MOSFETs.

[Summary of the invention]

In the conductivity modulation MOSFET according to the present invention, the part of the high resistance layer exposed to the wafer surface is surrounded by the base diffusion layer, contrary to the conventional pattern in which the part of the high resistance layer exposed to the wafer surface surrounds the base diffusion layer. The pattern is arranged in a plurality of islands.

[Effects of the Invention] According to the present invention, the base layer resistance under the channel region can be made smaller than before, and the area of the high resistance layer opening under the gate insulating film can be made smaller than before.
750A/ca! A conduction modulation type MOSFET that does not latch up at current densities above can be realized.

[Embodiments of the invention]

The present invention will be explained in detail below. FIG. 1 shows the structure of a conductivity modulation type MO3FET according to an embodiment, where (a) is a plan view, and (b), (c), and (d) are A-A of ta), respectively.
-, BB-, CC- sectional views. There is an n-type high resistance layer 12 on the p+ type drain layer 11, a p type base diffusion layer 13 is formed on the surface of this high resistance layer 12, and an n+ type source diffusion layer 14 is formed in the base diffusion layer 13. is formed. A channel region 21 is formed between the source diffusion layer 14 and the wafer surface opening of the resistance layer 12, and a gate electrode 17 made of polycrystalline silicon is formed thereon via a gate insulating film 16. Source diffusion layer 14
The source It contacts both the base diffusion layer 13 and the base diffusion layer 13.
i18 is provided, and a drain electrode 19 is provided on the drain layer 11 on the back surface of the wafer. The basic structure described above is the same as the conventional one.

The features of this embodiment are as follows: First, the portions of the high resistance layer 12 that are open below the gate electrode 17 are arranged in a matrix in a plurality of rectangular shapes shown by the width La in FIG. A channel region 21 is formed along the sides. The reason for using a rectangular shape is that when the n-type high resistance layer is formed into an island shape, the width of the channel a region can be maximized.

The second feature is that each of the plurality of rectangular openings is completely surrounded by the p-type base diffusion layer to form an island shape. That is, the polycrystalline silicon film gate electrode 17 is continuously disposed over the entire surface of the substrate wafer so as to cover the channel region 21 and the rectangular opening of the high resistance layer 12, and the gate electrode 17 is placed continuously on the entire surface of the substrate wafer where the source voltage ti18 does not run. Live ARI! A gate electrode 20 is provided, and the first
As shown in FIGS. (b) to (d), a highly concentrated p4″ type base diffusion layer 15 is formed under the source electrode 18 and under the Aj2 gate electrode 20 superimposed on the polycrystalline silicon film gate electrode 17. The p-type base diffusion layer 13 and the p + type base diffusion layer 15 form a rectangular opening in the high-resistance layer 12 .

In actual device manufacturing, for example, a wafer is used in which a p+ type Si substrate serving as the drain layer 11 is used as a starting substrate and an n- type high resistance layer 12 is epitaxially grown thereon, and impurity diffusion and electrode formation are sequentially performed on this wafer. n-type high resistance 1
Of course, 112 may be used as the starting substrate.

In this example, as is clear from FIG. The peripheral lengths of the openings in the base diffusion layer 15 are almost equal.Therefore, compared to the conventional structure shown in FIG. !Only the gate electrode 17 made of a polycrystalline silicon film is present above the portion where the anti-layer 12 opens to the wafer surface, and there is no AIt gate electrode, so the gate electrode width La in this portion can be made sufficiently small.

As described above, this La is inversely proportional to the latching current density. In an actual prototype example, La = 15 μm. Therefore, according to this embodiment, the latch-up phenomenon can be prevented more effectively than before, and a latch-up current density of 750 A/cd is obtained. Furthermore, with a total operating area of 2011'', it was possible to turn off a current of up to 150A.

The present invention is not limited to the above embodiments. For example, the shape of the high resistance layer portion exposed on the wafer surface does not necessarily have to be rectangular. This is an example pattern in which the arrangement of the p+ type base diffusion layer making contact with the source electrode and the n- type high resistance layer opening below the gate electrode is reversed to correspond to the conventional pattern shown in Fig. 6. is shown in Figure 2. Furthermore, the second
In the figure, parts corresponding to those in FIG. 1 are given the same reference numerals as in FIG. 1. If such a pattern is used, it will be easier to explain the present invention in detail in comparison with FIG. 6. Now, the source diffusion layer 14
The width n of the channel region 21 is the same as that in FIG.
It is also assumed that the length and width T (perimeter) are the same as in FIG. In the case of FIG. 2, the current path of the hole current that can be handled from the high resistance layer 12 under the gate electrode to the p+ type layer 13.15 passing under the channel region 21 is opposite to the conventional path shown in FIG. 6. .

Therefore, the base resistance under the channel region from the high resistance layer opening with the same peripheral length to the contact area with the source N pole of the p+ type base diffusion layer is as shown in Figure 6. It is obviously smaller than when it is surrounded and centered. As a result, the pattern of the present invention is less likely to latch up than the conventional pattern.

Further, the island-like high resistance layer portion may have a shape similar to a rectangle having at least two parallel sides, and a channel region may be formed along each of the four sides or two long sides. .

Furthermore, in general, in equation (2), Sa is the area of the opening in the high-resistance layer, and ■ is the peripheral length of the opening, that is, the width of the channel, so if T is the same in FIGS. 2 and 6, then 5G-
On the 8th, the 6th factor is larger, so the current density JL that causes latch-up is generally smaller than that shown in FIG. The pattern shown in FIG. 6, which was used in the conventional power MO3FET, is no longer used at all. It is a high voltage power MOS
This is because it has become clear that in FETs, on-resistance increases unless the area Sa of the opening of the high-resistance layer and the surrounding area T are increased. However, in a conductivity modulation type MOSFET, since the n-type layer undergoes conductivity modulation, the resistance is low, so there is no need to make the area of the opening as wide as in the power MO3FET.

As is clear from the above explanation, the present invention is a conductive modulation type M
When applied to OSFETs, it is possible to achieve a large effect that is completely different from when applied to power MOSFETs.

Further, in the above embodiment, the drain electrode is used as the source.

It was placed on the opposite side of the gate electrode. So-called vertical MO3
Although FETs have been described, the present invention can also be applied to lateral MOSFETs. FIG. 3 is a sectional view of a main part of the embodiment. There is an n-high resistance layer 32 on the p4'' four-layer type 1, and a p-type base diffusion layer 33.n is on the surface of this high resistance layer 32.
++ A source diffusion layer 34 is formed, and a channel region 38 is formed between the source diffusion layer 34 and the high resistance layer 32, and a gate insulation [! A gate electrode 36 is disposed through the gate electrode 35, and a source electrode 37 is disposed in contact with both the source diffusion layer 34 and the base diffusion layer 33. This basic structure is the same as the previous embodiment.

In this embodiment, an n-type layer 39 with a higher concentration is further formed on the surface of the high-resistance layer 32, and a p+-type layer 14 is formed on the surface of the n-type layer 39.
Two layers 40 are formed and a drain electrode 41 is provided thereon. By providing this n-type layer 39, when this conductivity modulation type MOSFET is in a forward blocking state, the extension of the depletion layer that occurs can be suppressed, and the width Log of the wafer opening of the high resistance 1132 can be reduced. I can do it. Also in this structure, the p-type base diffusion layer 33 is n-
By forming a pattern that completely surrounds the wafer opening of the high-resistance layer 32, the same effect as in the previous embodiment can be obtained.

Note that it is also possible to make the p++ layer 1131 in FIG. 3 an n+ type layer.

[Brief explanation of drawings]

1(a) to (d) are diagrams showing the configuration of a conductivity modulation type MOSFET according to one embodiment of the present invention, FIG. 2 is a diagram showing a diffusion layer pattern of a conductivity modulation type MOSFET according to another embodiment, and FIG. 3
The figure is a cross-sectional view of a conductivity modulation type MOSFET of another embodiment, and Figures 4 and 5 are conventional conductivity modulation type MOSFETs.
, FIG. 6 is a diagram showing the diffusion layer pattern of the conductivity modulation type MOSFET of FIG. 5, FIG. 7 is a perspective view of the same, and FIG.
The figure also shows experimental data showing the latching characteristics. 11... p+ type Todo 142 layer 12... n- type high resistance layer, 13... p type base diffusion layer, 14... n++ source diffusion layer, 15... p4'' type base diffusion layer, 16.
... Gate insulating film, 17... Polycrystalline silicon film gate electrode, 18... Source electrode, 19... Drain electrode, 20... A2 gate electrode, 21... Channel region. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 1 (C). Figure 3 Figure 4 Figure 8 Lt, <1JT1) Procedural amendment 1, Indication of case Patent application No. 59-204427 2, Title of invention Conductive modulation type MO5FET 3, Person making amendment Relationship with case Patent application Person (307) Toshiba Corporation 4, Agent 6, Target of amendment % 60.12f 7. Contents of amendment (1) rRaJ in lines 14 and 17 of page 7 of the specification is corrected to rReJ. (2) In the drawings, Figure 7 will be corrected as shown in the attached sheet.

Claims (3)

[Claims] (1) A base diffusion layer of a first conductivity type is formed in the high resistance layer portion of a semiconductor substrate wafer having a highly concentrated drain layer of a first conductivity type and a high resistance layer of a second conductivity type; A high concentration, second conductivity type source diffusion layer is formed within the base diffusion layer, and a gate electrode is formed via a gate insulating film on a base diffusion layer which becomes a channel region sandwiched between the source diffusion layer and the high resistance layer. , in a conductivity modulation type MOSFET in which a source electrode is formed in contact with both the source diffusion layer and the base diffusion layer, a plurality of openings exposed on the wafer surface of the high resistance layer are completely surrounded by the base diffusion layer; A conductivity modulation type MOSFET characterized by having an island shape. (2) The plurality of island-shaped high-resistance layer portions are each rectangular and arranged in a matrix, and a channel region is formed along each long side. Conductivity modulation type MOSFE according to item 1
T. (3) The gate electrode is formed by forming a polycrystalline silicon film on top of a polycrystalline silicon film continuously arranged in a mesh pattern so as to cover the plurality of island-like high resistance layer parts, and forming a stripe pattern on top of the polycrystalline silicon film. Claim 1, characterized in that a high concentration base diffusion layer is formed under the metal film to separate the plurality of high resistance layer portions. conductivity modulation type MOSFET.