JPS62176168A - Vertical MOS transistor - Google Patents

Abstract

PURPOSE:To prevent punch through between a source and drain, to obtain an arbitrary avalanche breakdown voltage and to provide a low ON-resistance vertical MOS transistor, by uniformly flowing a breakdown current through the bottom part of a second-conductivity type diffused layer when a high reverse voltage such as a surge voltage is applied. CONSTITUTION:A drain region has a conventional three-layer structure. A P-type diffused layer 5 is formed in an N<-> type low concentration layer 4. The bottom part T of the layer 5 reaches an N-type medium concentration layer 3. The acceptor impurity concentration of the layer can be variously adjusted in a range, which is higher than the impurity concentration of a P-type well region 6. Then, the region 6, which has the acceptor impurity concentration determined by the desired threshold voltage value of a vertical MOS transistor, is formed in the layers 5 and 4. An N<+> type source region 7, which has donor impurity concentration, is formed in the layer 5 and the region 6. Then a gate oxide film 8 is formed at a part on each of the layers 4 and 5 and the regions 6 and 7. A gate electrode layer 9 and an interlayer insulating film 10 are sequentially formed thereon. A source electrode 11 is formed on the entire surface. The withstanding voltage of the P-N junction at each place in such a vertical MOS transistor becomes the minimum at the bottom part T of the layer 5. Breakdown starts at this part, and its current flows uniformly through the bottom part T.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vertical MOS transistor, and more particularly to a vertical MO3) transistor that has been improved to prevent element destruction due to breakdown.

[Conventional technology]

In recent years, with the advent of power MOS transistors, the second
As shown in the figure, M is used as a switching element for power load B.
The OS transistor A has come into use, and it is recommended that it be applied to switching in front of various in-vehicle devices, for example, in vehicles.

In this type of MOS transistor, relatively high voltage
Due to the necessity of switching large currents, sufficient consideration must be given to the withstand voltage of the elements. For example, if power load B is an inductive load such as a motor or solenoid,
A high voltage surge occurs when the load current is interrupted. It is necessary to create a structure in which the element will not be destroyed even if a high voltage such as this surge voltage is applied in the opposite direction between the source and drain and breakdown occurs.

Therefore, conventionally, as shown in the cross-sectional view of a vertical MOS transistor in FIG. An N type medium concentration layer 3 having an impurity concentration lower than that of the N type temperature concentration base layer 2, and an N type medium concentration layer 3 laminated on the upper surface of this N type medium concentration layer 3 and having an impurity concentration lower than that of the N type medium concentration layer 3.
The drain region consisting of the type low concentration layer 4 has a three-layer structure.

A P-type well region 6 is formed in the N-type low concentration layer 4, and its bottom reaches the N-type medium concentration layer 3 and is bonded thereto. Next, an N' source region 7 electrically connected to the source electrode 11 is formed in the P-type well region 6.

Next, a gate electrode layer 9 is formed via the gate oxide film 8 in a state spanning both the N° type source region 7 and the N− type low concentration layer 4, and then the glabella insulating film 10 and the source electrode 1 are formed.
A vertical MOS transistor constructed by sequentially forming MOS transistors 1 and 1 is shown.

[Problem that the invention seeks to solve]

However, according to the vertical MOS transistor having the above structure, in FIG.
Because it reaches the concentration layer 3 in the mold, the withstand voltage of the PN junction at this part C decreases, so even if breakdown occurs, the breakdown will occur at this part C, and the breakdown current will flow inside the element. Although it is possible to uniformly flow the flow over a relatively wide area C without concentrating, the following problems exist when actually used for vehicles, for example.

Typically, the threshold voltage of a vertical MO3) transistor is 2 to 4.
The acceptor impurity concentration of the P-type well region 6 at this time needs to be about lXIQ''am-3.
Considering a V vertical MOS transistor, the donor impurity concentration of the N-type medium concentration layer 3 at this time is I x 10 l6a
The depletion layer E tends to spread toward the lower impurity concentration side, but if the impurity concentrations of the P-type well region 6 and the N-type medium concentration layer 3 are relatively close to each other, Therefore, when a reverse voltage is applied between the source and the drain, the depletion layer E spreads somewhat toward the N-type medium concentration layer 3 side, but it spreads almost uniformly, and the depletion layer E becomes below the avalanche breakdown voltage. At the voltage value, the depletion layer E finally becomes N
゛゛The source region 7 is reached, and punch-through occurs intensively from the reached portion.

Therefore, the present invention was devised in view of the above-mentioned problems, and it prevents punch-through between the source and drain without being concerned with the design of the impurity concentration of the P-type well region 6, which is determined based on the threshold voltage. Another object of the present invention is to provide a vertical MOS l-transistor that can obtain an arbitrary avalanche breakdown voltage and has a low ON resistance.

[Means for solving problems]

In order to achieve the above object, the present invention provides a highly doped first electrode electrically connected to one of a pair of main electrodes serving as a source or a drain.
A conductivity type base layer, a medium concentration first conductivity type semiconductor layer consisting of at least one layer laminated on the high concentration first conductivity type base layer, and a low concentration semiconductor layer laminated on the medium concentration first conductivity type semiconductor layer. a first conductivity type semiconductor layer, a second conductivity type semiconductor well region formed in the low concentration first conductivity type semiconductor layer, and a second conductivity type semiconductor well region and the second conductivity type semiconductor well region formed in the low concentration first conductivity type semiconductor layer; and the bottom reaches the medium concentration first conductivity type semiconductor layer, or the bottom thereof is closer to the medium concentration first conductivity type semiconductor layer side than the bottom of the second conductivity type semiconductor well region. a second conductivity type diffusion layer having an impurity concentration higher than that of the second thick conductivity type semiconductor well region; a high concentration first conductivity type semiconductor region electrically connected to the other of the pair of main electrodes; and a second conductivity type semiconductor region between at least the high concentration first conductivity type semiconductor region and the low concentration first conductivity type semiconductor layer. The gate electrode layer is formed on the semiconductor well region with an insulating film interposed therebetween.

[Effect]

According to the above-described means, when a breakdown occurs due to a high reverse voltage such as a surge being applied between the source and drain, the breakdown current is uniformly distributed at the bottom of the second conductivity type diffusion layer. flows to Further, the depletion layer generated between the second conductivity type diffusion layer and the low concentration first conductivity type semiconductor layer or the medium concentration first conductivity type semiconductor layer is because the impurity concentration of the second conductivity type diffusion layer is relatively high. It becomes difficult to spread toward the second conductivity type diffusion layer side.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to embodiments shown in the drawings. 1st
The figure shows a sectional view of an embodiment of the present invention.

In the figure, the drain region has a three-layer structure similar to the conventional one, with an N゛ type temperature concentration base layer 2 connected to the drain electrode 1, and a layer laminated on the top surface of this N° type temperature concentration base layer 2. an N-type intermediate concentration layer 3 having a donor impurity concentration lower than that of the N-type temperature basal layer 2; and an N-type low concentration layer 4 having a donor impurity concentration. And N-
A P-type diffusion layer 5 is formed in the low-concentration layer 4 , and its bottom T reaches the medium-concentration N-type layer 3 .

Incidentally, the acceptor impurity concentration of this P type diffusion layer 5 can be variously adjusted within a range higher than the impurity concentration of a P type well region 6, which will be described later. Next, a P-type well region 6 having an acceptor impurity concentration determined based on the desired threshold voltage of the vertical MOS transistor is formed in the P-type diffusion layer 5 and the N-type low concentration layer 4, the surface of which is P-type diffused. It is formed to cover the surface of layer 5. Next, an N source region 7 electrically connected to the source electrode 11 and having a high donor impurity concentration is formed in the P type diffusion layer 5 and the P type well region 6.

Next, a gate oxide film 8 is formed on the N- type low concentration layer 4, the P-type diffusion layer 5, the P-type well region 6, and a part of the N+-type source region 7, and a gate electrode is formed on the top of the gate oxide film 8. Layer 9 and interlayer insulating film 10 are sequentially formed. Then, a source electrode 11 is formed on the entire surface. The interlayer insulating film 10 and the source electrode 11 are formed on the gate electrode layer 9 except for the lead-out portion, and the source electrode 11 is formed in the N' source region 7, the P-type diffusion layer 5 therebetween, and the P-type well region. Electrically connected to 6.

In a vertical MOS transistor configured as described above, when a high reverse voltage such as a surge is applied between the source and drain, P Since the breakdown voltage of the PN junction at the bottom T of the type diffusion layer 5 is the lowest, breakdown occurs from this bottom T, and the breakdown current flows uniformly through the bottom T, so the breakdown current flows locally concentrated. , it is possible to prevent the device from being destroyed.Here, the reason why the breakdown voltage at the bottom T is the lowest is because the impurity concentration in the N-type medium concentration layer 3 is higher than the impurity concentration in the N-type low concentration layer 4. In addition, due to the properties of the depletion layer mentioned earlier, the depletion layer generated by the high reverse voltage does not spread much in the N-type medium concentration layer 3, and becomes thinner than other parts. That is, the electric field is concentrated at the bottom T.

Since the impurity concentration of the P-type diffusion layer 5 is relatively high, the depletion layer at the bottom T does not spread much toward the P-type diffusion layer 5 side, and the depletion layer does not reach the N+ type source region 7. Therefore, punch-through between the source and drain can be prevented. The impurity concentration of the P-type diffusion layer 5 can be arbitrarily adjusted within a range that is higher than the impurity concentration of the P-type well region 6, so as to prevent punch-through and to obtain a desired breakdown voltage. Designed to.

Furthermore, since the drain region has a three-layer structure and the region with low impurity concentration can be made relatively narrow, current flows easily and the resistance during operation of the vertical MO3) transistor increases.
In other words, the value of ON resistance can be reduced, and vertical MO
3) The switching performance of transistors can be improved.

It should be noted that the present invention is not limited to the above embodiments, and can be modified in various ways as described below.

(1) In the above embodiment, the bottom T of the P-type diffusion layer 5 reaches the N-type medium concentration layer 3, but it does not have to reach the N-type intermediate concentration layer 3, and the desired 7-balancier breakdown voltage can be obtained and punch-through will not occur. It is sufficient if they are close enough to each other. Here, if the bottom T does not reach the N-type medium concentration layer 3, a depletion layer is generated between the P-type diffusion layer 5 and the N-type low concentration N4, but when the width of the depletion layer widens, the depletion layer The layer reaches the N-type medium concentration layer 3, and the width of the depletion layer becomes narrow at the bottom T, similar to the above embodiment, so that the same effect can be obtained.

(2) As shown in the cross-sectional view of another embodiment in FIG.
An N-type scattering layer 12 having the same conductivity type may be formed. By forming the N" type diffusion layer 12, vertical MO3)
When the transistor operates, the current flowing through the N-type scattering layer 12
It is possible to further reduce the ON resistance. still,
Although the bottom of the NWE diffused layer 12 does not reach the N-type medium concentration N3 in the figure, it may reach the N-type medium concentration layer 3.

(3) Although the above-mentioned embodiment shows an N-type channel vertical MOS transistor, the present invention can also provide similar effects to a P-type channel vertical MO3) transistor.

(4) Although the drain region in the above embodiment has a three-layer structure, the N-type medium concentration layer 3 may be divided into a plurality of layers, and the drain region may have a multi-layer structure of three or more layers.

(5) The above example shows only the inside of the element of a vertical MOS transistor, but when considering the withstand voltage of the element, the peripheral area of the element is also a problem, and the peripheral area of the element is shown in the cross-sectional view of Fig. 5. As shown in the sectional view of FIG. The P-type diffusion layer 5 may be formed in the same process as in the above embodiment, and as shown in the cross-sectional view of FIG. It may be formed into Note that the same reference numerals in FIGS. 5 to 7 refer to the same components as in the above embodiment, and the explanation thereof will be omitted. Here, in the embodiment shown in FIG. 5, the breakdown voltage of the peripheral part F of the element is larger than the breakdown voltage inside the element, so breakdown occurs only inside the element, and in the embodiment of FIGS. The breakdown voltage at the bottom of the P-type diffusion layer 5 of F is
Since the breakdown voltage is equal to the withstand voltage inside the element, breakdown occurs simultaneously inside the element and at the periphery F of the element, and breakdown occurs from a wider area, resulting in better protection of the element.

〔Effect of the invention〕

As described above, in the vertical MO3) transistor configured according to the present invention, punch-through between the source and drain can be prevented without being concerned with the element design determined by the threshold voltage of the vertical MOS transistor. , an arbitrary avalanche breakdown voltage can be obtained, and a vertical MOS transistor with low ON resistance can be provided, which is an excellent effect.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the structure of an embodiment of a vertical MOS transistor of the present invention, FIG. 2 is a switch-notching circuit diagram using a MOS transistor, and FIG. 3 is a vertical MOS transistor of the present invention.
) A cross-sectional view showing the structure of another embodiment of the transistor; FIG. 4 is a cross-sectional view showing the structure of a conventional vertical MO3 transistor;
5 to 7 are cross-sectional views showing the device periphery of the vertical MO3 transistor of the present invention. DESCRIPTION OF SYMBOLS 1... Drain electrode, 2... N-type warm concentration basal layer 3... N-type medium concentration layer, 4... N-type low concentration layer, 5...
...P type diffusion layer, 6...P type well region, 7...N
°-type source region, 8... gate oxide film, 9... gate electrode layer.

Claims (1)

[Scope of Claims] A heavily doped first conductivity type base layer electrically connected to one of a pair of main electrodes serving as a source or a drain; a medium doped base layer laminated on the high concentration first conductivity type base layer and comprising at least one layer; a first conductivity type semiconductor layer; a low concentration first conductivity type semiconductor layer stacked on the medium concentration first conductivity type semiconductor layer; a second conductivity type formed in the low concentration first conductivity type semiconductor layer; a semiconductor well region; formed in the second conductivity type semiconductor well region and the low concentration first conductivity type semiconductor layer, the bottom of which reaches the medium concentration first conductivity type semiconductor layer; is closer to the intermediate concentration first conductivity type semiconductor layer than the bottom of the second conductivity type semiconductor well region, and has an impurity concentration higher than that of the second conductivity type semiconductor well region. a second conductivity type diffusion layer; a high concentration first conductivity type semiconductor region formed in the second conductivity type semiconductor well region and electrically connected to the other of the pair of main electrodes; and at least the high concentration first conductivity type semiconductor; A vertical MOS transistor comprising a gate electrode layer formed on the second conductivity type semiconductor well region between the region and the low concentration first conductivity type semiconductor layer with an insulating film interposed therebetween.