JP2014187308A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently manufacture a semiconductor device having improved mounting strength.SOLUTION: A semiconductor device manufacturing method comprises: forming trenches 4T on top faces 4a of leads 4 of a lead frame LF so as to stride over boundaries BL between the leads 4 and frame parts LFs; mounting a semiconductor chip on a chip mounting part of the lead frame LF and electrically connecting the semiconductor chip with the leads 4; and subsequently forming a body resin part 6mb for encapsulating the semiconductor chip and the leads 4 so as to expose a part of the top faces 4a of the leads 4. In forming of the body resin part 6mb, an in-dam resin part is formed between neighboring leads among the plurality of leads 4 and the frame part LFs and an in-trench resin part 6t is formed inside each trench 4T. The semiconductor device manufacturing method further comprises: irradiating the in-dam resin part and the in-trench resin part 6t with laser beams 55 from the top face 4a side to remove the in-dam resin part and the in-trench resin part 6t; and forming a metal film on a part exposed from the body resin part 6mb by a plating method.

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, for example, a technique effective when applied to a semiconductor device in which a lead serving as an external terminal is exposed on a lower surface of a sealing body.

  Japanese Patent Laying-Open No. 2005-191240 (Patent Document 1) describes a semiconductor device in which a plurality of leads are exposed on the lower surface of a sealing body. Japanese Patent Application Laid-Open No. H10-228561 describes that a recess is formed on the mounting surface of the lead.

  Japanese Unexamined Patent Application Publication No. 2008-112961 (Patent Document 2) and US Pat. No. 8017447 (Patent Document 3) describe a method of manufacturing a semiconductor device in which a recess is formed on a mounting surface of a lead. .

  Further, International Publication No. 2011/004746 (Patent Document 4) describes a semiconductor device in which each of a plurality of leads exposed on the lower surface of a sealing body protrudes outward in a plan view.

JP 2005-191240 A JP 2008-112961 A (FIGS. 6A to 6E) US Patent No. 8017447 (FIG. 3A to FIG. 3D) International Publication No. 2011/004746 (FIGS. 29 and 30)

  As a package mode of a semiconductor device, there is a package in which a lead which is an external terminal is exposed on a lower surface side (that is, a mounting surface side) of a sealing body. Examples of such a package include a QFN (Quad Flat Non-leaded package) type and a SON (Small Outline Non-leaded package) type. As described above, when a package in which leads are exposed on the lower surface side of the sealing body is mounted on a mounting substrate, the package is mounted by bonding a bonding material such as solder to the exposed surface of the leads.

  However, when solder (joining material) is joined only to the lower surface of the lead, the mounting strength is lower than that of a QFP (Quad Flat Package) type semiconductor device. Therefore, the inventor of the present application has studied a technique for improving the mounting strength of the semiconductor device in which the lead is exposed on the lower surface side of the sealing body. Also, a manufacturing technique for efficiently manufacturing a semiconductor device with improved mounting strength of the semiconductor device was examined.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  In a method of manufacturing a semiconductor device according to an embodiment, a lead frame having a mounting surface and an opposite surface opposite to the mounting surface, and a plurality of leads arranged next to the chip mounting portion are connected to a frame portion Prepare. Here, a groove portion is formed on the opposite surface of each of the plurality of leads so as to straddle the boundaries between the plurality of leads and the frame portion. In addition, after mounting a semiconductor chip on the chip mounting portion and connecting to the plurality of leads, the semiconductor chip and the plurality of leads are arranged so that a part of the opposite surface of each of the plurality of leads is exposed. A main body resin part to be sealed is formed. At this time, an in-dam resin portion is formed between the adjacent leads of the plurality of leads and the frame portion, and an in-groove resin portion is formed inside the groove portion. In addition, the resin part in the dam and the resin part in the groove are irradiated with a laser from the opposite surface side to remove the resin part in the dam and the resin part in the groove, and then the part exposed from the main body resin part. A metal film is formed.

  According to the one embodiment, a semiconductor device with improved mounting strength can be efficiently manufactured.

It is a top view of the semiconductor device which is one embodiment. It is a bottom view which shows the mounting surface side of the semiconductor device shown in FIG. It is sectional drawing along the AA line of FIG. FIG. 2 is a perspective plan view showing an internal structure of the semiconductor device in a state where the sealing body shown in FIG. 1 is seen through. FIG. 2 is an enlarged plan view showing a part around a lead shown in FIG. 1 in an enlarged manner. It is an expanded sectional view along the AA line of FIG. It is an expanded sectional view along the BB line of FIG. It is an expanded sectional view along CC line of FIG. FIG. 6 is an enlarged plan view showing a state where the semiconductor device shown in FIG. 5 is mounted on a mounting substrate. It is an expanded sectional view along the AA line of FIG. It is an expanded sectional view along the BB line of FIG. It is an expanded sectional view along CC line of FIG. It is explanatory drawing which shows the assembly flow of the semiconductor device shown in FIGS. It is a top view which shows the whole lead frame structure prepared at the base-material preparation process shown in FIG. FIG. 15 is an enlarged plan view of one of a plurality of device forming units illustrated in FIG. 14. FIG. 16 is an enlarged plan view showing a part of a plurality of leads shown in FIG. 15 in an enlarged manner. It is an expanded sectional view along the AA line of FIG. It is an expanded sectional view along the BB line of FIG. It is an expanded sectional view along the CC line of FIG. FIG. 16 is an enlarged plan view showing a state where a semiconductor chip is mounted on the die pad shown in FIG. 15 via a bonding material. It is an expanded sectional view along the AA line of FIG. FIG. 21 is an enlarged plan view showing a state where the semiconductor chip shown in FIG. 20 and a plurality of leads are electrically connected through wires. It is an expanded sectional view along the AA line of FIG. FIG. 23 is a plan view showing a state in which a sealing body is formed in the device formation portion of the lead frame shown in FIG. 22. It is an expanded sectional view along the AA line of FIG. It is sectional drawing which shows the state which has arrange | positioned the lead frame in the molding die in the sealing process shown in FIG. FIG. 25 is an enlarged plan view showing an enlarged periphery of some of the leads shown in FIG. 24. It is an expanded sectional view along the AA line of FIG. It is an enlarged plan view which shows the state which removed the resin part in a dam shown in FIG. 27, and the resin part in a groove | channel. FIG. 30 is an enlarged cross-sectional view schematically showing a state in which resin is being removed by laser irradiation in a cross section taken along line AA shown in FIG. 29. FIG. 30 is an enlarged cross-sectional view schematically showing a state in which resin is being removed by laser irradiation in a cross section taken along line BB shown in FIG. 29. FIG. 31 is an enlarged cross-sectional view showing a state in which a metal film is formed on the exposed surface of the lead frame shown in FIG. 30 from the resin. It is explanatory drawing which shows the outline | summary of the plating process by the electroplating method. FIG. 14 is an enlarged plan view showing a state in which each device forming unit is singulated in the singulation process shown in FIG. 13. FIG. 14 is an enlarged cross-sectional view showing a state in which the boundary between the lead and the frame portion is cut in the singulation process shown in FIG. 13. FIG. 36 is a perspective view showing the shape of the upper die shown in FIG. 35. FIG. 36 is an enlarged cross-sectional view showing a state in which the boundary between the lead and the frame portion is cut in the singulation process of the embodiment which is a modified example with respect to FIG. 35; FIG. 38 is an enlarged plan view showing a state where the semiconductor device shown in FIG. 37 is mounted on a mounting substrate. It is an expanded sectional view along the AA line of FIG. It is an expanded sectional view along the BB line of FIG. It is an expanded sectional view along CC line of FIG. It is an expanded sectional view which shows the modification with respect to FIG.

(Description format, basic terms, usage in this application)
In the present application, the description of the embodiment will be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Regardless of the front and rear, each part of a single example, one is a part of the other, or a part or all of the modifications. In principle, repeated description of similar parts is omitted. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It does not exclude things that contain. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but includes a SiGe (silicon-germanium) alloy, other multi-component alloys containing silicon as a main component, and other additives. Needless to say, it is also included. Moreover, even if it says gold plating, Cu layer, nickel / plating, etc., unless otherwise specified, not only pure materials but also members mainly composed of gold, Cu, nickel, etc. Shall be included.

  In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  Moreover, in each figure of embodiment, the same or similar part is shown with the same or similar symbol or reference number, and description is not repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, hatching or a dot pattern may be added in order to clearly indicate that it is not a void or to clearly indicate the boundary of a region.

(Embodiment 1)
The technology described in the following embodiments can be applied to various package type semiconductor devices in which the leads are exposed on the lower surface side of the sealing body. In this embodiment, as an example, an embodiment applied to a QFN type semiconductor device in which a plurality of leads which are external terminals are exposed from the sealing body on the lower surface (mounting surface) of the sealing body will be described. . 1 is a top view of the semiconductor device of the present embodiment, FIG. 2 is a bottom view showing the mounting surface side of the semiconductor device shown in FIG. 1, and FIG. 3 is a cross-sectional view taken along line AA of FIG. . FIG. 4 is a perspective plan view showing the internal structure of the semiconductor device in a state where the sealing body shown in FIG. 1 is seen through.

<Semiconductor device>
First, the outline | summary of a structure of the semiconductor device 1 of this Embodiment is demonstrated using FIGS. The semiconductor device 1 according to the present embodiment is mounted on a die pad (chip mounting portion, tab) 2 (see FIGS. 2 to 4) and an adhesive 7 (see FIGS. 3 and 4) on the die pad 2. And a semiconductor chip 3 (see FIGS. 3 and 4). Further, the semiconductor device 1 includes a plurality of leads (terminals and external terminals) 4 arranged around the semiconductor chip 3 (die pad 2), and a plurality of pads (electrode pads and bonding pads) PD of the semiconductor chip 3 (FIG. 4). And a plurality of wires (conductive members) 5 (see FIG. 4) for electrically connecting the leads 4 and the leads 4 respectively. A plurality of suspension leads TL are connected to the die pad 2. The semiconductor device 1 also includes a semiconductor chip 3, a plurality of wires 5, and a sealing body (resin body) 6 that seals part of the plurality of leads 4.

<Appearance structure>
First, the external structure of the semiconductor device 1 will be described. The planar shape of the sealing body (resin body) 6 shown in FIG. The sealing body 6 has an upper surface 6a, a lower surface (back surface, mounting surface) 6b (see FIG. 2) opposite to the upper surface 6a, and a side surface 6c located between the upper surface 6a and the lower surface 6b. ing. As shown in FIG. 3, the side surface 6c is an inclined surface that is not orthogonal to the upper surface 6a and the lower surface 6b.

  Here, the corner portion 6p of the sealing body 6 refers to a peripheral area of a corner that is an intersection of any two sides (two main sides) intersecting among the four sides (four main sides) of the sealing body 6. Contains. Strictly speaking, as shown in FIGS. 1 and 2, the corner 6 p of the sealing body 6 is partially chamfered, so that the intersection of the main sides is more than the corner 6 p of the sealing body 6. Is also arranged outside. However, since the chamfered portion is sufficiently small compared to the length of the main side, in the present application, the center of the chamfered portion is regarded as the corner of the sealing body 6 for description. Specifically, the corner portion 6p is a region indicated by a dot pattern in FIGS. 1 and 2, and its boundary is defined as follows. That is, in the semiconductor device 1, a plurality of leads 4 are arranged along the four sides of the sealing body 6. Of the plurality of leads 4 arranged along each side, a region up to the lead 4 arranged next to the corner (center of the chamfered portion) of the sealing body 6 is defined as a corner portion. In this application, when it is described as the corner 6p of the sealing body 6 or the corner of the cavity, it is used as the same meaning and contents as described above, except where it is clearly stated that it is used with a different meaning and contents.

  As shown in FIGS. 1 and 2, in the semiconductor device 1, a plurality of leads 4 are arranged along each side (each main side) of the sealing body 6 having a square planar shape. The plurality of leads 4 are each made of a metal material, and in the present embodiment, for example, a metal film made of nickel (Ni) on the surface of a base material made of, for example, copper (Cu) or copper (Cu) (not shown). It consists of a laminated metal member formed. In the example shown in FIGS. 1 and 2, for example, a plurality of leads 4 having a width of 0.2 mm are arranged along each side at an arrangement pitch (inter-center line distance) of 0.5 mm. Further, the thickness of the lead 4 is, for example, 0.2 mm.

  The lower surfaces of the leads 4 (the lower surface of the inner portion 4 i and the lower surface of the outer portion 4 o shown in FIG. 3) are exposed from the sealing body 6 on the lower surface 6 b of the sealing body 6. Further, some of the leads 4 (outer portion 4 o) are also exposed from the side surface 6 c of the sealing body 6. Specifically, as shown in FIG. 3, a part (outer portion 4 o) of each of the plurality of leads 4 formed along each side of the sealing body 6 is a side surface 6 c (side) of the sealing body 6. Projecting outward from In the example shown in FIG. 3, it protrudes outward from the side surface 6c of the sealing body 6 by about 0.3 mm, for example.

  Although details will be described later, when the semiconductor device 1 is mounted on a mounting board (not shown), the leads 4 and terminals on the mounting board side are electrically connected via a connecting material such as solder. Therefore, by exposing the plurality of leads 4 from the side surface 6c in addition to the lower surface 6b of the sealing body 6, the bonding area between the connecting material and the lead 4 is increased, so that the bonding strength can be improved.

  In addition, as shown in FIGS. 1 to 3, the surface of the exposed portion of the plurality of leads 4 (and the lower surface, the upper surface, and the side surface of the outer portion 4o) is connected to the lead 4 and the solder material (joining material) during mounting. In order to improve the property (wetting property), for example, a metal film SD made of solder is formed. Thereby, when a solder material is used as a connecting material at the time of mounting, the wettability of the solder material can be further improved.

  The metal film SD (solder material) of the present embodiment is made of, for example, a so-called lead-free solder that does not substantially contain lead (Pb), for example, only tin (Sn), tin-bismuth (Sn-Bi). Or tin-copper-silver (Sn-Cu-Ag). Here, the lead-free solder means a lead (Pb) content of 0.1 wt% or less, and this content is defined as a standard of the RoHS (Restriction of Hazardous Substances) directive. Hereinafter, in the present embodiment, when a solder material or a solder component is described, it indicates lead-free solder unless otherwise specified.

  As shown in FIG. 2, the lower surface 2 b of the die pad 2 is exposed from the sealing body 6 on the lower surface 6 b of the sealing body 6. That is, the semiconductor device 1 is a die pad exposed type (tab exposed type) semiconductor device. The die pad 2 is made of a metal material having a higher thermal conductivity than the sealing body 6. In the example shown in FIG. 2, for example, nickel (Cu) is formed on the surface of a base material made of copper (Cu) or copper (Cu). It consists of a laminated metal member on which a metal film (not shown) made of Ni) is formed. As described above, the die pad exposed semiconductor device is a semiconductor in which the die pad 2 is not exposed by exposing a metal member (die pad 2) such as copper (Cu) having a higher thermal conductivity than that of the sealing body 6. Compared with the device, the heat dissipation of the package can be improved. 2 and 3, the lower surface 2b of the die pad 2 is formed with a metal film SD that functions as a bonding material at the time of mounting, and covers the lower surface of the substrate. The metal film SD is a plating film (solder film) formed by, for example, a plating method as described above.

  As shown in FIGS. 1 and 2, in the semiconductor device 1, a part of the suspension lead TL is exposed from the sealing body 6 outside the corner portion 6 p of the sealing body 6. Specifically, as shown in FIG. 4, one end portion of the suspension lead TL is connected to the die pad 2 (formed integrally), and the other end portion (exposed portion 11) is exposed from the sealing body 6. ing. Since the suspension leads TL are formed integrally with the die pad 2, the suspension leads TL are made of the same metal material as that of the die pad 2 including the exposed portions (fins and corner leads) 11. By exposing a part of the suspension lead TL from the sealing body 6 in this way, when the semiconductor device 1 is mounted on a mounting board (not shown), the exposed portion 11 can be joined to a terminal on the mounting board side. . Thereby, the mounting strength of the semiconductor device 1 can be improved. In the example shown in FIGS. 1 to 3, a metal film SD made of, for example, solder is formed on the exposed surface of the exposed portion 11. Thereby, the mounting strength of the semiconductor device 1 can be further improved. However, as a modification, a structure in which the exposed portion of the suspension lead TL as shown in FIG. 2 is not provided can be employed.

<Internal structure>
Next, the internal structure of the semiconductor device 1 will be described. As shown in FIG. 4, the upper surface (chip mounting surface) 2 a of the die pad 2 has a quadrangular shape in plan view. In the present embodiment, for example, it is a square. In the example shown in FIG. 4, the outer size (planar size) of the die pad 2 is larger than the outer size of the semiconductor chip 3 (planar size of the back surface 3b). As described above, the semiconductor chip 3 is mounted on the die pad 2 having an area larger than the outer size, and the lower surface 2b of the die pad 2 is exposed from the sealing body 6, thereby improving heat dissipation.

  Further, as shown in FIG. 4, the semiconductor chip 3 is mounted on the die pad 2. The semiconductor chip 3 is mounted at the center of the die pad 2. As shown in FIG. 5, the semiconductor chip 3 is mounted on the die pad 2 via the adhesive 7 with the back surface 3 b facing the top surface 2 a of the die pad 2. That is, it is mounted by a so-called face-up mounting method in which the surface (back surface 3b) opposite to the surface (main surface) 3a on which the plurality of pads PD are formed is opposed to the chip mounting surface (upper surface 2a). This adhesive material 7 is an adhesive material for die-bonding the semiconductor chip 3, and for example, an epoxy-based thermosetting resin can be used.

  As shown in FIG. 4, the planar shape of the semiconductor chip 3 mounted on the die pad 2 is a quadrangle. In the present embodiment, for example, it is a square. As shown in FIG. 3, the semiconductor chip 3 includes a front surface (main surface, upper surface) 3a, a back surface (main surface, lower surface) 3b opposite to the front surface 3a, and a space between the front surface 3a and the back surface 3b. And a side surface 3c. As shown in FIGS. 3 and 4, a plurality of pads (bonding pads) PD are formed on the surface 3a of the semiconductor chip 3, and in the present embodiment, the plurality of pads PD are provided on each surface 3a. It is formed along the side. Although not shown, the main surface of the semiconductor chip 3 (specifically, a semiconductor element formation region provided on the upper surface of the base material (semiconductor substrate) of the semiconductor chip 3) includes a plurality of semiconductor elements (circuit elements). Is formed. In addition, the plurality of pads PD are connected to each other via wiring (not shown) formed in a wiring layer disposed inside the semiconductor chip 3 (specifically, between the surface 3a and a semiconductor element formation region not shown). It is electrically connected to the semiconductor element.

  The semiconductor chip 3 (specifically, the base material of the semiconductor chip 3) is made of, for example, silicon (Si). In addition, an insulating film is formed on the surface 3a to cover the base material and wiring of the semiconductor chip 3, and each surface of the plurality of pads PD is exposed from the insulating film in the opening formed in the insulating film. doing. The pad PD is made of metal, and in the present embodiment, is made of, for example, aluminum (Al) or an alloy layer mainly composed of aluminum (Al).

  As shown in FIG. 4, for example, a plurality of leads 4 made of the same copper (Cu) as the die pad 2 are arranged around the semiconductor chip 3 (specifically, around the die pad 2). A plurality of electrode pads (bonding pads) PD formed on the surface 3a of the semiconductor chip 3 are composed of a plurality of leads 4 (inner portions 4i) positioned inside the sealing body 6 and a plurality of wires (conductive members). ) 5 are electrically connected to each other. The wire 5 is made of, for example, gold (Au), a part (for example, one end) of the wire 5 is bonded to the electrode pad PD, and the other part (for example, the other end) is bonded to the bonding region of the inner portion 4i. It is joined. In addition, although illustration is abbreviate | omitted, the plating film is formed in the surface (specifically the surface of the plating film which consists of nickel (Ni)) of the bonding area | region of the inner part 4i. The plating film is made of, for example, silver (Ag) or gold (Au). By forming a plating film made of silver (Ag) or gold (Au) on the surface of the bonding region of the inner portion 4i, the bonding strength with the wire 5 made of gold (Au) can be improved.

  As shown in FIG. 4, a plurality of suspension leads TL are connected (linked) to the die pad 2. Each of the suspension leads TL has one end connected to a corner (corner) of the die pad 2. Each of the plurality of suspension leads TL has the other end extending toward the corner 6p (see FIG. 1) of the sealing body 6 and exposed from the sealing body 6 outside the corner 6p.

  By extending the suspension leads TL toward the corners 6p of the sealing body 6 (see FIG. 1), the arrangement of the leads 4 arranged along each side (each main side) of the sealing body 6 is changed. Since it can arrange | position without inhibiting, the number of the leads 4, ie, the number of terminals of the semiconductor device 1, can be increased.

  Further, as shown in FIG. 4, a portion (sealing portion) connecting the die pad 2 and the exposed portion 11 of the suspension lead TL is subjected to half etching processing from the lower surface side, and the lower surface side is also sealed 6. It is sealed by. Thereby, since the suspension lead TL and the sealing body 6 can be firmly fixed, it is possible to prevent the suspension lead TL from falling off the sealing body 6.

<Detailed structure of lead>
Next, the detailed structure of the lead 4 shown in FIGS. FIG. 5 is an enlarged plan view showing a part of the periphery of the lead shown in FIG. 6 is an enlarged sectional view taken along line AA in FIG. 5, FIG. 7 is an enlarged sectional view taken along line BB in FIG. 5, and FIG. 8 is an enlarged view taken along line CC in FIG. It is sectional drawing. FIG. 5 shows an enlarged view of three leads 4 arranged in the X direction among the plurality of leads 4 shown in FIG. Accordingly, in the following description of the structure of the lead 4, the Y direction in which the lead 4 extends is the length direction of the lead 4, and the X direction orthogonal to the Y direction is orthogonal to the width direction of the lead 4 and the XY plane. The Z direction to be performed will be described as the thickness direction of the lead 4.

  As shown in FIGS. 5 to 8, the lead 4 is the same as the upper surface 2 a (see FIG. 3) of the die pad 2 (see FIG. 3), and faces the Z direction (see FIGS. 3 and 6). It has the lower surface 4b (refer FIGS. 6-8) on the opposite side to 4a. The lead 4 is located between the upper surface 4a and the lower surface 4b, and extends to the outside of the side surface 6c (see FIG. 5) of the sealing body 6 and the side surface 4c1 and the side surface 4c2 (FIGS. 5, 7, and 5). 8). Further, the lead 4 has a front end surface (end portion) 4 ot (see FIGS. 5 and 6) disposed at a position farthest from the side surface 6 c of the sealing body 6. The front end surface 4 ot is disposed on the opposite side of the inner side surface (end portion) 4 it (see FIG. 6) facing the die pad 2 (see FIG. 3).

  Further, when the sealing body 6 is formed by the so-called transfer mold method, immediately after the sealing body 6 is formed, the in-dam resin portion 6d remains between the adjacent leads 4 (see FIG. 5). However, as shown in FIG. 5, in this embodiment, most of the in-dam resin portion 6d between the adjacent leads 4 is removed. The reason why a part of the in-dam resin portion 6d remains as shown in FIG. 5 will be described later. For this reason, the side surface 4 c 1 and the side surface 4 c 2 of the lead 4 are exposed from the resin constituting the sealing body 6. 7 and 8, a metal film SD is formed so as to surround the upper surface 4a, the lower surface 4b, and the side surfaces 4c1, 4c2 of the lead 4. Thus, by exposing the side surfaces 4c1 and 4c2 from the resin in addition to the lower surface 4b of the outer portion 4o of the lead 4, the side surfaces 4c1 and 4c2 can be used as a bonding surface at the time of mounting. For this reason, compared with the semiconductor device with which the side surfaces 4c1 and 4c2 are covered with resin, the mounting strength can be improved.

  Further, as shown in FIG. 6, a part of the tip surface 4 ot of the lead 4 is exposed from the metal film SD. Although details will be described later, in the manufacturing process of the semiconductor device 1, when the lead 4 is cut and the tip surface 4 ot is formed after forming the metal film SD, the tip surface 4 ot is exposed from the metal film SD. Further, in the manufacturing process of the semiconductor device 1, when a cutting jig (not shown) is pressed and cut from the lower surface 4b side to the upper surface 4a side of the lead 4, as shown in FIG. The part SDt formed by partly dragging the metal film SD to the cutting die is formed. A part of the front end surface 4ot on the lower surface 4b side is covered with a portion SDt extending from the line of intersection with the lower surface 4b toward the upper surface 4a2.

  As shown in FIGS. 7 and 8, the lead 4 has a trapezoidal shape in a cross-sectional view in the X direction orthogonal to the extending direction of the lead 4. In other words, in the lead 4, the width of the lower surface 4b (that is, the length in the X direction) is larger than the width of the upper surface 4a. In other words, the area of the lower surface 4b of the lead 4 is larger than the area of the upper surface 4a in plan view. Thus, by making the cross-sectional shape of the lead 4 a regular trapezoid, the distance between the adjacent leads 4 can be reduced and the area of the mounting surface of each lead 4 can be increased. Although details will be described later, when removing the resin (resin in the dam) embedded between the adjacent leads 4 by irradiating with a laser, the side surfaces 4c1 and 4c2 of the lead 4 are inclined surfaces. The side surfaces 4c1 and 4c2 can be easily irradiated with laser light.

  Further, the outer portion 4o of the lead 4 has a step portion 4D on the distal end surface 4ot side. In the example shown in FIG. 6, the outer part 4o of the lead 4 is lower than the flat part (part) 4F having the upper surface 4a1 located at the same height as the upper surface 4a of the inner part 4i and the upper surface 4a of the inner part 4i. And a step portion (part) 4D located on the lower surface 4b side. As can be seen by comparing FIG. 7 and FIG. 8, the stepped portion 4D is thinner than the portion other than the stepped portion 4D. In the example shown in FIG. 8, for example, the thickness T1 of the stepped portion 4D is about half of the thickness T2 of the portion shown in FIG. 7, and is about 0.1 mm, for example. That is, the upper surface 4a2 of the step portion 4D is located at a height between the upper surface 4a1 and the lower surface 4b of the flat portion 4F other than the step portion 4D.

  On the other hand, as shown in FIG. 6, the lower surface 4b of the lead 4 is located at the same height as the inner portion 4i, the flat portion 4F of the outer portion 4o, and the lower surface 4b of the step portion 4D. In other words, no step is provided on the lower surface 4 b side of the lead 4, which is a flat surface. Note that that the lower surface 4b is a flat surface means that the flatness is higher than that of the upper surface 4a, and does not exclude, for example, a case where fine irregularities are formed on the lower surface 4b.

  In the semiconductor device 1 of the present embodiment, the mounting strength of the semiconductor device 1 can be improved by providing the step portion 4D in the outer portion 4o of the lead 4. The reason will be described below. FIG. 9 is an enlarged plan view showing a state where the semiconductor device shown in FIG. 5 is mounted on a mounting substrate. 10 is an enlarged cross-sectional view taken along line AA in FIG. 9, FIG. 11 is an enlarged cross-sectional view taken along line BB in FIG. 9, and FIG. 12 is an enlarged view taken along line CC in FIG. It is sectional drawing. 9 to 12, when the semiconductor device 1 shown in FIGS. 5 and 6 is mounted on the mounting substrate 20, the lead 4 and the terminal 21 of the mounting substrate 20 are electrically connected via the solder material SDb. Indicates the state.

  A mounting substrate (motherboard or wiring substrate) 20 shown in FIG. 9 has an upper surface (mounting surface) 20a that is an electronic component mounting surface, and the semiconductor device 1 is mounted on the upper surface 20a. A plurality of terminals 21 which are terminals on the mounting board side are arranged on the upper surface 20a.

  As shown in FIG. 10, the lead 4 of the semiconductor device 1 and the terminal 21 of the mounting substrate 20 are electrically connected via a solder material SDb. The solder material SDb is a conductive joint material made of lead-free solder, and a part thereof is joined to the terminal 21 and the other part is joined to the lower surface 4 b of the lead 4. In order to electrically connect and fix the lead 4 and the terminal 21 via the solder material SDb, the solder material SDb is heated and melted to be joined to the lead 4 and the terminal 21 which are the joined portions. Reflow processing is performed. In this reflow process, as described with reference to FIGS. 6 to 8, when the metal film SD is formed on the exposed surface of the lead 4, the wettability of the solder material SDb can be improved. When a solder material is used as the metal film SD, as shown in FIG. 10, the solder component contained in the metal film SD is integrated with the solder material SDb.

  When the reflow process is performed, the molten solder material SDb is deformed as shown in FIGS. 10 to 12 under the influence of the surface tension and gravity of the solder material itself. First, in the flat part 4F of the outer part 4o, as shown in FIG. 11, the solder material SDb scoops up along the side surfaces 4c1 and 4c2 of the lead 4, and a solder fillet is formed. However, since the thickness T2 of the flat portion 4F is as thick as about 0.2 mm, for example, the solder material SDb does not reach the upper surface 4a1 of the flat portion 4F, and part of the side surfaces 4c1, 4c2 is exposed from the solder material SDb. It becomes a state. Further, the metal film SD formed on the upper surface 4a1 of the flat portion 4F remains on the upper surface 4a1 of the flat portion 4F in a state separated from the solder material SDb.

  Further, in the step portion 4D of the outer portion 4o, as shown in FIG. 12, the solder material SDb crawls up along the side surfaces 4c1 and 4c2 of the lead 4, and a solder fillet is formed. Further, since the thickness T1 of the step portion 4D is smaller than the thickness T2 (see FIG. 11) of the flat portion 4F (see FIG. 11), the solder material SDb can reach the upper surface 4a2 of the step portion 4D. As a result, in the step portion 4D, the solder material SDb integrated so as to continuously surround the lower surface 4b, the upper surface 4a2, the side surface 4c1, and the side surface 4c2 is formed. For this reason, in the step portion 4D, it is difficult for the bonding surface between the lead 4 and the solder material SDb to be peeled off, so that the mounting strength of the lead 4 can be improved.

  By the way, if the amount of the solder material disposed on the terminal 21 is increased when mounting on the mounting substrate 20, the solder material SDb can reach the upper surface 4a1 of the flat portion 4F. However, in this case, there is a possibility that adjacent leads 4 shown in FIG. 9 or terminals 21 shown in FIG. 9 are electrically connected to each other via the solder material SDb due to an increase in the amount of solder material used. On the other hand, according to the present embodiment, the solder material SDb is formed in a part of the lead 4 by providing a portion having a smaller thickness than the inner portion 4i and the flat portion 4F of the lead 4 as in the step portion 4D. The upper surface 4a2 is reached. For this reason, it is preferable at the point which suppresses the usage-amount increase of the solder material SDb and improves mounting strength.

  As another embodiment different from the present embodiment, a method of reducing the thickness of the entire lead 4 (for example, about 0.1 mm) is also conceivable. However, in this case, there is a concern that the strength of each lead 4 is reduced by reducing the thickness of the lead 4. On the other hand, according to the present embodiment, a part of the lead 4, more specifically, as shown in FIG. 6, a step which is a part of the outer portion 4 o protruding outward from the side surface 6 c of the sealing body 6 in plan view. The thickness of the portion 4D is reduced. Therefore, the thickness of the inner part 4i and the flat part 4F is the same as the thickness of the die pad 2 shown in FIG. 3, for example. For this reason, the strength reduction of each lead 4 can be suppressed and the mounting strength of the lead 4 can be improved.

<Manufacturing process of semiconductor device>
Next, the manufacturing process of the semiconductor device 1 shown in FIGS. 1 to 6 will be described. The semiconductor device 1 in the present embodiment is manufactured along the assembly flow shown in FIG. FIG. 13 is an explanatory diagram showing an assembly flow of the semiconductor device shown in FIGS.

1. Substrate preparation step;
First, as a base material preparation step shown in FIG. 13, a lead frame (base material) LF as shown in FIG. 14 is prepared. 14 is a plan view showing the overall structure of the lead frame prepared in the base material preparation step shown in FIG. 13, and FIG. 15 is an enlarged plan view of one of the plurality of device forming portions shown in FIG. FIG. 16 is an enlarged plan view showing a part of the plurality of leads shown in FIG. 17 is an enlarged sectional view taken along line AA in FIG. 16, FIG. 18 is an enlarged sectional view taken along line BB in FIG. 16, and FIG. 19 is taken along line CC in FIG. FIG.

  The lead frame LF prepared in this step includes a plurality of device forming parts (product forming parts) LFd inside the outer frame LFf. In the example illustrated in FIG. 14, the lead frame LF includes 14 device forming portions LFd in the row direction and 5 device forming portions LFd arranged in a matrix, and includes a total of 70 device forming portions LFd. The lead frame LF is made of metal, and in this embodiment, for example, a metal film (not shown) made of nickel (Ni) is formed on the surface of a base material made of copper (Cu) or copper (Cu), for example. A laminated metal film.

  In addition, frame portions LFs are arranged around each device forming portion LFd so as to surround each device forming portion LFd. The frame portion LFs is a region to be cut in an individualization process (see FIG. 13) described later. Further, as shown in FIG. 15, the frame portion LFs is formed so as to surround the plurality of leads 4.

  Further, as shown in FIG. 15, a die pad 2 having a quadrangular shape in plan view is formed at the center of each device forming portion LFd. One end of the suspension lead TL is connected to each of the four corners of the die pad 2 and is arranged so as to extend toward the corner of the device forming portion LFd. The other end of the suspension lead TL is connected to the frame portion LFs. The die pad 2 is connected to the frame portion LFs via the suspension lead TL, and is supported by the frame portion LFs.

  A plurality of leads 4 are formed around the die pad 2 between the plurality of suspension leads TL. Further, the plurality of leads 4 are respectively connected to the frame portion LFs arranged on the outer side of the plurality of leads 4 with respect to the die pad 2. The frame portion LFs is formed integrally with the plurality of leads 4, the suspension leads TL, and the die pad 2.

  Also, as shown in FIG. 16, between adjacent leads 4, a dam portion that is a gap surrounded by a side surface 4c1 of one lead 4, a side surface 4c2 of the other lead 4, and a frame portion LFs. DM is formed. The dam part DM is formed between each of the plurality of leads 4.

  As shown in FIGS. 16 and 17, each of the plurality of leads 4 (see FIG. 16) is provided with a groove portion (groove, stepped portion, recessed portion, recessed portion) 4 </ b> T on the upper surface 4 a side. This groove portion 4T is a portion that becomes the step portion 4D shown in FIG. In the present embodiment, as shown in FIGS. 16 and 17, the groove 4T is formed so as to straddle the boundary BL between the lead 4 and the frame portion LFs. Thereby, as shown in FIG. 6, the stepped portion 4 </ b> D can be formed at a position intersecting the tip end surface 4 ot of the lead 4.

  Note that the boundary BL between the lead 4 and the frame portion LFs is a virtual line of a planned area where each of the plurality of leads 4 is separated from the frame portion LFs in the singulation process shown in FIG. It doesn't have to exist. In the individualization step, some deviation may occur depending on the alignment accuracy of the cutting jig. Therefore, even when the position of the cutting jig is slightly deviated, the groove 4T is formed on the connecting portion including the boundary BL between the lead 4 and the frame portion LFs so that the step 4D can be reliably provided at the tip of the lead 4. For example, the groove width is about 0.2 to 0.3 mm.

  As shown in FIG. 17, the upper surface 4a2 corresponding to the bottom surface of the groove 4T is located at a position (on the lower surface 4b side) lower than the upper surface 4a1 of the inner portion 4i and the flat portion 4F. Thereby, as shown in FIG. 12, in the stepped portion 4D, the solder material SDb integrated so as to continuously surround the lower surface 4b, the upper surface 4a2, the side surface 4c1, and the side surface 4c2 can be formed at the time of mounting.

  On the other hand, since the frame portion LFs has a function as a support member that supports a metal member such as the lead 4 and the die pad 2 (see FIG. 15) during the manufacturing process, from the viewpoint of securing support strength, It is preferable to make the plate thickness larger than the groove 4T. Therefore, in the example shown in FIG. 17, the height of the upper surface LFa of the frame portion LFs is located at the same height as the upper surface 4 a 1 of the inner portion 4 i of the lead 4. In other words, the thickness of the frame portion LFs is the same as that of the inner portion 4 i of the lead 4. The height of the lower surface LFb of the frame portion LFs is the same as that of the lower surface 4b of the lead 4.

  The groove 4T can be formed by, for example, an etching process, that is, a removal process using a chemical reaction. In this case, it is formed by a so-called half-etching process in which etching is performed until the metal plate of the groove 4T is removed by about half of the plate thickness in a state where the portions other than the groove 4T of the lead frame LF are covered with a mask (not shown). can do.

  As shown in FIGS. 18 and 19, the lead 4 has a trapezoidal shape in a cross-sectional view in the X direction orthogonal to the extending direction of the lead 4 (for example, the Y direction shown in FIG. 17). In other words, in the lead 4, the width of the lower surface 4b (that is, the length in the X direction) is larger than the width of the upper surface 4a. In other words, the area of the lower surface 4b of the lead 4 is larger than the area of the upper surface 4a in plan view. The side surfaces 4c1 and 4c2 of the lead 4 shown in FIGS. 18 and 19 can be inclined with respect to the lower surface 4b and the upper surface 4a, for example, by pressing using a die (not shown).

2. Semiconductor chip mounting process;
Next, as a semiconductor chip mounting step shown in FIG. 13, the semiconductor chip 3 is mounted on the die pad 2 via the adhesive 7 as shown in FIGS. 20 and 21. 20 is an enlarged plan view showing a state in which a semiconductor chip is mounted on the die pad shown in FIG. 15 via a bonding material, and FIG. 21 is an enlarged cross-sectional view taken along line AA in FIG.

  In the example shown in FIG. 21, a so-called face-up mounting method in which the back surface 3 b of the semiconductor chip 3 (the surface opposite to the front surface 3 a on which the plurality of pads PD are formed) is opposed to the upper surface 2 a of the die pad 2. Installed in. As shown in FIG. 20, the semiconductor chip 3 is mounted at the center of the die pad 2 so that each side of the surface 3 a is arranged along each side of the die pad 2.

  In this step, for example, the semiconductor chip 3 is mounted via an adhesive 7 that is an epoxy-based thermosetting resin. The adhesive 7 is a paste material that has fluidity before being cured (thermoset). is there. When the paste material is used as the adhesive material 7 in this way, first, the adhesive material 7 is applied onto the die pad 2, and then the back surface 3 b of the semiconductor chip 3 is adhered to the upper surface 2 a of the die pad 2. Then, after bonding, when the adhesive 7 is cured (for example, heat treatment is performed), the semiconductor chip 3 is bonded and fixed onto the die pad 2 via the adhesive 7 as shown in FIG.

  Further, in this step, the adhesive 7 and the semiconductor chip 3 are respectively disposed on the die pad 2 provided in each of the plurality of device forming portions LFd. Then, the semiconductor chip 3 is mounted on each device forming portion LFd.

  In the present embodiment, an embodiment in which a paste material made of a thermosetting resin is used for the adhesive material 7 has been described, but various modifications can be applied. For example, instead of a paste material, an adhesive material, which is a tape material (film material) having adhesive layers on both sides, is attached in advance to the back surface 3b of the semiconductor chip 3, and the semiconductor chip 3 is placed on the die pad 2 via the tape material. May be installed.

3. Wire bonding process;
Next, as a wire bonding step shown in FIG. 13, a plurality of pads PD and a plurality of leads 4 of the semiconductor chip 3 are connected via a plurality of wires (conductive members) 5 as shown in FIGS. 22 and 23. , Each electrically connected. 22 is an enlarged plan view showing a state where the semiconductor chip shown in FIG. 20 and a plurality of leads are electrically connected via wires, and FIG. 23 is an enlarged cross-sectional view taken along line AA in FIG. is there.

  In this step, for example, the lead frame LF in which the semiconductor chip 3 is mounted on the die pad 2 of each device forming unit LFd is disposed on the heat stage (lead frame heating table) HS. Then, the pad PD of the semiconductor chip 3 and the lead 4 are electrically connected via the wire 5. In the present embodiment, the wire 5 is connected by a so-called nail head bonding method in which, for example, the wire 5 is supplied via a capillary (not shown), and the wire 5 is bonded using ultrasonic waves and thermocompression bonding.

  A plating film made of, for example, silver (Ag) or gold (Au) is formed on a part of the lead 4 (bonding region disposed at the tip of the inner part 4i), and a part of the wire 5 is The lead 4 is electrically connected through this plating film. The wire 5 is made of metal, and in this embodiment, is made of, for example, gold (Au).

  In the present embodiment, after connecting a part (end part) of the wire to the pad PD of the semiconductor chip 3, the other part of the wire 5 is used as a bonding region in the lead 4 (part of the upper surface 4 a of the lead 4). The wires are connected by a so-called positive bonding method. Further, the lower surface 4b located on the opposite side of the bonding region is in contact with the mounting surface HSa of the heat stage HS. That is, since the wire 5 is bonded to the thick portion of the lead 4, a sufficient load can be applied when the wire 5 is bonded to the lead 4, thereby improving the bonding strength. Can do.

  In this step, the wires 5 are bonded to the plurality of leads 4 provided in the plurality of device forming portions LFd, respectively. Thereby, in each device formation part LFd, the semiconductor chip 3 and the plurality of leads 4 are electrically connected via the plurality of wires 5.

4). Sealing step;
Next, as the sealing step shown in FIG. 13, as shown in FIGS. 24 and 25, the sealing body 6 is formed, the semiconductor chip 3 (see FIG. 25), the plurality of wires 5 (see FIG. 25), and A part of each of the plurality of leads 4 is sealed. 24 is a plan view showing a state where a sealing body is formed in the device forming portion of the lead frame shown in FIG. 22, and FIG. 25 is an enlarged cross-sectional view taken along line AA of FIG. FIG. 26 is a cross-sectional view showing a state in which the lead frame is arranged in the molding die in the sealing step shown in FIG. FIG. 27 is an enlarged plan view showing the periphery of some of the leads shown in FIG. FIG. 28 is an enlarged cross-sectional view along the line AA in FIG.

  In this step, as shown in FIG. 25, the sealing body 6 is formed so that the lower surfaces 4b of the plurality of leads 4 provided in each device forming portion LFd are exposed. In the present embodiment, the sealing body 6 is formed so that the lower surface 2b of the die pad 2 provided in each device forming portion LFd is exposed. In this step, for example, the sealing body 6 is formed by a so-called transfer mold method in which a softened resin is press-fitted into the molding die 50 in a state where the lead frame LF is sandwiched between the molding die 50 shown in FIG. Form.

  The molding die 50 includes an upper die (die) 51 arranged on the upper side of the lead frame LF and a lower die (die) 52 arranged on the lower side of the lead frame LF. The upper mold 51 includes a clamp surface (mold surface, pressing surface, surface) 51a for pressing the lead frame LF, and a cavity (recessed portion) 51b formed inside the clamp surface 51a. The lower mold 52 includes a clamp surface (mold surface, pressing surface, surface) 52a that is disposed so as to face the clamp surface 51a and presses the lead frame LF. In this embodiment, since a QFN type package is manufactured, no cavity is formed inside the clamp surface 52a of the lower mold 52.

  In the sealing process, a sealing resin is press-fitted into the cavity 51b, and a part of each of the semiconductor chip 3, the plurality of wires 5, and the plurality of leads 4 is sealed. And the sealing body 6 shown in FIG. 24 is formed by thermosetting the resin supplied to the cavity 51b.

  In the example shown in FIG. 26, a resin film (film material) 53 is disposed between the lead frame LF and the lower mold 52. A pressing force from the clamp surface 52 a of the lower mold 52 is applied to the lower surface side (back surface side, mounting surface side) of the lead frame LF via the resin film 53. For this reason, as shown in FIG. 26, the lower surface 4 b of the lead 4 and the lower surface 2 b of the die pad 2 are easily adhered to the resin film 53. By bringing the resin film 53 into close contact, it is possible to suppress the sealing resin from entering the lower surface 4b of the lead 4 and the lower surface 2b of the die pad 2. That is, the lower surface 4b of the lead 4 and the lower surface 2b of the die pad 2 can be exposed.

  Further, the molding die 50 of the present embodiment includes a plurality of cavities 51b, and the sealing body 6 is formed in a state in which each of the plurality of cavities 51b is disposed so as to correspond to the plurality of device forming portions LFd. The so-called individual sealing method is applied. In other words, in the sealing process of the present embodiment, the clamp surface 51a of the upper mold 51 of the molding die 50 shown in FIG. 26 is pressed around each of the plurality of device forming portions LFd.

  In this case, in addition to the main body resin portion 6mb formed in the cavity 51b, as shown in FIG. 24, it is embedded in a dam portion DM (see FIG. 27) which is a gap surrounded by the adjacent leads 4 and the frame portion LFs. The inside dam resin portion 6d is formed. Further, an in-gate resin portion 6g is formed in the gate portion which is a resin supply port. Further, a vent-inside resin portion 6v is formed in a vent portion that is disposed diagonally of the gate portion and discharges gas and excess resin in the cavity 51b (see FIG. 26) to the outside. In addition, an in-runner resin portion 6r is formed in the runner portion constituting the path for supplying the resin to the gate portion.

  On the other hand, as shown in FIG. 27, the outer portion 4o of the lead 4 is exposed around the main body resin portion 6mb so as to protrude outward from the side surface 6c of the main body resin portion 6mb. In the outer portion 4o, the upper surface 4a and the lower surface 4b (see FIG. 28) are exposed from the sealing body 6, and the side surface 4c1 and the side surface 4c2 are sealed by the in-dam resin portion 6d. In the present embodiment, as shown in FIG. 27, the groove 4T is formed so as to straddle the boundary BL between the lead 4 and the frame LFs. For this reason, in this process, resin flows into the groove 4T from the dam part DM surrounded by the side surface 4c1, the side surface 4c2 and the frame part LFs of the lead 4, and the in-groove resin part 6t is formed. That is, as shown in FIG. 28, among the upper surface 4a of the outer portion 4o of the lead 4, the upper surface 4a2 corresponding to the bottom surface of the groove portion 4T is sealed with the in-groove resin portion 6t.

5. Resin removal process (laser irradiation process);
Next, as the resin removal step shown in FIG. 13, the in-dam resin portion 6d and the in-groove resin portion 6t shown in FIG. 27 are removed. FIG. 29 is an enlarged plan view showing a state in which the resin part in the dam and the resin part in the groove shown in FIG. 27 are removed. 30 is an enlarged cross-sectional view schematically showing a state in which the resin is being removed by laser irradiation in the cross section along the line AA shown in FIG. 29, and FIG. 31 is a line BB shown in FIG. FIG. 6 is an enlarged cross-sectional view schematically showing a state in which a resin is being removed by laser irradiation in a cross section taken along a line.

  In this step, as shown in FIG. 30 and FIG. 31, a portion of the lead frame LF other than the main body resin portion 6mb (see FIG. 30) is irradiated with a laser beam 55, whereby the in-dam resin portion 6d ( 31) and the in-groove resin portion 6t (see FIG. 30) are removed. Specifically, as shown in FIG. 30, a laser irradiation device 56 as a light source of the laser beam 55 is disposed on the upper surface LFa side of the lead frame LF, that is, on the chip mounting surface side opposite to the mounting surface, and the upper surface LFa. The laser beam 55 is irradiated from the side toward the groove 4T. Further, as shown in FIG. 31, a laser irradiation device 56 as a light source of the laser beam 55 is disposed on the upper surface LFa side of the lead frame LF, and the laser beam 55 is irradiated from the upper surface LFa side toward the dam part DM.

  The laser light 55 is, for example, a YAG laser using yttrium, aluminum, and garnet crystals, and is a near infrared light having a fundamental wavelength of 1064 nm (nanometers). The laser beam 55 has an output of about 40 W (watts), for example, and is output by a pulse operation of about 20 kHz (kilohertz). The focus of the laser beam 55 is adjusted to the surface of the resin part that is the removal target. Further, the line width and the laser interval of the laser light 55 are, for example, about 40 μm (micrometers), for example, at a scanning speed of about 300 mm / second (300 millimeters per second), and around the body resin portion 6 mb shown in FIG. Scan. The number of scans is, for example, about 3 times.

  Near-infrared light becomes a heat source for heating the irradiated object, and the resin that is the irradiated object can be removed thermally. The dam resin portion 6d (see FIG. 31) and the groove resin portion 6t (see FIG. 30), which are objects to be removed in this step, are many, such as thermosetting resins such as epoxy resins, curing agents, and silica. This is an insulating resin body mainly composed of filler particles, and contains many secondary raw materials in addition to the above. Therefore, by irradiating the laser beam 55 which is near-infrared light, the removal target can be removed by a thermal action with little material selectivity.

  As shown in FIG. 31, in the present embodiment, each of the plurality of leads 4 is such that the width of the upper surface 4a is smaller than the width of the lower surface 4b in a cross section cut in a direction orthogonal to the extending direction. The side surface 4c1 and the side surface 4c2 form an inclined trapezoidal cross-sectional shape. Thus, by making the side surfaces 4c1, 4c2 of the lead 4 into inclined surfaces, in this step, even when the laser beam 55 is irradiated from a direction perpendicular to the upper surface 4a, for example, the side surfaces 4c1, 4c2 are irradiated. It becomes easy. As a result, the removal reliability of the in-dam resin portion 6d is improved. Further, in this step, if the in-dam resin portion 6d can be surely removed and the side surfaces 4c1, 4c2 can be exposed, a metal film can be formed so as to cover the side surfaces 4c1, 4c2 in the plating step shown in FIG. Therefore, when the semiconductor device is mounted, the wettability between the lead 4 and the solder material can be improved.

  Although illustration is omitted, from the viewpoint of improving the ease of laser irradiation, as a modification to FIG. 31, the width of the upper surface 4a is larger than the width of the lower surface 4b, and the side surface 4c1 and the side surface 4c2 are inclined surfaces. An inverted trapezoidal cross-sectional shape is also conceivable. In this case, the laser irradiation device 56 is disposed on the lower surface LFb side of the lead frame LF, that is, on the mounting surface side, and the laser beam 55 is irradiated from the lower surface LFb side toward the dam portion DM, thereby lasers the side surfaces 4c1 and 4c2. The light 55 is easily irradiated.

  However, considering the viewpoint of increasing the area of the lower surface 4b, which is the main mounting surface of the lead 4, and improving the mounting strength, a regular trapezoidal shape as in the present embodiment is preferable. Therefore, as shown in FIG. 31, in this step, it is preferable to irradiate the laser beam 55 from the upper surface LFa side of the lead frame LF. Further, in this case, when the groove 4T (see FIG. 30) is provided on the upper surface 4a side of the lead 4 as in the present embodiment, the removal of the in-dam resin portion 6d shown in FIG. Since the in-groove resin portion 6t is irradiated with the laser beam 55 from the same direction (from the upper surface LFa side), these removals can be collectively performed in the same process. Therefore, the time required for the resin removal step can be shortened and the manufacturing efficiency can be improved as compared with the case where the laser beam 55 is irradiated from both the upper surface LFa side and the lower surface LFb side. In other words, when the groove 4T is formed on the upper surface side of the lead 4 as in the present embodiment, manufacturing efficiency can be improved by making the cross-sectional shape of the lead 4 a regular trapezoid.

  In this step, as shown in FIG. 29, in the outer portion 4o of the lead 4, it may be removed so as to leave a part of the in-dam resin portion 6d on the main body resin portion 6mb side. In the case of the method of removing the resin thermally as in the present embodiment, in order to remove all the resin part 6d in the dam, the laser beam 55 (see FIG. 30) is irradiated to the boundary with the main body resin part 6mb. There is a concern that the main body resin portion 6mb deteriorates due to the heat effect. Therefore, as shown in FIG. 29, it is preferable to irradiate the laser beam 55 so as to leave a part of the resin portion 6d in the dam in the vicinity of the main body resin portion 6mb in terms of reducing the thermal effect on the main body resin portion 6mb. .

  On the other hand, since the groove 4T is a part for forming the step 4D shown in FIGS. 5 and 6, in order to reliably form the metal film SD (see FIG. 6) in the plating step shown in FIG. It is preferable to improve the removal accuracy of the in-groove resin portion 6t shown in FIG. In the present embodiment, as described above, the groove 4T is formed so as to straddle the boundary BL between the lead 4 and the frame portion LFs. That is, the groove 4T is formed at a position farthest from the main body resin portion 6mb in the device forming portion LFd. For this reason, even when the entire groove 4T is irradiated with the laser beam 55, the thermal influence on the main body resin portion 6mb can be reduced.

6). Plating process;
Next, as a plating step shown in FIG. 13, as shown in FIG. 32, a metal film SD is formed on the exposed surfaces of the leads 4 from the main body resin portion 6mb. 32 is an enlarged cross-sectional view showing a state in which a metal film is formed on the resin exposed surface of the lead frame shown in FIG. 30, and FIG. 33 is an explanatory view showing an outline of the plating process by the electrolytic plating method.

  In this step, a metal film SD (see FIG. 32) made of, for example, solder is formed on the surface of the metal member exposed from the resin by electrolytic plating. In the electrolytic plating method, as shown in FIG. 33, a lead frame LF which is a workpiece to be plated is placed in a plating tank 60 containing a plating solution 61. At this time, the workpiece is connected to the cathode 62 in the plating tank 60. For example, in the example shown in FIG. 33, the outer frame LFf of the lead frame LF is electrically connected to the cathode 62. A metal film SD is formed on the exposed surface of the metal member connected to the outer frame LFf of the lead frame LF by applying a DC voltage, for example, between the cathode 62 and the anode 63 also disposed in the plating tank 60. (See FIG. 32). That is, in this embodiment, the metal film SD is formed by a so-called electrolytic plating method.

As described above, the metal film SD of the present embodiment is made of so-called lead-free solder that does not substantially contain lead (Pb). For example, only tin (Sn), tin-bismuth (Sn-Bi), Or it is tin-copper-silver (Sn-Cu-Ag). For this reason, the plating solution 61 used in the present plating step is an electrolytic plating solution containing a metal salt such as Sn ²⁺ or Bi ³⁺ . In the following description, Sn—Bi alloyed metal plating will be described as an example of lead-free solder plating, but Bi can be replaced with a metal such as Cu or Ag.

In the present embodiment, as described above, the plating process is performed in a state where the plurality of leads 4 are electrically connected to the outer frame LFf through the frame portion LFs. The die pad 2 is electrically connected to the outer frame LFf via the frame portion LFs and the suspension lead TL (see FIG. 15). Therefore, when a voltage is applied between the anode 63 and the cathode 62 shown in FIG. 31 in a state where the lead frame LF is immersed in the plating solution 61, current is passed between both electrodes (between the anode 63 and the cathode 62). As described above, since the outer frame LFf of the lead frame LF is electrically connected to the cathode 62, Sn ²⁺ and Bi ³⁺ in the plating solution 61 are exposed at a predetermined ratio and the exposed surface of the lead 4 shown in FIG. To form a metal film SD.

  As described above, according to the electrolytic plating method, the metal film SD is formed on the surface of the metal member exposed from the resin. Therefore, in the present embodiment, the metal film SD is formed so as to cover the upper surface 4a of the outer portion 4o of the lead 4 and the lower surface 4b of the lead 4 exposed outside the main body resin portion 6mb of the sealing body 6. . In the present embodiment, a resin removing step is performed before the plating step, and the upper surface 4a2 corresponding to the bottom surface of the groove 4T of the lead 4 is exposed as shown in FIG. The metal film SD can be formed so as to cover it. Further, as shown in FIGS. 7 and 8, the metal film SD can be formed so as to cover the side surfaces 4c1 and 4c2 of the lead 4. In other words, the dam portion DM shown in FIG. 29 is covered with the metal film SD shown in FIG. 7 or FIG. Further, as shown in FIG. 32, in this step, the metal film SD is also formed on the frame portion LFs of the lead frame LF. Further, as shown in FIG. 25, in this embodiment, the lower surface 2 b of the die pad 2 is exposed from the sealing body 6. Therefore, in this step, the metal film SD is formed so as to cover the lower surface 2b of the die pad 2 as shown in FIG. Although the film thickness of the metal film SD can be changed according to product specifications, for example, a film of about 10 μm to 20 μm is formed.

7). Individualization step;
Next, as shown in FIG. 34, as the individualization process shown in FIG. 13, the frame portions LFs to which the plurality of leads 4 and the suspension leads TL are connected are cut, and the plurality of device forming portions LFd are individually separated. Divide into pieces. FIG. 34 is an enlarged plan view showing a state in which each device forming unit is singulated in the singulation process shown in FIG. 13. FIG. 35 is an enlarged cross-sectional view showing a state where the boundary between the lead and the frame portion is cut in the singulation process shown in FIG. FIG. 36 is a perspective view showing the shape of the upper die shown in FIG.

  In this step, for example, as shown in FIG. 35, a punch (cut punch, cutting blade) 65 and a die (pressing member, die) 66, which are press dies (die) for cutting, are used for pressing. Each of the plurality of leads 4 is separated from the frame portion LFs by processing.

  Specifically, the die 66 that is a pressing member during press working includes an upper die (die) 66a disposed on the upper surface 4a side of the lead 4 and a lower (die) die 66b disposed on the lower surface 4b side of the lead 4. Have. The upper die 66a presses the periphery of the cut portion of the lead 4 in a state where it is in contact with at least the upper surface 4a1 of the lead 4 and the lower die 66b is in contact with the lower surface 4b of the lead 4. The cut portion of the lead 4 is a boundary BL between the lead 4 and the frame portion LFs. However, the cut portion of the lead 4 may be a position different from the boundary BL shown in FIG. 30 at least at a position overlapping the groove 4T.

  Further, the punch 65 that is a cutting blade at the time of press working is movable in the thickness direction of the lead frame LF, and the lead 4 is fixed by being sandwiched between dies 66 as schematically shown in FIG. In this state, the punch 65 is inserted from the lower surface 4b side of the lead 4 toward the upper surface 4a side. As a result, the lead 4 is sheared in the thickness direction at the boundary BL and separated from the frame portion LFs.

  In this embodiment, since the groove 4T is formed at the boundary BL between the lead 4 and the frame portion LFs, the lead 4 is cut in the middle of the groove 4T, and the step described with reference to FIG. Part 4D is formed. Further, a part SDt extending from the lower surface 4b toward the upper surface 4a2 is formed on the cut surface of the lead 4 by dragging a part of the metal film SD to the punch 65.

  Here, as shown in FIG. 12 described above, when the semiconductor device 1 is mounted, in order to make the solder material SDb reach the upper surface 4a2 of the stepped portion 4D, the position of the upper surface 4a2 may be brought closer to the lower surface 4b. preferable. Further, when the amount of the solder material SDb that goes around to the lower surface 4b side of the lead 4 at the time of mounting increases, the amount of the solder material SDb that covers the side surfaces 4c1 and 4c2 of the lead 4 relatively decreases, so the solder material SDb becomes the step portion 4D. It becomes difficult to reach the upper surface 4a2. Therefore, in the singulation process, it is preferable to suppress the deformation of the tip portion of the lead 4, that is, the portion where the step portion 4D is formed.

  Therefore, in the present embodiment, the lead 4 is pressed while the upper die 66a is in contact with the upper surface 4a2 of the groove 4T. In other words, in addition to the upper surface 4a1 and the lower surface 4b of the flat portion 4F of the lead 4, the cutting process is performed with the upper surface 4a2 of the groove portion 4T being pressed. For this reason, since the vicinity of the cut portion can be pressed, the deformation of the tip portion of the lead 4, that is, the portion where the step portion 4D is formed can be suppressed, and the shape of the step portion 4D can be stably formed. .

  As described above, when the upper die 66a is brought into contact with both the upper surface 4a1 of the flat portion 4F and the upper surface 4a2 of the groove portion 4T when performing the cutting process, the shape of the contact surface of the upper die 66a is determined as the lead 4 It is necessary to follow the shape of the flat part 4F and the groove part 4T. Therefore, in the present embodiment, the upper die 66a is a pressing surface (contact surface) that is a pressing surface (contact surface) that is in contact with the upper surface 4a1 of the flat portion 4F, and a pressing surface (contact surface) that is in contact with the upper surface 4a2 of the groove portion 4T. The surface 66a2. The boundary between the surface 66a1 and the surface 66a2 is a stepped surface as shown in FIGS. 35 and 36, and the surface 66a1 and the surface 66a2 have different heights with respect to the thickness direction (Z direction) of the lead 4. Is located. In the example shown in FIG. 35, the surface 66a2 is disposed at a position lower than the surface 66a1.

  In other words, the upper die 66a of the present embodiment is provided with a protruding wall 66w protruding toward the lead 4 at one end in the extending direction of the lead 4 (Y direction in the example shown in FIG. 35). Yes. The front end surface of the protruding wall 66w is a surface 66a2 that is a pressing surface (contact surface) that is brought into contact with the upper surface 4a2 of the groove 4T. Further, the lower surface of the portion other than the protruding wall 66w is a surface 66a1, which is a pressing surface (contact surface) that is brought into contact with the upper surface 4a1 of the flat portion 4F. In this way, by providing the protruding wall 66w at one end of the upper die 66a, the upper die 66a is separated from both the upper surface 4a1 of the flat portion 4F of the lead 4 and the upper surface 4a2 of the groove portion 4T in the singulation process. Can be contacted simultaneously.

  By the way, in the present embodiment, when the cutting process is performed, the protruding wall 66w is provided on the upper die 66a in order to bring the upper die 66a into contact with both the upper surface 4a1 of the flat portion 4F and the upper surface 4a2 of the groove portion 4T. Therefore, the shape of the protruding wall 66w needs to follow the shape of the groove 4T of the lead 4 (or the step 4D formed after cutting). First, the width of the protruding wall 66w (the length in the extending direction of the lead 4 and the width in the Y direction in the example shown in FIG. 35) is the groove width of the groove portion 4T (the length in the extending direction of the lead 4). In the example shown in FIG. 35, it is necessary to make it smaller than the width in the Y direction. The width of the protruding wall 66w is, for example, less than 0.1 mm. Moreover, the height (length in the thickness direction (Z direction)) of the protruding wall 66w is the same as the depth of the groove 4T, and is, for example, about 0.1 mm. In this way, by forming the protruding wall 66w with high accuracy on the contact surface side of the upper die 66a with the lead 4, in addition to the upper surface 4a1 and the lower surface 4b of the flat portion 4F of the lead 4, the upper surface 4a2 of the groove portion 4T is also formed. Cutting can be performed in a pressed state. As a result, deformation of the lead 4 in the singulation process can be suppressed.

  The shape of the upper die 66a can be provided with a protruding wall 66w (see FIG. 35) corresponding to each of the plurality of leads 4 shown in FIG. 34. However, as shown in FIG. 34) may be provided with a protruding wall 66w having a longitudinal direction along the arrangement direction (for example, the X direction). In this case, the plurality of leads 4 can be pressed together by one upper die 66a.

  After this step, necessary inspections and tests such as an appearance inspection and an electrical test are performed, and what has passed is a completed semiconductor device 1 shown in FIG. Then, the semiconductor device 1 is shipped or mounted on a mounting board (not shown).

(Embodiment 2)
In the first embodiment, for example, as shown in FIG. 12, a step 4D is provided at the tip of the lead 4, and the lower surface 4b, the upper surface 4a2, the side surface 4c1, and the side surface 4c2 of the step 4D are continuously surrounded during mounting. The technology for improving the mounting strength of the semiconductor device by forming the solder material SDb integrated as described above has been described. In the present embodiment, as a modification of the first embodiment, a technique for improving the mounting strength of the semiconductor device by deforming the tip portion of the lead 4 in the direction opposite to the mounting surface in the singulation process will be described. To do.

  The present embodiment is different from the first embodiment in the singulation process in the manufacturing process of the semiconductor device. Further, the shape of the stepped portion 4D of the obtained semiconductor device is different from that of the first embodiment. Except for the differences described above, the semiconductor device and the method for manufacturing the semiconductor device of the present embodiment are the same as those of the first embodiment. Therefore, in the present embodiment, the description will focus on the differences from the first embodiment. The overlapping description will be omitted in principle, and will be described with reference to FIGS.

  As described above, when the semiconductor device 1 is mounted, in order to make the solder material SDb reach the upper surface 4a2 of the step portion 4D, the position of the upper surface 4a2 is preferably close to the lower surface 4b. Therefore, in the above-described individualization step, it is preferable to suppress the deformation of the tip portion of the lead 4, that is, the portion where the step portion 4D is formed. Further, as shown in FIG. 35 described in the above-described individualization step, it is preferable to provide a protruding wall 66w at the peripheral edge of the upper die 66a in order to suppress deformation of the portion where the step 4D is formed. .

  However, in order to bring the protruding wall 66w into contact with the upper surface of the groove 4T, the width of the protruding wall 66w (the length in the extending direction of the lead 4 and the width in the Y direction in the example shown in FIG. 35) is set to the groove 4T. The groove width (the length in the extending direction of the lead 4, which is the width in the Y direction in the example shown in FIG. 35) needs to be made smaller. For example, it is necessary to make the width of the protruding wall 66w smaller than 0.1 mm, and to bring the lower surface of the protruding wall 66w into contact with the upper surface 4a2 of the groove 4T formed in each of the plurality of leads 4. Therefore, in the singulation process, it is necessary to align the upper die 66a and the lead frame LF with high accuracy.

  Therefore, the inventor of the present application has studied the simplification of the singulation process, and studied an embodiment in which the lead 4 is cut in a state where the upper die 66a is not in contact with the upper surface 4a2 of the groove 4T. FIG. 37 is an enlarged cross-sectional view showing a state in which the boundary between the lead and the frame portion is cut in the singulation process of the present embodiment, which is a modification to FIG.

  As shown in FIG. 37, in the manufacturing method of the semiconductor device of the present embodiment, of the die 66 that is a pressing member at the time of press working, the shape of the upper die (die) 66c disposed on the upper surface side of the lead frame LF. However, it is different from the upper die 66a shown in FIG. Specifically, the upper die 66c shown in FIG. 37 is not formed with the protruding wall 66w as shown in FIG. 35, and the surface 66a1 which is a contact surface with the lead 4 is a uniform flat surface having no step or depression. It has become.

  As shown in FIG. 37, when cutting is performed using the upper die 66c having a flat contact surface, the upper surface 4a2 of the groove 4T does not contact the upper die 66c when cutting with the punch 65. In other words, in the present embodiment, in the singulation process, a position away from the boundary BL, which is a cutting location (for example, a location separated by about 0.1 mm) is pressed, and the upper surface 4a2 side of the groove 4T where the cutting location is arranged Will not hold down. As described above, when the punch 65 is inserted without pressing the upper surface 4a2 side of the groove 4T, the stress generated by the insertion pressure of the punch 65 is concentrated near the boundary between the groove 4T and the flat portion 4F, and the groove 4T and the flat portion are formed. With the vicinity of the boundary of 4F as a base point, the groove 4T is easily bent toward the chip mounting surface side, that is, the upper surface 4a side.

  In other words, the lower surface 4b of the lead 4 formed according to the present embodiment has a lower surface 4b1 and a lower surface 4b2 having different angles. The lower surface 4b1 is a surface located on the opposite side of the inner portion 4i of the lead 4 and the upper surface 4a1 of the flat portion 4F, and faces the same direction as the lower surface 6b of the main body resin portion 6mb (Z direction in the example shown in FIG. 37). ing. On the other hand, the lower surface 4b2 is a surface located on the opposite side of the upper surface 4a2 of the step portion 4D of the lead 4, and the upper surface 4a2 and the lower surface 4b2 are inclined with respect to the lower surface 6b of the main body resin portion 6mb of the sealing body 6, respectively. It is an inclined surface.

  As described above, in the present embodiment, in the singulation process, cutting is performed without bringing the upper die 66c into contact with the upper surface 4a2 of the groove 4T. Therefore, the processing accuracy required for the upper die 66c has a larger margin than the processing accuracy required for the upper die 66a of the above-described embodiment shown in FIG. Further, the alignment accuracy between the upper die 66c and the lead frame LF in the present embodiment may be lower than the alignment accuracy between the upper die 66a and the lead frame LF in the above-described embodiment shown in FIG. That is, in this embodiment, the singulation process can be performed more easily than in the above embodiment.

  On the other hand, in the semiconductor device 1A obtained by the semiconductor device manufacturing method of the present embodiment, as shown in FIG. 37, the tip portion of the outer portion 4o of the lead 4 is bent toward the opposite side of the mounting surface. Hereinafter, the mounting strength when the semiconductor device 1A is mounted on the mounting substrate will be described.

<About mounting strength of semiconductor devices>
FIG. 38 is an enlarged plan view showing a state where the semiconductor device shown in FIG. 37 is mounted on a mounting substrate. 39 is an enlarged sectional view taken along the line AA in FIG. 38, FIG. 40 is an enlarged sectional view taken along the line BB in FIG. 38, and FIG. 41 is an enlarged view taken along the line CC in FIG. It is sectional drawing. FIG. 42 is an enlarged cross-sectional view showing a modification to FIG. 38 to 41 show a state in which when the semiconductor device 1A shown in FIG. 37 is mounted on the mounting board 20, the lead 4 and the terminal 21 of the mounting board 20 are electrically connected via the solder material SDb. ing.

  As shown in FIG. 39, when the tip portion of the outer portion 4o of the lead 4 is bent in the direction opposite to the mounting surface, the thickness T3 of the solder material SDb disposed between the step portion 4D and the upper surface 21a of the terminal 21. Is thicker than the thickness T4 of the solder material SDb disposed between the inner portion 4i and the upper surface 21a of the terminal 21. Therefore, when the amount of the solder material applied on the terminal 21 at the time of mounting is small, as shown in FIG. 41, in the vicinity of the front end surface 4ot (see FIG. 39) of the outer portion 4o, the solder material reaches the upper surface 4a2 of the step portion 4D. There is a case where the metal film SD covering the upper surface 4a1 and the solder material SDb are separated because the SDb does not wet up.

  However, as shown in FIG. 39, in the present embodiment, the stepped portion 4D of the lead 4 bends around the boundary between the stepped portion 4D and the flat portion 4F, and therefore near the boundary between the stepped portion 4D and the flat portion 4F. As described with reference to FIG. 12, the solder material SDb integrated so as to continuously surround the lower surface 4b, the upper surface 4a2, the side surface 4c1, and the side surface 4c2 is formed. Therefore, the mounting strength can be improved as compared with the case where the step portion 4D is not provided.

  Further, after mounting the semiconductor device 1A on the mounting substrate 20, when a temperature cycle load (thermal load generated by repeated heating and cooling) is applied, the leading end surface 4ot and the bottom surface 4b2 of the lead 4 shown in FIG. The stress caused by the temperature cycle load becomes the largest at the joint interface where the two cross. In other words, when the electrical connection state between the lead 4 and the terminal 21 of the semiconductor device 1A is broken by a temperature cycle load, the break is likely to occur with the portion where the tip surface 4ot and the lower surface 4b2 of the lead 4 intersect as a base point.

  Here, in the semiconductor device 1A of the present embodiment, the thickness T3 of the solder material SDb disposed in the portion where the stress is greatest is the thickness of the solder material SDb in the case of the semiconductor device 1 shown in FIG. The thickness corresponding to the thickness T4 shown in FIG. For this reason, the tolerance with respect to the temperature cycle load of the solder material SDb improves, and the temperature cycle life (the number of temperature cycles until it is damaged due to the temperature cycle load) can be extended. That is, the semiconductor device 1A has higher mounting reliability in that the temperature cycle life can be extended as compared with the semiconductor device 1 described in the first embodiment.

  Moreover, when the lower surface 4b2 of the step portion 4D is an inclined surface as in the present embodiment, the space between the step portion 4D and the terminal 21 is widened. For this reason, if the amount of the solder material applied when mounting the semiconductor device 1A is increased, even if it is in the vicinity of the front end surface 4ot (see FIG. 39) of the lead 4, as shown as a modified example in FIG. The solder material SDb can be wetted up to the upper surface 4a2 of the portion 4D. That is, in the step portion 4D, the solder material SDb integrated so as to continuously surround the lower surface 4b2, the upper surface 4a2, the side surface 4c1, and the side surface 4c2 can be formed. Further, in the case of the present embodiment, since a wide space can be secured between the stepped portion 4D and the terminal 21, even if the amount of solder material is increased, as shown in FIG. They can be electrically separated from each other.

  As shown in FIG. 39, in the semiconductor device 1A of the present embodiment, the portion where the tip surface 4ot of the lead 4 intersects the lower surface 4b2 of the step portion 4D is at a position higher than the lower surface 4b1 of the inner portion 4i. For this reason, the shape of the solder fillet extending further outward from the tip surface 4 ot can be made larger than that of the first embodiment. Therefore, according to the present embodiment, after mounting the semiconductor device 1A, the solder material SDb is wetted up by a visual inspection from the opposite side of the mounting surface or an appearance inspection using an imaging device such as an image sensor. Can be easily confirmed.

  As described above, in the present embodiment, in the singulation process, the punch 65 is inserted from the lower surface 4b side of the lead 4 toward the upper surface 4a2 side without contacting the upper die 66c to the upper surface 4a2 of the groove portion 4T. . As a result, the lead 4 is cut and the distal end portion on the distal end surface 4 ot side is bent toward the upper surface 4 a 2 side. Thereby, the singulation process can be simplified. Further, the arrangement space of the solder material SDb can be increased at the tip of the lead 4. If attention is paid to the effect of simplifying the singulation process and the effect of securing the arrangement space of the solder material SDb, the following modifications can be considered.

  That is, if the improvement in mounting strength due to the solder material SDb getting wet up to the upper surface 4a2 of the stepped portion 4D is not considered, a part or all of the upper surface 4a2 of the stepped portion 4D is formed in the in-groove resin portion 6t (see FIG. 27). ) May not be removed. In this case, the processing time of the resin removal process shown in FIG. 13 can be shortened.

  Further, by bending the tip portion of the lead 4, it is possible to easily confirm the wet-up state of the solder material SDb after mounting the semiconductor device. Therefore, part or all of the in-dam resin portion 6d (see FIG. 27) between the adjacent leads 4 may not be removed. In this case, the resin removal step shown in FIG. 13 can be omitted.

  However, in the situation where the resin part 6d and the resin part 6t in the dam shown in FIG. 27 are not completely removed, when the singulation process described with reference to FIG. 39 is performed, the resin part 6d and the groove in the dam There is a concern that the inner resin portion 6t becomes a resistance to bending, and the lead 4 is difficult to bend stably. Further, in the singulation process, a crack is generated in a part of the resin part 6d in the dam or the resin part 6t in the groove, and when this crack progresses, there is a concern that the main body resin part 6mb is damaged.

<Modification>
Although the invention made by the inventors of the present application has been specifically described above based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

(Modification 1)
For example, in the above-described embodiment, a so-called quad type semiconductor device in which a plurality of leads 4 are arranged along the four main sides of a quadrangular sealing body 6 in plan view will be described. did. However, as a modification, for example, the present invention can be applied to a SON type semiconductor device in which a plurality of leads 4 are arranged along two opposite sides of a sealing body having a quadrangular shape in plan view.

(Modification 2)
Further, for example, in the above embodiment, the die pad exposed type (tab exposed type) semiconductor device in which the lower surface 2b of the die pad 2 is exposed from the sealing body 6 has been described. However, as a modification, it can be applied to a semiconductor device in which a die pad is sealed inside a sealing body. In this case, the lower surface 2b of the die pad 2 is preliminarily thinned by etching, or the suspension lead TL is bent so that the lower surface 2b of the die pad 2 is positioned higher than the lower surface 4b of the lead 4. An offset method can be used.

(Modification 3)
Further, for example, in the above embodiment, the embodiment in which the side surfaces 4c1 and 4c2 are inclined with respect to the upper surface 4a and the lower surface 4b so that the cross-sectional shape in the direction orthogonal to the extending direction of the leads 4 forms a regular trapezoid. It was taken up and explained. This is because the laser light 55 is likely to hit the side surfaces 4c1 and 4c2 when the laser light 55 is irradiated from a direction perpendicular to the upper surface 4a of the lead 4 in the resin removing step shown in FIG. is there. Therefore, as a modification, even if the side surfaces 4c1 and 4c2 are orthogonal to the upper surface 4a and the lower surface 4b, the in-dam resin portion 6d cannot be removed. In addition, although it is necessary to change the angle during scanning, the laser beam 55 can be irradiated from a direction inclined with respect to the side surfaces 4c1 and 4c2 of the lead 4.

(Modification 4)
Further, for example, in the above-described embodiment, the description has been given of the embodiment in which the groove 4T is formed by an etching process, that is, a removal process using a chemical reaction. However, as a modification, it can be formed by mechanical action such as shearing using a mold or cutting using a cutting jig such as a blade.

(Modification 5)
Further, for example, in the above embodiment, the embodiment in which the lead frame LF in which the groove 4T is formed in advance is prepared in the base material preparation step shown in FIG. 13 has been described. However, as a modification, the groove 4T can be formed at an arbitrary timing before the plating step. However, when the groove 4T is formed in a state where the components are mounted on the lead frame LF, it is necessary to protect the mounted components regardless of whether chemical processing or mechanical processing is performed. Becomes complicated. Therefore, it is particularly preferable to form the groove 4T in advance before mounting the semiconductor chip 3.

(Modification 6)
Further, for example, in the above embodiment, the semiconductor chip 3 has been described by taking an example in which the semiconductor chip 3 is mounted on the die pad 2 by a so-called face-up mounting method. However, as a modification, the bonding region of the lead 4 and the pad PD of the semiconductor chip 3 can be arranged to face each other and can be mounted by a so-called face-down mounting method. In this case, a bump electrode (not shown) can be used in place of the wire 5 as a conductive member that electrically connects the lead 4 and the pad PD of the semiconductor chip 3. Such a connection method is called a flip chip connection method.

(Modification 7)
For example, in the above-described embodiment, the embodiment in which the resin film 53 is disposed between the lead frame LF and the lower mold 52 in the sealing process has been described. However, as a modification, the lead frame LF can be directly disposed on the lower mold 52 without the resin film 53 interposed therebetween.

(Modification 8)
For example, in the above-described embodiment, the embodiment in which the metal film SD is formed by the electrolytic plating method in the plating step has been described. However, as a modification, the metal film SD can be formed by an electroless plating method.

(Modification 9)
Furthermore, the modified examples can be applied in combination within a range not departing from the gist of the technical idea described in the above embodiment.

  In addition, a part of the contents described in the above embodiment will be described below.

[Appendix 1]
A chip mounting portion having a first surface and a second surface opposite to the first surface;
A third surface facing the same direction as the first surface of the chip mounting portion and a fourth surface opposite to the third surface, and a plurality of leads disposed next to the chip mounting portion;
A semiconductor chip having a front surface, a plurality of electrode pads formed on the front surface, and a back surface opposite to the front surface and mounted on the first surface side of the chip mounting portion;
A plurality of conductive members that electrically connect the plurality of electrode pads of the semiconductor chip and the plurality of leads, respectively;
A main body resin portion for sealing the semiconductor chip and the plurality of conductive members;
Have
Each of the plurality of leads is formed with a step portion on the third surface side at a position farthest from the main body resin portion,
Of the plurality of leads, the third surface and the fourth surface of the portion exposed from the main body resin portion are covered with a metal film.

[Appendix 2]
A chip mounting portion having a first surface and a second surface opposite to the first surface;
A third surface facing the same direction as the first surface of the chip mounting portion and a fourth surface opposite to the third surface, and a plurality of leads disposed next to the chip mounting portion;
A semiconductor chip having a front surface, a plurality of electrode pads formed on the front surface, and a back surface opposite to the front surface and mounted on the first surface side of the chip mounting portion;
A plurality of conductive members that electrically connect the plurality of electrode pads of the semiconductor chip and the plurality of leads, respectively;
A main body resin portion for sealing the semiconductor chip and the plurality of conductive members;
Have
Each of the plurality of leads is formed with a step portion on the third surface side at a position farthest from the main body resin portion,
The step portion is bent from the fourth surface side toward the third side,
Of the plurality of leads, the fourth surface of the portion exposed from the main body resin portion is covered with a metal film.

1, 1A Semiconductor device 2 Die pad (chip mounting part, tab)
2a Top surface (chip mounting surface)
2b Bottom surface (mounting surface)
3 Semiconductor chip 3a surface (main surface, upper surface)
3b Back surface (main surface, bottom surface)
3c Side 4 Lead (terminal, external terminal)
4a, 4a1, 4a2 Upper surface 4b, 4b1, 4b2 Lower surface 4c1, 4c2 Side surface 4D Step part (part)
4F flat part (part)
4i Inner part (part)
4it inner surface (end)
4o Outer part (part)
4 ot tip (end)
4T Groove (groove, step, recess, recess)
5 Wire (conductive member)
6 Sealing body (resin body)
6a Upper surface 6b Lower surface (back surface, mounting surface)
6c Side surface 6d Resin portion 6g in dam Resin portion 6mb in gate Main body resin portion 6p Corner portion 6r Resin portion 6t in runner Resin portion 6v in groove Resin portion 7 in vent 7 Adhesive 11 Exposed portion (fin, corner lead)
20 Mounting board (motherboard, wiring board)
20a Top surface (mounting surface)
21 Terminal 21a Upper surface 50 Mold 51 Mold (mold)
51a Clamp surface (mold surface, pressing surface, surface)
51b Cavity (recessed part)
52 Lower mold (mold)
52a Clamp surface (mold surface, pressing surface, surface)
53 Resin film (film material)
55 Laser beam 56 Laser irradiation device 60 Plating tank 61 Plating solution 62 Cathode 63 Anode 65 Punch (cut punch, cutting blade)
66 Die (holding member, mold)
66a, 66c Upper die (mold)
66a1, 66a2 surface 66b lower die (die)
66w Protruding wall BL Boundary DM Dam part HS Heat stage (Lead frame heating stand)
HSa mounting surface LF Lead frame (base material)
LFa Upper surface LFb Lower surface LFd Device formation part (product formation part)
LFf Outer frame LFs Frame PD pad (bonding pad, electrode pad)
SD Metal film SDb Solder material SDt Partial TL Hanging lead

Claims (16)

A semiconductor device manufacturing method including the following steps:
(A) preparing a lead frame including a device forming portion and a frame portion located around the device forming portion;
here,
The device forming portion includes a chip mounting portion having a first surface and a second surface opposite to the first surface, a third surface facing the same direction as the first surface of the chip mounting portion, and the third surface. A plurality of leads having a fourth surface opposite to the surface, arranged next to the chip mounting portion, and respectively connected to the frame portion;
A groove portion is formed on the third surface of each of the plurality of leads so as to straddle each coupling portion of the plurality of leads and the frame portion,
(B) After the step (a), mounting a semiconductor chip having a surface, a plurality of electrode pads formed on the surface, and a back surface opposite to the surface on the first surface of the chip mounting portion The step of:
(C) After the step (b), a step of electrically connecting the plurality of electrode pads and the plurality of leads of the semiconductor chip through a plurality of conductive members, respectively.
(D) After the step (c), the plurality of leads, the semiconductor chip, and the plurality of conductive members are made of resin so that the third surface and the fourth surface of each of the plurality of leads are exposed. Are sealed between the main body resin portion for sealing the semiconductor chip and the plurality of conductive members, and the leads that are adjacent to each other among the plurality of leads, and each of the plurality of leads Forming a resin part in the dam that covers the side surface and a resin part in the groove that covers the groove part of each of the plurality of leads;
(E) The process of removing the resin part in a dam and the resin part in a groove | channel by irradiating a laser beam with respect to parts other than the said main body resin part among the said lead frames after the said (d) process. ;
here,
In the step of irradiating the laser beam, the laser beam is irradiated from the third surface side to the fourth surface side of each of the plurality of leads,
(F) After the step (e), forming a metal film on a portion of the lead frame exposed from the main body resin portion;
(G) A step of separating each of the plurality of leads from the frame portion after the step (f). In claim 1,
Each of the plurality of leads is a method of manufacturing a semiconductor device, wherein a width of the fourth surface is larger than a width of the third surface in a cross-sectional view in a direction orthogonal to the extending direction of the plurality of leads. In claim 2,
In the step (e), the laser beam is irradiated from a direction perpendicular to the third surface. In claim 1,
In the step (g), the mold is brought into contact with each of the third and fourth surfaces of each of the plurality of leads, from the fourth surface side of the groove portion toward the third surface side. A method of manufacturing a semiconductor device, wherein a cutting blade is inserted into each of the plurality of leads. In claim 4,
In the step (g), the mold is brought into contact with each of the third and fourth surfaces of each of the plurality of leads, and a part of the mold is brought into contact with the bottom surface of the groove, A manufacturing method of a semiconductor device, wherein the cutting blade is inserted into each of the plurality of leads from the fourth surface side of the groove portion toward the third surface side. In claim 5,
The mold to be brought into contact with the third surface in the step (g) is provided with a protruding wall protruding toward the lead at one end in the extending direction of the lead,
In the step (g), the cutting blade is inserted in a state where the tip surface of the protruding wall is in contact with the bottom surface of the groove. In claim 1,
In the step (f), the metal film made of a solder material is formed by a plating method. In claim 1,
Each of the plurality of leads includes an inner portion sealed by the main body resin portion and an outer portion exposed from the main body resin portion in the step (d),
The thickness of the frame portion is the same as the thickness of the inner portion of the lead. In claim 1,
Each of the plurality of leads includes an inner portion sealed by the main body resin portion and an outer portion exposed from the main body resin portion in the step (d),
The method of manufacturing a semiconductor device, wherein the outer portion includes a flat portion that is provided between the groove portion and the groove portion and the inner portion and is formed to have the same thickness as the inner portion. In claim 1,
In the step (e),
A method of manufacturing a semiconductor device, wherein the laser light is irradiated so as to leave a part of the resin part in the dam on the main body resin part side. In claim 4,
In the step (g), the mold is brought into contact with each of the third and fourth surfaces of each of the plurality of leads, and the mold is not brought into contact with the bottom surface of the groove. A cutting blade is inserted into each of the plurality of leads from the fourth surface side toward the third surface side, and each of the cut end portions of the plurality of leads is bent toward the third surface side. A method for manufacturing a semiconductor device. A semiconductor device manufacturing method including the following steps:
(A) preparing a lead frame including a device forming portion and a frame portion located around the device forming portion;
here,
The device forming portion includes a chip mounting portion having a first surface and a second surface opposite to the first surface, a third surface facing the same direction as the first surface of the chip mounting portion, and the third surface. A plurality of leads having a fourth surface opposite to the surface, arranged next to the chip mounting portion, and respectively connected to the frame portion;
A groove portion is formed on the third surface of each of the plurality of leads so as to straddle each coupling portion of the plurality of leads and the frame portion,
(B) After the step (a), mounting a semiconductor chip having a surface, a plurality of electrode pads formed on the surface, and a back surface opposite to the surface on the first surface of the chip mounting portion The step of:
(C) After the step (b), a step of electrically connecting the plurality of electrode pads and the plurality of leads of the semiconductor chip through a plurality of conductive members, respectively.
(D) After the step (c), the plurality of leads, the semiconductor chip, and the plurality of conductive members are made of resin so that the third surface and the fourth surface of each of the plurality of leads are exposed. Are sealed between the main body resin portion for sealing the semiconductor chip and the plurality of conductive members, and the leads that are adjacent to each other among the plurality of leads, and each of the plurality of leads Forming a resin part in the dam that covers the side surface and a resin part in the groove that covers the groove part of each of the plurality of leads;
(E) after the step (d), forming a metal film on a portion of the lead frame exposed from the main body resin portion;
(F) After the step (e), a step of separating each of the plurality of leads from the frame portion and bending the cut end portions of the plurality of leads toward the third surface side. In claim 12,
In the step (f), the mold is brought into contact with each of the third and fourth surfaces of each of the plurality of leads, and the mold is not brought into contact with the bottom surface of the groove. A cutting blade is inserted into each of the plurality of leads from the fourth surface side toward the third surface side, and the cut end portions of the plurality of leads are bent toward the third surface side. A method for manufacturing a semiconductor device. In claim 13,
In the step (e), the metal film made of a solder material is formed by a plating method. In claim 13,
Each of the plurality of leads includes an inner portion sealed by the main body resin portion and an outer portion exposed from the main body resin portion in the step (d),
The thickness of the frame portion is the same as the thickness of the inner portion of the lead. In claim 13,
Each of the plurality of leads includes an inner portion sealed by the main body resin portion and an outer portion exposed from the main body resin portion in the step (d),
The method of manufacturing a semiconductor device, wherein the outer portion includes a flat portion that is provided between the groove portion and the groove portion and the inner portion and is formed to have the same thickness as the inner portion.

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