JP2014007287A - Semiconductor device manufacturing method - Google Patents

Abstract

The reliability of a semiconductor device is improved.
A semiconductor chip 3 is mounted on each of a plurality of device regions 40a connected via tie bars 40tb, and a lead 4 provided in each device region 40a and the semiconductor chip 3 are electrically connected, and then a plurality of the device regions 40a are connected. The sealing body 6 is formed to collectively seal the device regions 40a. Moreover, after forming the sealing body 6, a metal film is formed on the exposed surface of the lead 4 by plating, and then the plurality of device regions 40a are divided. Moreover, after forming the sealing body 6 and before forming a metal film, it has the following processes. That is, a part of each of the lead 4 and the tie bar 40tb is removed by using the blade BD1 that is wider than a blade (not shown) used in the step of dividing the plurality of device regions 40a.
[Selection] Figure 26

Description

  The present invention relates to a semiconductor device manufacturing technique, for example, a technique effective when applied to a semiconductor device in which leads serving as external terminals are exposed on the lower surface and side surfaces of a sealing body.

  Japanese Patent Laying-Open No. 2009-200195 (Patent Document 1) describes a semiconductor device in which a side surface of an inner lead is covered with a metal layer.

  Japanese Unexamined Patent Publication No. 2000-294715 (Patent Document 2) describes a semiconductor device in which an inclined surface is provided on the lower surface side of the peripheral edge portion of a lead.

JP 2009-200195 A JP 2000-294715 A

  As a package mode of a semiconductor device, there is a package in which a lead as an external terminal is exposed on the lower surface side of a sealing body. Examples of such a package include a QFN (Quad Flat Non-leaded package) type and a SON (Small Outline Non-leaded package). As described above, when a package in which leads are exposed on the lower surface side of the sealing body is mounted on a mounting substrate, the package is mounted by bonding a bonding material such as solder to the exposed surface of the leads.

  However, when solder (bonding material) is bonded only to the lower surface of the lead, it is required to improve the mounting strength of the semiconductor device or to improve the visibility when the mounting state is inspected. Therefore, in addition to the lower surface of the lead, a technique for bonding solder (bonding material) to the side surface or forming a solder fillet (solder fillet) on the side surface of the lead is required.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  The outline of typical ones disclosed in the present application will be briefly described as follows.

  That is, a semiconductor chip is mounted on each of a plurality of device regions connected via tie bars, and the leads provided in each device region are electrically connected to the semiconductor chip. A sealing body to be sealed is formed. Moreover, after forming the sealing body, a metal film is formed on the exposed surface of the lead by a plating method, and then the plurality of device regions are divided. Moreover, after forming the said sealing body, and before forming the said metal film, it has the following processes. That is, a part of each of the lead and the tie bar is removed using the first blade having a width wider than the second blade used in the step of dividing the plurality of device regions.

  The effects obtained by the representative embodiments disclosed in the present application will be briefly described as follows.

  That is, according to the exemplary embodiment disclosed in the present application, the reliability of the semiconductor device can be improved.

It is a top view of the semiconductor device which is one embodiment. FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 3 is a side view of the semiconductor device shown in FIGS. 1 and 2. FIG. 2 is a perspective plan view showing the internal structure of the semiconductor device with the sealing body shown in FIG. 1 removed. It is sectional drawing along the AA line of FIG. It is sectional drawing along the BB line of FIG. It is an expanded sectional view which shows the state which apply | coated the bonding material to the mounting surface of the mounting board | substrate which mounts the semiconductor device shown in FIG. FIG. 8 is an enlarged plan view showing a mounting surface side of the mounting substrate shown in FIG. 7. FIG. 8 is an enlarged cross-sectional view illustrating a state where the semiconductor device illustrated in FIG. 5 is disposed on the mounting substrate illustrated in FIG. 7. FIG. 10 is an enlarged cross-sectional view illustrating a state where the bonding material illustrated in FIG. 9 is heat-treated to join the lead and the land. It is an expanded sectional view which shows the joining state of the semiconductor device and mounting board in the cross section along the BB line of FIG. FIG. 9 is an enlarged plan view illustrating a state in which a semiconductor device is mounted on the mounting substrate illustrated in FIG. 8 and bonded. It is explanatory drawing which shows typically the structure of the external appearance test process of the mounting structure shown in FIGS. It is explanatory drawing which shows the assembly flow of the semiconductor device shown in FIGS. It is a top view which shows the whole lead frame structure prepared at a lead frame preparation process. FIG. 16 is an enlarged plan view around two device regions among the plurality of device regions shown in FIG. 15. It is an expanded sectional view along the AA line of FIG. It is an expanded sectional view along the BB line of FIG. FIG. 17 is an enlarged plan view showing a state in which a semiconductor chip is mounted on the die pad shown in FIG. 16 via a bonding material. It is an expanded sectional view along the AA line of FIG. FIG. 20 is an enlarged plan view showing a state where the semiconductor chip shown in FIG. 19 and a plurality of leads are electrically connected through wires. It is an expanded sectional view along the AA line of FIG. FIG. 22 is a plan view showing a state where a sealing body is formed in the device region of the lead frame shown in FIG. 21. It is an expanded sectional view along the AA line of FIG. It is sectional drawing which shows the state which has arrange | positioned the lead frame in the shaping die in a sealing process. FIG. 25 is an enlarged cross-sectional view illustrating a state in which the lead frame illustrated in FIG. 24 is cut and the lower surface side of the tie bar is exposed. It is an expanded sectional view which expands further and shows the dicing area | region periphery shown in FIG. FIG. 24 is a plan view showing a state in which the lead frame shown in FIG. 23 is fixed with a dicing tape. FIG. 29 is an enlarged plan view showing a part of the lower surface side of the lead frame shown in FIG. 28 in an enlarged manner. FIG. 27 is an enlarged cross-sectional view showing a state in which a metal film is formed on exposed surfaces of the lead and die pad shown in FIG. 26. It is explanatory drawing which shows the outline | summary of the plating process by the electroplating method. FIG. 30 is an enlarged plan view showing a state where a metal film is formed on the lead frame shown in FIG. 29 and then separated for each device region. FIG. 31 is an enlarged cross-sectional view showing a state in which the lead frame shown in FIG. 30 is fixed to a dicing tape and separated into pieces. It is an expanded sectional view which expands further and shows the dicing area | region periphery of FIG. It is an enlarged plan view which shows the modification with respect to FIG. It is an expanded sectional view for demonstrating the shape of the cutting process part of the dicing blade shown in FIG. 26 and FIG. It is an expanded sectional view which shows the modification with respect to FIG. It is an expanded sectional view which shows the other modification with respect to FIG. FIG. 5 is a perspective plan view showing a modified example with respect to FIG. 4. FIG. 10 is a perspective plan view showing another modified example with respect to FIG. 4. It is sectional drawing which shows the modification with respect to FIG. FIG. 14 is an explanatory diagram when an appearance inspection process is performed in the configuration of another semiconductor device of FIG. 13;

(Description format, basic terms, usage in this application)
In the present application, the description of the embodiment will be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Regardless of the front and rear, each part of a single example, one is a part of the other, or a part or all of the modifications. In principle, repeated description of similar parts is omitted. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It does not exclude things that contain. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but includes a SiGe (silicon-germanium) alloy, other multi-component alloys containing silicon as a main component, and other additives. Needless to say, it is also included. Moreover, even if it says gold plating, Cu layer, nickel / plating, etc., unless otherwise specified, not only pure materials but also members mainly composed of gold, Cu, nickel, etc. Shall be included.

  In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  Moreover, in each figure of embodiment, the same or similar part is shown with the same or similar symbol or reference number, and description is not repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, hatching or a dot pattern may be added in order to clearly indicate that it is not a void or to clearly indicate the boundary of a region.

  The technology described in the following embodiments can be applied to various package type semiconductor devices in which the leads are exposed on the lower surface side of the sealing body. In this embodiment, as an example, an embodiment applied to a QFN type semiconductor device in which a plurality of leads which are external terminals are exposed from the sealing body on the lower surface (mounting surface) of the sealing body will be described. . 1 is a top view of the semiconductor device of the present embodiment, FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1, and FIG. 3 is a side view of the semiconductor device shown in FIGS. FIG. 4 is a perspective plan view showing the internal structure of the semiconductor device with the sealing body shown in FIG. 1 removed. 5 is a cross-sectional view taken along line AA in FIG. 1, and FIG. 6 is a cross-sectional view taken along line BB in FIG. Although FIG. 3 is a side view, in order to easily distinguish the sealing body 6 from the lead 4 and the metal film SD, each is shown with a pattern or hatching, and the positions of the leads 4 are two points. Shown with a chain line.

<Semiconductor device>
First, an outline of the configuration of the semiconductor device 1 according to the present embodiment will be described with reference to FIGS. The semiconductor device 1 according to the present embodiment is mounted on a die pad (chip mounting portion, tab) 2 (see FIGS. 4 to 6) and a die bond material DB (see FIGS. 4 to 6) on the die pad 2. And a semiconductor chip 3 (see FIGS. 4 to 6). Further, the semiconductor device 1 includes a plurality of leads (terminals, external terminals) 4 arranged around the semiconductor chip 3 (die pad 2) and a plurality of pads (electrodes, bonding pads) PD (FIG. 4, FIG. 4). A plurality of wires (conductive members) 5 (see FIGS. 4 and 5) for electrically connecting the leads 4 and the leads 4 respectively. A plurality of suspension leads TL are connected to the die pad 2. The semiconductor device 1 also includes a semiconductor chip 3, a plurality of wires 5, and a sealing body (resin body) 6 that seals part of the plurality of leads 4.

<Appearance structure>
First, the external structure of the semiconductor device 1 will be described. The planar shape of the sealing body (resin body) 6 shown in FIG. 1 is a rectangular shape, and is, for example, a square in the present embodiment. The sealing body 6 has an upper surface 6a, a lower surface (back surface, mounting surface) 6b (see FIG. 2) opposite to the upper surface 6a, and a side surface 6c located between the upper surface 6a and the lower surface 6b. ing. In the example shown in FIG. 5, the side surface 6c is orthogonal to the upper surface 6a and the lower surface 6b.

  As shown in FIG. 2, in the semiconductor device 1, a plurality of leads 4 are arranged along each side (side surface 6 c) of the sealing body 6. The plurality of leads 4 are each made of a metal material, and in the present embodiment, for example, a metal film made of nickel (Ni) on the surface of a base material made of, for example, copper (Cu) or copper (Cu) (not shown). It is made of a laminated metal member formed.

  Further, as shown in FIG. 2, in the lower surface 6 b of the sealing body 6, a part (lower surface 4 b) of each lead 4 is exposed from the sealing body 6. A metal film SD is formed on the exposed portion of the lead 4 from the sealing body 6, and the lower surface 4 b is covered with the metal film SD. The metal film SD is a plating film formed by, for example, a plating method, and is made of, for example, a solder material. The metal film SD functions as a bonding material when the lead 4 is bonded to a mounting substrate side terminal to be described later.

  The metal film SD (solder material) of the present embodiment is made of so-called lead-free solder that does not substantially contain lead (Pb). For example, only tin (Sn), tin-bismuth (Sn-Bi), or For example, tin-copper-silver (Sn-Cu-Ag). Here, the lead-free solder means a lead (Pb) content of 0.1 wt% or less, and this content is defined as a standard of the RoHS (Restriction of Hazardous Substances) directive. Hereinafter, in the present embodiment, when a solder material or a solder component is described, it indicates lead-free solder unless otherwise specified.

  Further, as shown in FIG. 2, a stepped portion 10 is provided on the peripheral edge portion of the lower surface (mounting surface) of the semiconductor device 1. The stepped portion 10 is continuously formed on the peripheral edge of the lower surface of the semiconductor device 1 over the entire circumference. In the example shown in FIG. 3, each of the plurality of leads 4 includes a step surface (lower surface, intermediate surface) 4f that is continuous with the side surface 4c and is positioned between the lower surface 4b and the upper surface 4a. Further, the side surface 4c is provided with a side surface 4e continuous to the lower surface 4b and the step surface 4f. In addition, the sealing body 6 includes a step surface (lower surface, intermediate surface) 6f that is continuous with the side surface 6c and located between the lower surface 6b and the upper surface 6a. Further, a side surface 6e is provided on the inner side of the side surface 6c. Although details will be described later, such a configuration improves the visibility in the inspection after mounting. Further, the mounting strength can be improved.

  Further, as shown in FIG. 3, the side surface 4c of the lead 4 is not covered with the metal film SD but is exposed. The reason for the structure in which the side surface 4c is exposed from the metal film SD is derived from the manufacturing process of the semiconductor device 1, and the details will be described when the manufacturing method of the semiconductor device is described.

  Next, as shown in FIG. 2, the lower surface 2 b of the die pad (chip mounting portion, tab) 2 is exposed from the sealing body 6 on the lower surface 6 b of the sealing body 6. That is, the semiconductor device 1 is a die pad exposed type (tab exposed type) semiconductor device. The die pad 2 is made of a metal material having a higher thermal conductivity than that of the sealing body 6. In this embodiment, for example, nickel (Ni) is formed on the surface of a base material made of, for example, copper (Cu) or copper (Cu). ) Formed of a laminated metal film (not shown). As described above, the die pad exposed semiconductor device is a semiconductor in which the die pad 2 is not exposed by exposing a metal member (die pad 2) such as copper (Cu) having a higher thermal conductivity than that of the sealing body 6. Compared with the device, the heat dissipation of the package can be improved. 2 and 3, the lower surface 2b of the die pad 2 is formed with a metal film SD that functions as a bonding material at the time of mounting, and covers the lower surface of the substrate. The metal film SD is a plating film (solder film) formed by, for example, a plating method as described above.

  As shown in FIGS. 2 and 3, in the semiconductor device 1, a part of the suspension lead TL is exposed from the sealing body 6 outside the corner portion 6 k (intersection of the side surface 6 c) of the sealing body 6. Yes. Specifically, as shown in FIGS. 4 and 6, one end portion (sealing portion TL1) of the suspension lead TL is connected to the die pad 2 (formed integrally), and the other end portion (exposed portion TL2). Is exposed from the sealing body 6 at the corner 6k. That is, the suspension lead of the present embodiment is a so-called I suspension type. Since the suspension lead TL is formed integrally with the die pad 2, the suspension lead TL is made of the same metal material as the die pad 2. In the present embodiment, for example, copper (Cu) or a laminated metal film in which a metal film (not shown) made of nickel (Ni) is formed on the surface of a base material made of copper (Cu). Further, as shown in FIG. 2, a metal film SD that functions as a bonding material at the time of mounting is formed on the lower surface of the exposed portion of the suspension lead TL, and covers the lower surface of the base material. The metal film SD is a solder film formed by, for example, a plating method as described above.

  In other words, the semiconductor device 1 includes a step portion 10 continuously formed so as to surround the peripheral portion of the lower surface 6b of the sealing body, and the plurality of leads 4 and the plurality of suspension leads TL are sealed in the step portion 10. It is exposed from the stationary body 6.

  By exposing a part of the suspension lead TL from the sealing body 6 in this manner, the exposed portion of the suspension lead TL can be joined to the terminal of the mounting substrate when the semiconductor device 1 is mounted on the mounting substrate described later. Thereby, the mounting strength of the semiconductor device 1 can be improved. However, as a modification, a structure in which the exposed portion of the suspension lead TL as shown in FIG. 2 is not provided can be employed.

<Internal structure>
Next, the internal structure of the semiconductor device 1 will be described. As shown in FIG. 4, the upper surface (chip mounting surface) 2a of the die pad 2 has a quadrangular shape in plan view. In the present embodiment, for example, it is a square. In the example shown in FIG. 4, the outer size (planar size) of the die pad 2 is larger than the outer size of the semiconductor chip 3 (planar size of the back surface 3b). As described above, the semiconductor chip 3 is mounted on the die pad 2 having an area larger than the outer size, and the lower surface 2b of the die pad 2 is exposed from the sealing body 6, thereby improving heat dissipation.

  Further, as shown in FIG. 4, the semiconductor chip 3 is mounted on the die pad 2. The semiconductor chip 3 is mounted at the center of the die pad 2. As shown in FIG. 5, the semiconductor chip 3 is mounted on the die pad 2 via a die bond material (adhesive material) DB with the back surface 3 b facing the top surface 2 a of the die pad 2. That is, it is mounted by a so-called face-up mounting method in which the surface (back surface 3b) opposite to the surface (main surface) 3a on which the plurality of pads PD are formed is opposed to the chip mounting surface (upper surface 2a). This die bond material DB is an adhesive when the semiconductor chip 3 is die-bonded. In the present embodiment, for example, an epoxy thermosetting resin contains metal particles made of silver (Ag) or the like. Die bond material DB is used.

  As shown in FIG. 4, the planar shape of the semiconductor chip 3 mounted on the die pad 2 is a quadrangle. In the present embodiment, for example, it is a square. As shown in FIG. 5, the semiconductor chip 3 includes a front surface (main surface, upper surface) 3a, a back surface (main surface, lower surface) 3b opposite to the front surface 3a, and a space between the front surface 3a and the back surface 3b. And a side surface 3c. As shown in FIGS. 4 and 5, a plurality of pads (bonding pads) PD are formed on the surface 3a of the semiconductor chip 3, and in the present embodiment, the plurality of pads PD are provided on each surface 3a. It is formed along the side. Although not shown, the main surface of the semiconductor chip 3 (specifically, a semiconductor element formation region provided on the upper surface of the base material (semiconductor substrate) of the semiconductor chip 3) includes a plurality of semiconductor elements (circuit elements). Is formed. In addition, the plurality of pads PD are connected to each other via wiring (not shown) formed in a wiring layer disposed inside the semiconductor chip 3 (specifically, between the surface 3a and a semiconductor element formation region not shown). It is electrically connected to the semiconductor element.

  The semiconductor chip 3 (specifically, the base material of the semiconductor chip 3) is made of, for example, silicon (Si). In addition, an insulating film is formed on the surface 3a to cover the base material and wiring of the semiconductor chip 3, and each surface of the plurality of pads PD is exposed from the insulating film in the opening formed in the insulating film. doing. The pad PD is made of metal, and in the present embodiment, for example, aluminum (Al) or an alloy layer mainly composed of aluminum (Al).

  As shown in FIG. 4, a plurality of leads 4 made of, for example, the same copper (Cu) as that of the die pad 2 are arranged around the semiconductor chip 3 (specifically, around the die pad 2). The plurality of pads (bonding pads) PD formed on the surface 3 a of the semiconductor chip 3 are electrically connected to the plurality of leads 4 and the plurality of wires (conductive members) 5, respectively. The wire 5 is made of, for example, gold (Au), a part (for example, one end) of the wire 5 is bonded to the pad PD, and the other part (for example, the other end) is bonded to the upper surface 4 a of the lead 4. It is joined to. Although not shown, a plating film is formed on the surface of the bonding region of the lead 4 (specifically, the surface of the plating film made of nickel (Ni)). The plating film is made of, for example, silver (Ag) or gold (Au). Bonding strength with the wire 5 made of gold (Au) by forming a plating film made of silver (Ag) or gold (Au) on the surface of the bonding region (wire bonding region) of the lead 4 (inner lead part) Can be improved.

  Further, as shown in FIG. 5, the lead 4 is positioned on the opposite side of the upper surface (wire bonding surface) 4 a and the upper surface 4 a to be sealed by the sealing body 6, and the sealing body 6 on the lower surface 6 b of the sealing body 6. A lower surface (mounting surface) 4b exposed from the surface. The lead 4 has a side surface 4c on the outer peripheral side. Further, as described above, the lead 4 includes a step surface (lower surface, intermediate surface) 4f that is continuous with the side surface 4c and is positioned between the lower surface 4b and the upper surface 4a. Further, the side surface 4c is provided with a side surface 4e continuous to the lower surface 4b and the step surface 4f.

  As shown in FIG. 4, a plurality of suspension leads TL are connected (linked) to the die pad 2. One end of each of the plurality of suspension leads TL is connected to a corner (corner) of the die pad 2 that forms a quadrangle in plan view. Each of the plurality of suspension leads TL has the other end extending toward the corner 6k of the sealing body 6 and is exposed from the sealing body 6 at the corner 6k. The suspension leads TL are extended toward the corners 6k of the sealing body 6 so that the arrangement of the leads 4 arranged along each side (each main side) of the sealing body 6 is not hindered. Therefore, the number of leads 4, that is, the number of terminals of the semiconductor device 1 can be increased. As shown in FIG. 6, a part of the suspension lead TL (sealing portion TL <b> 1) is half-etched from the lower surface side, and the lower surface side is sealed by the sealing body 6. Thereby, since the suspension lead TL and the sealing body 6 can be firmly fixed, it is possible to prevent the suspension lead TL from falling off the sealing body 6.

<Method of mounting semiconductor device>
Next, a method for mounting the semiconductor device described with reference to FIGS. FIG. 7 is an enlarged cross-sectional view showing a state in which a bonding material is applied to the mounting surface of the mounting substrate on which the semiconductor device shown in FIG. 5 is mounted. FIG. 8 is an enlarged plan view showing the mounting surface side of the mounting board shown in FIG. 9 is an enlarged cross-sectional view showing a state in which the semiconductor device shown in FIG. 5 is arranged on the mounting substrate shown in FIG. 7, and FIG. 10 is a process in which the bonding material shown in FIG. It is an expanded sectional view which shows the state which carried out. FIG. 11 is an enlarged cross-sectional view showing a bonding state of the semiconductor device and the mounting substrate in a cross section taken along line BB in FIG. FIG. 12 is an enlarged plan view showing a state where the semiconductor device is mounted on the mounting substrate shown in FIG. 8 and bonded.

  In the present embodiment, first, the mounting substrate 20 shown in FIGS. 7 and 8 is prepared (substrate preparation step). The mounting substrate (motherboard, wiring substrate) 20 has an upper surface (mounting surface) 20a that is an electronic component mounting surface, and the semiconductor device 1 described with reference to FIGS. 1 to 6 is mounted on the upper surface 20a. A plurality of lands (terminals) 21 which are terminals on the mounting substrate side are arranged on the upper surface 20a. In the example shown in FIG. 8, the mounting substrate 20 includes a plurality of lands (lead connection terminals) 21a, lands (die pad connection terminals) 21b, and a plurality of lands (suspended lead connection terminals) 21c. The upper surface 20 a is covered with an insulating film (solder resist film) 22, and the insulating film 22 is formed with openings at positions overlapping the plurality of lands 21, and in the openings, the plurality of lands 21 are separated from the insulating film 22. Exposed.

  Next, as shown in FIG. 7, bonding materials 23 are respectively arranged (applied) on the plurality of lands 21 provided on the upper surface 20 a of the mounting substrate 20 (bonding material arrangement step). In the example shown in FIG. 7, the bonding material 23 is a solder material called cream solder (or paste solder). Cream solder contains a solder component that becomes a conductive bonding material and a flux component that activates the surface of the bonding portion, and is paste-like at room temperature. The bonding material can be applied by, for example, screen printing. By this step, the bonding material 23 is disposed on each of the plurality of lands 21. In the example shown in FIG. 2, in the semiconductor device 1, each of the plurality of leads 4, the die pad 2, and the plurality of suspension leads TL is exposed on the lower surface 6 b of the sealing body 6. 21 is connected. Therefore, in this step, the bonding material 23 is applied to each of the plurality of lands 21a, lands 21b, and the plurality of lands 21c shown in FIG.

  Next, as shown in FIG. 9, the semiconductor device 1 is disposed on the upper surface 20a of the mounting substrate 20 (package mounting step). In this step, the semiconductor device 1 is arranged on the upper surface 20 a that is the mounting surface of the mounting substrate 20 by aligning the positions of the terminals of the semiconductor device 1 with the positions of the lands 21 on the mounting substrate 20. Specifically, in this step, the die pad 2 of the semiconductor device 1 is on the land 21b of the mounting substrate 20, the plurality of leads 4 are on the plurality of lands 21a, and the plurality of suspension leads TL (see FIG. 6) are the plurality of lands 21c. (See FIG. 8).

  Next, heat treatment is performed in a state where the semiconductor device 1 is disposed on the mounting substrate 20, and the plurality of leads 4 and the plurality of lands 21 a are bonded via bonding materials 24 as shown in FIG. 10. (Reflow process). The bonding material 24 shown in FIG. 10 is a conductive member (solder material) formed by integrating the solder component contained in the bonding material 23 shown in FIG. 9 and the solder component of the metal film SD. One surface of the bonding material 24 is bonded to the lower surface 4b of the lead 4, and the other surface of the bonding material 24 is bonded to the exposed surface of the land 21a. That is, in this step, each of the plurality of leads 4 and the plurality of lands 21 a is electrically connected via the bonding material 24.

  On the land 21b, which is a die pad connection terminal, one surface of the bonding material 24 is bonded to the lower surface 2b of the die pad 2, and the other surface of the bonding material 24 is bonded to the exposed surface of the land 21b. That is, in this step, a heat dissipation path connected from the die pad 2 to the mounting substrate 20 is formed. When the die pad 2 is used as a terminal for supplying a reference potential, for example, the die pad 2 and the land 21b are electrically connected through the bonding material 24 in this step.

  In this step, when the bonding material 23 shown in FIG. 9 is heated, the flux component contained in the bonding material 23 flows out and activates the exposed surfaces of the metal film SD and the lands 21. Thereby, the solder component, the metal film SD, and the land 21 included in the bonding material 23 are easily wetted. When further heated, the melting point of the solder component is reached and the solder component is melted. At this time, since the metal film SD and the land 21 are easily wetted with the solder (the solder wettability is high), the solder component spreads on the exposed surface of the land 21 and the surface on which the metal film SD is formed. Thereby, as shown in FIG. 10, the bonding material 24 spreads over the entire exposed surface of the land 21. Further, the bonding material 24 wets and spreads over the entire lower surface 2b, which is the exposed surface of the die pad 2. Further, the bonding material 24 spreads wet on the lower surface 4 b and the stepped portion 10 among the exposed surfaces of the leads 4. On the other hand, as shown in FIG. 9, since the metal film SD is not formed on the side surface 4c, the bonding material 24 shown in FIG. In particular, when the bonding material 24 is composed of lead-free solder, the wettability tends to be lower than that of so-called lead solder. Therefore, the bonding material 24 gets wet on the side surface 4c where the metal film SD is not formed. hard.

  Here, the mounting strength of the semiconductor device 1 will be described. After the semiconductor device 1 is mounted on the mounting substrate 20, a temperature cycle load is applied in a use environment. The temperature cycle load is a load generated when the environmental temperature of the mounting structure in which the semiconductor device 1 is mounted on the mounting substrate 20 is repeatedly changed. As the temperature cycle load, for example, there is a stress generated due to a difference in coefficient of linear expansion of each member constituting the mounting structure. This stress tends to concentrate on the peripheral edge of the mounting surface of the semiconductor device 1. For this reason, in order to extend the temperature cycle life (the number of temperature cycles until the connection portion is damaged by the temperature cycle load), the strength of the connection portion between the lead 4 and the land 21 arranged at the peripheral portion of the mounting surface is improved. It is preferable.

  Therefore, the semiconductor device 1 of the present embodiment is provided with a stepped portion 10 that is continuous with the side surface 4 c on the peripheral edge side of the lead 4. As a result, the thickness of the bonding material 24 can be increased just below the side surface 4c where the stress generated by the temperature cycle is most likely to concentrate. Therefore, it is possible to improve the connection reliability of the semiconductor device 1 by improving the strength of the joint between the lead 4 and the land 21a. The semiconductor device 1 also includes a side surface 4e that is continuous with the lower surface 4b of the lead 4 and the step surface 4f. Thereby, since it joins with the joining material 24 in the some surface which mutually cross | intersects, the joining strength of the joining material 24 and the lead | read | reed 4 can be improved. Further, by providing the step portion 10 on the lower surface 4 b side of the lead 4, the contact area between the bonding material 24 and the lead 4 is increased, so that the bonding strength between the lead 4 and the bonding material 24 can be improved.

  In particular, when the semiconductor device 1 is downsized, the size of each lead 4 is reduced, so that the area of the lower surface 4b that is the mounting surface is reduced. According to the present embodiment, even when the area of the lower surface 4b of the lead 4 is reduced by downsizing, the step strength 10 can be provided to suppress a reduction in mounting strength. In other words, by improving the mounting strength of the lead 4, the area of the lower surface 4b of the lead 4 can be reduced, so that the semiconductor device 1 can be reduced in size.

  In the example shown in FIG. 11, a part of the suspension lead TL (exposed portion TL2) is connected to the land 21c of the mounting substrate 20 through the bonding material 24. In the present embodiment, since the suspension lead TL is formed integrally with the die pad 2, it is not necessary to electrically connect the suspension lead TL and the land 21c. However, the connection strength between the semiconductor device 1 and the mounting substrate 20 can be improved by fixing the suspension leads TL and the lands 21 c via the bonding material 24. For example, the stress concentration is alleviated by dispersing the stress concentrated on the bonding material 24 connecting the lead 4 and the land 21a shown in FIG. 10 to the bonding material 24 connecting the suspension lead TL and the land 21a shown in FIG. be able to. In order to wet the bonding material 24 on the exposed portion TL2 of the suspension lead TL, a metal film SD (see FIG. 6) is formed on the exposed portion TL2, and the metal film SD and the bonding material are used in the reflow process. 23 need to be contacted. As shown in FIG. 11, only the lower surface of the suspension lead TL is exposed at the exposed portion TL2 of the suspension lead TL. In other words, the lead 4 shown in FIG. 10 has a side surface 4e that connects the step surface 4f and the lower surface 4b, and thus the bonding material 24 gets wet to the step surface 4f. On the other hand, as shown in FIG. 11, the suspension lead TL exposes the step surface of the lower surface (surface corresponding to the step surface 4f in FIG. 10) of the exposed portion TL2 disposed at a position higher than the lower surface 6b of the sealing body 6. Like the side surface 4e shown in FIG. 10, there is no side surface from the height of the lower surface 6b of the sealing body 6 to the lower surface of the exposed portion TL2. For this reason, in the bonding material arranging step, more bonding material 23 is applied to the suspension lead connection land 21c shown in FIG. 8 than the lead connection land 21a, and the lower surface of the exposed portion TL2 and the bonding material 23 are applied. It is preferable to make it contact.

  In addition, after this process, when the residue of the flux component contained in the bonding | jointing material 23 shown in FIG. 9 remains, a washing process is performed as needed and this residue is removed.

  Next, the appearance of the semiconductor device 1 mounted on the mounting substrate 20 is inspected (inspection process). In this step, in particular, a connection portion between the semiconductor device 1 and the mounting substrate 20, that is, a bonding state by the bonding material 24 is inspected. In this step, for example, the appearance of the connected state can be visually inspected from the upper surface side of the semiconductor device 1 (the upper surface 6a side of the sealing body 6 shown in FIG. 12), but image processing is performed from the viewpoint of efficiently performing the inspection. It is preferable to inspect using this.

  For example, it can test | inspect using the inspection apparatus (appearance inspection apparatus) 30 typically shown in FIG. FIG. 13 is an explanatory view schematically showing a configuration of an appearance inspection process of the mounting structure shown in FIGS. 10 to 12. FIG. 42 is an explanatory diagram when the appearance inspection process is performed in the configuration of the other semiconductor device of FIG. The inspection apparatus 30 includes a light irradiation unit 31 that irradiates light to a portion to be inspected, an image pickup unit 32 that detects and images light reflected by the portion to be inspected, and a control electrically connected to the image pickup unit 32 A portion 33 is provided. The control unit 33 includes, for example, an image processing unit that performs processing (image processing) on the data obtained by the imaging unit 32, a determination unit that evaluates data after image processing, and performs pass / fail determination. As described above, in this step, in particular, since the bonding state by the bonding material 24 is inspected, the light irradiation unit 31 is disposed on the upper surface side of the semiconductor device 1 (the upper surface 6a side of the sealing body 6), and the bonding material Light is irradiated toward 24. The imaging unit 32 is also arranged on the upper surface side of the semiconductor device 1 (upper surface 6a side of the sealing body 6), and detects and images the light reflected by the bonding material 24.

  Here, when the side surface 4c and the lower surface 4b of the lead 4 are connected like the semiconductor device H1 shown in FIG. 42, in other words, when the step portion 10 shown in FIG. 13 is not formed, the amount of the bonding material 24 Is difficult to adjust. That is, since the distance between the lower surface of the lead 4 and the land 21 is short at the periphery of the semiconductor device H1, if the amount of the bonding material 24 is large, a part of the bonding material 24 rises upward on the outside of the lead 4. It is easy to become a shape. However, in this case, the following problem occurs.

  That is, as described above, in the inspection process, the bonding material 24 outside the lead 4 is photographed, and pass / fail judgment is performed using the obtained image data. However, when the bonding material 24 swells upward outside the lead 4 as in the semiconductor device H1, the light reflection direction becomes unstable due to the shape of the swelled portion. For this reason, the amount of reflected light that reaches the imaging unit 32 is reduced, causing erroneous determination.

  On the other hand, in the case of the semiconductor device 1 of the present embodiment, as shown in FIG. 13, since the step portion 10 is provided, the separation distance of the region between the step portion 10 and the land 21 is such that the lower surface 4 b and the land 21. It is larger than the separation distance of the area between. In other words, the thickness of the bonding material 24 disposed between the stepped portion 10 and the land 21 is larger than the thickness of the bonding material 24 disposed between the lower surface 4 b and the land 21. If the stepped portion 10 is provided at the peripheral edge as in the semiconductor device 1 and the distance between the stepped surface 4f and the land 21 is increased, the amount of the bonding material 24 can be adjusted more easily than the semiconductor device H1 shown in FIG. . That is, even when the amount of the bonding material 24 is large, it is difficult for a part of the bonding material 24 to rise upward as shown in FIG. 42. For example, the exposed surface is flat or slightly depressed as shown in FIG. However, it tends to be a fillet shape.

  As shown in FIG. 13, when the exposed surface of the bonding material 24 has a flat or slightly recessed fillet shape, the reflection direction of the light applied to the bonding material 24 is stabilized. For this reason, compared with the example shown in FIG. 42, the amount of reflected light reaching the imaging unit 32 is increased, and an accurate determination process can be performed.

  As described above, according to the present embodiment, it is possible to extend the temperature cycle life of the semiconductor device 1 by improving the bonding strength of the bonding portion by the bonding material 24. That is, the reliability of the semiconductor device 1 can be improved. In addition, as shown in FIG. 11, the mounting strength of the semiconductor device 1 can be further improved by exposing a part of the suspension lead TL and allowing the exposed portion TL2 of the suspension lead TL to be joined to the land 21c. . Also, as shown in FIG. 13, according to the present embodiment, the exposed surface of the bonding material 24 is flat or slightly depressed, and thus has a fillet shape, so that it is possible to easily detect problems during mounting. As a result, the mounting reliability of the semiconductor device 1 can be improved.

<Manufacturing process of semiconductor device>
Next, the manufacturing process of the semiconductor device 1 shown in FIGS. 1 to 13 will be described. The semiconductor device 1 in the present embodiment is manufactured along the assembly flow shown in FIG. FIG. 14 is an explanatory diagram showing an assembly flow of the semiconductor device shown in FIGS.

1. Lead frame preparation process;
First, as a lead frame preparation step shown in FIG. 14, a lead frame (base material) 40 as shown in FIG. 15 is prepared. FIG. 15 is a plan view showing the entire structure of the lead frame prepared in the lead frame preparation step, and FIG. 16 is an enlarged plan view of the periphery of two device regions among the plurality of device regions shown in FIG. 17 is an enlarged cross-sectional view taken along the line AA in FIG. 16, and FIG. 18 is an enlarged cross-sectional view taken along the line BB in FIG.

  The lead frame 40 prepared in this step includes a plurality of device regions (product formation regions) 40a inside the outer frame 40b. In the example shown in FIG. 15, the lead frame 40 includes 16 device regions 40 a arranged in a matrix in the row direction and 4 device regions 40 a in the column direction, and has a total of 64 device regions 40 a. The lead frame 40 is made of metal, and in this embodiment, for example, a metal film (not shown) made of nickel (Ni) is formed on the surface of a base material made of copper (Cu) or copper (Cu), for example. It consists of a laminated metal film.

  Further, a dicing area 40c surrounding each device area 40a is arranged between the device areas 40a. This dicing area 40c is an area to be cut in the individualization step (see FIG. 14) described later. In addition, as shown in FIG. 16, the dicing region 40 c is formed so as to surround the plurality of leads 4. A tie bar 40tb is disposed in the dicing area 40c so as to surround the periphery of the device area 40a. The tie bar 40tb is formed integrally with the leads 4 and the outer frame (frame body) 40b shown in FIG.

  As shown in FIG. 16, a die pad 2 having a quadrangular shape in plan view is formed at the center of each device region 40a. The suspension leads TL are connected to the four corners of the die pad 2, respectively, and are arranged to extend toward the corners of the device region 40a. A plurality of leads 4 are formed around the die pad 2 between the plurality of suspension leads TL. The plurality of leads 4 are respectively connected to the die pad 2 to tie bars 40 tb arranged outside the plurality of leads 4.

  In other words, the lead frame 40 is disposed between the tie bar 40tb, the die pad 2 disposed inside the tie bar 40tb in a plan view, the plurality of suspension leads TL connecting the die pad 2 and the tie bar 40tb, and the die pad 2 and the tie bar 40tb. A plurality of leads 4.

  In other words, as shown in FIG. 16, the lead frame 40 has adjacent device regions 40a, and a plurality of leads 4 are provided in each device region 40a. A tie bar 40tb is provided between one device region 40a and the other device region 40a, and a plurality of leads 4 are connected to the tie bar 40tb.

  In addition, a part of the lead frame 40 is processed in advance so as to reduce the plate thickness. In other words, as shown in FIG. 16 with hatching, the lead frame 40 has a thin portion (half-etched portion) 40hf that is thinner than other regions. In the example shown in FIGS. 16 to 17, the thin portion 40 hf is formed by a half etching process in which an etching process is performed halfway in the thickness direction from the lower surface 4 b side of the lead 4. Specifically, the thickness of a part of the lead 4 adjacent to the tie bar 40 tb and the tie bar 40 tb is thinner than the thickness of the other part of the lead 4.

  As shown in FIG. 17, a portion of the tie bar 40tb and the lead 4 disposed in the dicing region 40c between the adjacent device regions 40a is a thin portion 40hf. In other words, the tie bar 40tb and a part of the lead 4 are partly removed from the lower surface side of the lead frame, and are thinner than the other part of the lead 4. In other words, the tie bar 40tb and a part of the lead 4 are subjected to a half etching process in advance. Thus, the amount of the metal member to be cut can be reduced in the singulation process shown in FIG. 14 by setting the inside of the dicing region 40c to the thin portion 40hf. For this reason, the metal burr | flash etc. which arise at the time of cutting can be reduced, and the reliability of a semiconductor device can be improved.

  Further, as shown in FIG. 18, the suspension lead TL is a thin portion 40hf. By making the suspension lead TL into the thin portion 40hf in this way, the lower surface side of the suspension lead TL can be sealed in the sealing step shown in FIG. 14, so that the die pad 2 is removed from the sealing body. Can be suppressed.

2. With semiconductor chip;
Next, as a semiconductor chip mounting step shown in FIG. 14, the semiconductor chip 3 is mounted on the die pad 2 via the die bond material DB as shown in FIGS. 19 is an enlarged plan view showing a state in which a semiconductor chip is mounted on the die pad shown in FIG. 16 via a bonding material, and FIG. 20 is an enlarged cross-sectional view taken along line AA in FIG.

  In the example shown in FIG. 20, a so-called face-up mounting method in which the back surface 3 b of the semiconductor chip 3 (the surface opposite to the front surface 3 a on which a plurality of pads PD are formed) is opposed to the upper surface 2 a of the die pad 2. Installed in. Further, as shown in FIG. 19, the semiconductor chip 3 is mounted at the center of the die pad 2 so that each side of the surface 3 a is arranged along each side of the die pad 2.

  In this step, for example, the semiconductor chip 3 is mounted via a die bond material DB which is an epoxy-based thermosetting resin. The die bond material DB is a paste material having fluidity before being cured (thermoset). is there. When the paste material is used as the die bond material DB in this way, first, the die bond material DB is applied onto the die pad 2, and then the back surface 3 b of the semiconductor chip 3 is bonded to the upper surface 2 a of the die pad 2. Then, when the die bond material DB is cured (for example, heat treatment is performed) after bonding, the semiconductor chip 3 is fixed on the die pad 2 via the die bond material DB as shown in FIG.

  In this step, the die bond material DB and the semiconductor chip 3 are respectively disposed on the die pads 2 provided in the plurality of device regions 40a. Then, the semiconductor chip 3 is mounted in each device region 40a.

  In the present embodiment, the embodiment in which the paste material made of the thermosetting resin is used for the die bond material DB has been described, but various modifications can be applied. For example, instead of a paste material, an adhesive material, which is a tape material (film material) having adhesive layers on both sides, is attached in advance to the back surface 3b of the semiconductor chip 3, and the semiconductor chip 3 is placed on the die pad 2 via the tape material. May be installed.

3. Wire bonding process;
Next, as a wire bonding step shown in FIG. 14, a plurality of pads PD and a plurality of leads 4 of the semiconductor chip 3 are connected via a plurality of wires (conductive members) 5 as shown in FIGS. 21 and 22. , Each electrically connected. 21 is an enlarged plan view showing a state where the semiconductor chip shown in FIG. 19 and a plurality of leads are electrically connected via wires, and FIG. 22 is an enlarged cross-sectional view taken along line AA in FIG. is there.

  In this step, for example, the lead frame 40 on which the semiconductor chip 3 is mounted on the die pad 2 in each device region 40a is placed on a heat stage (lead frame heating table) (not shown). Then, the pad PD of the semiconductor chip 3 and the lead 4 are electrically connected via the wire 5. In the present embodiment, the wire 5 is connected by a so-called nail head bonding method in which, for example, the wire 5 is supplied via a capillary (not shown), and the wire 5 is bonded using ultrasonic waves and thermocompression bonding.

  A plating film made of, for example, silver (Ag) or gold (Au) is formed on a part of the lead 4 (bonding region disposed at the tip of the inner lead part), and a part of the wire 5 is The lead 4 is electrically connected through this plating film. The wire 5 is made of metal, and in this embodiment, is made of, for example, gold (Au).

  Further, in this embodiment, after connecting a part (end part) of the wire to the pad PD of the semiconductor chip 3, the other part of the wire 5 is connected to the bonding region (a part of the upper surface of the lead 4) in the lead 4. The wires are connected by the so-called positive bonding method. The bonding region is located on the opposite side of the lower surface 4b. That is, since the wire 5 is bonded to the thick portion of the lead 4, a sufficient load can be applied when the wire 5 is bonded to the lead 4, thereby improving the bonding strength. Can do.

  Further, in this step, the wires 5 are bonded to the plurality of leads 4 respectively provided in the plurality of device regions 40a. As a result, in each device region 40 a, the semiconductor chip 3 and the plurality of leads 4 are electrically connected via the plurality of wires 5.

4). Sealing step;
Next, as a sealing step shown in FIG. 14, as shown in FIGS. 23 and 24, a sealing body (sealing body) 6 is formed, the semiconductor chip 3 (see FIG. 24), and a plurality of wires 5 (see FIG. 24) and a part of each of the plurality of leads 4 (see FIG. 24). 23 is a plan view showing a state in which a sealing body is formed in the device region of the lead frame shown in FIG. 21, and FIG. 24 is an enlarged cross-sectional view taken along the line AA in FIG. FIG. 25 is a cross-sectional view showing a state in which the lead frame is disposed in the molding die in the sealing step. FIG. 24 shows a part of the molding die 50 shown in FIG.

  In this step, as shown in FIG. 24, the sealing body 6 is formed so that the lower surfaces 4b of the plurality of leads 4 provided in each device region 40a are exposed. Moreover, in this Embodiment, as shown in FIG. 24, the sealing body 6 is formed so that the lower surface 2b of the die pad 2 provided in each device area | region 40a may each be exposed. In this step, for example, a so-called transfer mold method is shown in FIG. 23, in which a softened resin is press-fitted into the molding die 50 and cured after the lead frame 40 is sandwiched between the molding die 50 shown in FIG. The sealing body 6 is formed.

  The molding die 50 includes an upper die (die) 51 arranged on the upper side of the lead frame 40 and a lower die (die) 52 arranged on the lower side of the lead frame 40. The upper die 51 includes a clamp surface (mold surface, pressing surface, surface) 51a for pressing the lead frame 40, and a cavity (recessed portion) 51b formed inside the clamp surface 51a. The lower mold 52 includes a clamp surface (mold surface, pressing surface, surface) 52a that is disposed so as to face the clamp surface 51a and presses the lead frame 40. In this embodiment, since a QFN type package is manufactured, no cavity is formed inside the clamp surface 52a of the lower mold 52.

  In the sealing process, a sealing resin is press-fitted into the cavity 51b, and a part of each of the semiconductor chip 3 (see FIG. 24), the plurality of wires 5 (see FIG. 24), and the plurality of leads 4 (see FIG. 24). Is sealed. And the sealing body 6 shown in FIG. 23 is formed by thermosetting the resin supplied to the cavity 51b.

  24 and 25, a resin film (film material) 53 is disposed between the lead frame 40 and the lower mold 52. A pressing force from the clamp surface 52 a of the lower mold 52 is applied to the lower surface side (back surface side, mounting surface side) of the lead frame 40 through the resin film 53. For this reason, as shown in FIG. 24, the lower surface 4 b of the lead 4 and the lower surface 2 b of the die pad 2 are easily adhered to the resin film 53. By bringing the resin film 53 into close contact, it is possible to suppress the sealing resin from entering the lower surface 4b of the lead 4 and the lower surface 2b of the die pad 2. That is, the lower surface 4b of the lead 4 and the lower surface 2b of the die pad 2 can be exposed.

  Moreover, in this Embodiment, the sealing body 6 is formed so that the several device area | region 40a may be sealed collectively. In other words, as shown in FIG. 25, in the sealing process, the lead frame 40 is arranged in the molding die 50 so that the plurality of device regions 40a of the lead frame 40 are accommodated in one cavity 51b. A semiconductor package in which the sealing body 6 is formed so as to cover a plurality of device regions 40a arranged in a matrix (array) in this manner is called a MAP (Multi Array Package) type semiconductor device. Moreover, the sealing method which seals the several device area | region 40a collectively is called a block sealing (Block Molding) method. In the MAP type semiconductor device, since the interval between the device regions 40a can be reduced, the effective area of one lead frame 40 is increased. That is, the number of products that can be acquired from one lead frame 40 increases. In this way, the manufacturing process can be made more efficient by increasing the effective area of one lead frame 40. In particular, when several tens of products are acquired from one lead frame 40, the effect of improving the manufacturing efficiency due to the increase in effective area is great.

  Here, in this step, as shown in FIG. 24, the sealing resin wraps around and adheres to the region not in close contact with the molding die 50 or the resin film 53. For this reason, the sealing body 6 is formed in the formed thin part 40hf by the half etching process. In other words, in this step, the thin portion 40hf is sealed with resin. The inventor of the present application studied a method of forming the depression corresponding to the stepped portion 10 shown in FIG. 2 in the lead frame 40 in advance by a half etching process. However, if the sealing process is performed in a state where the lead frame is provided with a depression in advance, the resin is embedded in the depression provided in advance as in the thin-walled portion 40hf shown in FIG. It turns out that it cannot be formed. Therefore, in the present embodiment, as shown in FIG. 14, a half dicing process is performed after the sealing process and before the plating process. Thereby, the resin embedded in the thin portion 40hf is removed, and the lower surface side (rear surface side, mounting surface side) of the thin portion 40hf is exposed.

5. Half dicing process (first cutting process);
Next, as a half dicing step shown in FIG. 14, the resin (sealing body 6 shown in FIG. 24) embedded in the lower surface side (back surface side, mounting surface side) of the thin portion 40hf as shown in FIG. 26 is removed. The tie bar 40tb and the lower surface side (back surface side, mounting surface side) of the tie bar 40tb are exposed. FIG. 26 is an enlarged cross-sectional view showing a state in which the lead frame shown in FIG. 24 is cut and the lower surface side of the tie bar is exposed. FIG. 27 is an enlarged sectional view further enlarging the periphery of the dicing region shown in FIG. FIG. 28 is a plan view showing a state in which the lead frame shown in FIG. 23 is fixed with a dicing tape. FIG. 29 is an enlarged plan view showing a part of the lower surface side of the lead frame shown in FIG. 28 in an enlarged manner.

  In this step, as shown in FIG. 26, cutting is performed using a blade (rotating blade) BD1, and the resin embedded on the lower surface side of the thin portion 40hf is removed. The blade BD1 is an annular (ring-shaped) or disk-shaped cutting jig, and a plurality of abrasive grains are fixed to a cutting portion disposed on the periphery of the circle. And a to-be-processed part can be cut and removed by pressing the cutting process part of braid | blade BD1 to which the several abrasive grain was fixed to a to-be-processed object.

  In this step, the step surface (lower surface, intermediate surface) 4f of the lead 4 described with reference to FIG. 5 is exposed. Therefore, as shown in FIG. 27, the width W1 of the blade BD1 used in this step, that is, the cutting width in this half dicing step is thicker (larger) than the width W2 of the tie bar 40tb. Thereby, the step surface 4f can be exposed in each of the leads 4 connected to both sides of the tie bar 40tb. In other words, in this step, the stepped portion 10 is formed in each of the plurality of leads 4 by forming a groove along the dicing region 40c by cutting with the blade BD1.

  Further, from the viewpoint of reliably removing the resin adhering to the lower surface side of the thin wall portion 40hf, it is preferable to cut and remove a part of the tie bar 40tb and a part of the lead 4 adjacent to the tie bar 40tb. Therefore, the width W1 of the blade BD1 shown in FIG. 27 is preferably thicker (larger) than the width (groove width) W4 of the thin portion 40hf shown in FIG.

  In this step, the plurality of leads 4 are not separated from the tie bars 40tb. In other words, in this step, other portions on the lower surface side (back surface side, mounting surface side) are removed so as to leave a part of the upper surface side of each of the lead 4 and the tie bar 40tb. By connecting the lead 4 to the tie bar 40tb, a metal film can be easily formed by using an electroplating method in a plating process described later.

  Next, the detailed flow of this process is demonstrated. In this step, first, as shown in FIG. 28, the lead frame 40 on which the sealing body 6 (see FIG. 23) is formed is fixed to a frame (ring frame) 56 via a tape (dicing tape) 55. At this time, since cutting is performed from the lower surface side (back surface side, mounting surface side) of the lead frame 40, the upper surface 6a of the sealing body 6 is adhered to the tape 55 as shown in FIG. Fix so that the side (back side, mounting surface side) faces upward.

  Next, the blade BD1 shown in FIG. 26 is rotated along the dicing area 40c of the lead frame 40 while rotating. As a result, as shown in FIG. 29, step portions 10 are formed at the peripheral edge portions of the leads 4 along the dicing region 40c. Here, as shown in FIG. 15, the outer frame 40b of the lead frame 40 is formed with a mark 40m serving as an alignment mark when cutting with the blade BD1 (see FIG. 26). In the example shown in FIG. 15, two marks 40m are provided for each dicing line (dicing region 40c). One of the two marks 40m is provided on the extension line of the dicing line (dicing region 40c), and the other is provided at a position that does not overlap the extension line of the dicing line. When the mark 40m is provided on the extension line of the dicing line, the alignment accuracy is improved, so that the stepped portion 10 shown in FIG. 29 can be formed with high accuracy. However, in the half dicing process, the outer frame 40b of the lead frame 40 is also cut. For this reason, the mark 40m arranged on the extension line of the dicing line is scraped off in this step. Therefore, a mark 40m is provided at a position that does not overlap with an extension line of the dicing line as an alignment mark used in an individualization process described later.

  Moreover, the depth of the groove formed in this step, that is, the depth of the stepped portion 10 shown in FIG. That is, the depth of the stepped portion 10 is preferably as deep as possible from the viewpoint of improving the mounting strength of the semiconductor device 1 (see FIG. 1), or from the viewpoint of easily detecting a problem when the semiconductor device 1 is mounted. Therefore, in this step, it is preferable to perform cutting at a depth of half or more with respect to the entire thickness of the lead 4 (distance from the lower surface 4b to the upper surface 4a). However, it is preferable that the plurality of leads 4 are connected to the tie bars 40tb at least until the plating step described below is completed. Therefore, from the viewpoint of preventing the connecting portion between the lead 4 and the tie bar 40tb from breaking before the plating process is completed, the tie bar 40tb is preferably thicker. Taking these into consideration, the depth of the stepped portion 10 is particularly preferably about half of the total thickness of the lead 4 (distance from the lower surface 4b to the upper surface 4a). For example, when the total thickness of the lead 4 is about 0.2 mm, the depth of the stepped portion 10 is preferably about 0.1 mm.

  In this step, since the blade BD1 travels along the dicing area 40c, the lower surface side (rear surface side, mounting surface side) of a part of the suspension lead TL (exposed portion TL2) as shown in FIG. To expose. In this way, by exposing a part of the suspension lead TL (exposed portion TL2) in the half dicing step, a metal film can be formed on the exposed surface of the suspension lead TL in the plating step described later. As a result, as described with reference to FIG. 11, a part of the suspension lead TL (exposed portion TL2) can be connected to the land 21c of the mounting substrate 20 via the bonding material 24. Mounting strength can be improved. Moreover, according to this Embodiment, the process of forming the level | step-difference part 10 in the lead 4 and the process of exposing a part of suspension lead TL can be performed collectively. Therefore, it is possible to prevent an increase in the manufacturing process due to exposing the suspension leads TL.

  Further, since the lower surface side of the lead frame is cut in the half dicing step, it can be manufactured using a lead frame not provided with the thin portion 40hf shown in FIG. 17 as a modification to the present embodiment. However, when cutting a metal material, if the amount of the metal material to be cut increases, the possibility of generating metal scraps and metal burrs increases. Therefore, from the viewpoint of suppressing the generation amount of metal scraps and metal burrs, it is preferable to provide a thin portion 40hf in advance and reduce the amount of metal material to be cut as shown in FIG.

  Further, when the arrangement interval between the adjacent device regions 40a is wide, as another modified example of the half dicing process, the dicing blade is run twice between each device region 40a, and the tie bar 40tb is sandwiched between the adjacent device regions 40a. A method of forming the stepped portions 10 on the matching leads 4 can be considered. In this case, the resin covering the tie bar 40tb remains between the stepped portions 10.

  However, from the viewpoint of improving the manufacturing efficiency, as shown in the example shown in FIG. 27, the stepped portions 10 are collectively arranged with respect to the adjacent leads 4 with the arrangement interval of the adjacent device regions 40a close to each other with the tie bar 40tb interposed therebetween. Is preferably formed. In other words, in the half dicing step, it is preferable to expose the lower surface of the tie bar 40tb from the sealing body 6. Thereby, the cutting time in a half dicing process can be shortened.

6). Plating process;
Next, as a plating step shown in FIG. 14, as shown in FIG. 30, a metal film SD is formed on the exposed surfaces of the plurality of leads 4 and the die pad 2. FIG. 30 is an enlarged cross-sectional view showing a state in which a metal film is formed on the exposed surfaces of the lead and die pad shown in FIG. 26, and FIG. 31 is an explanatory view showing an outline of the plating process by electrolytic plating.

  First, as shown in FIG. 31, in this step, as shown in FIG. 31, the lead frame 40 which is a workpiece to be plated is placed in a plating tank 60 containing a plating solution 61. At this time, the workpiece is connected to the cathode 62 in the plating tank 60. For example, in the example shown in FIG. 31, the outer frame 40 b of the lead frame 40 is electrically connected to the cathode 62. A metal film SD is formed on the exposed surface of the metal member connected to the outer frame 40b of the lead frame 40 by applying a DC voltage, for example, between the cathode 62 and the anode 63 also disposed in the plating tank 60. (See FIG. 30). That is, in this embodiment, the metal film SD is formed by a so-called electrolytic plating method.

As described above, the metal film SD of the present embodiment is made of so-called lead-free solder that does not substantially contain lead (Pb). For example, only tin (Sn), tin-bismuth (Sn-Bi), Or it is tin-copper-silver (Sn-Cu-Ag). For this reason, the plating solution 61 used in this plating step is an electrolytic plating solution containing a metal salt such as Sn ²⁺ or Bi ³⁺ . In the following description, Sn—Bi alloyed metal plating will be described as an example of lead-free solder plating, but Bi can be replaced with a metal such as Cu or Ag.

In the present embodiment, as described above, the plating process is performed in a state where the plurality of leads 4 are electrically connected to the outer frame 40b via the tie bars 40tb. The die pad 2 is electrically connected to the outer frame 40b via the tie bar 40tb and the suspension lead TL (see FIG. 16). Accordingly, when a voltage is applied between the anode 63 and the cathode 62 shown in FIG. 31 in a state where the lead frame 40 is immersed in the plating solution 61, the current flows between both electrodes (between the anode 63 and the cathode 62). As described above, since the outer frame 40b of the lead frame 40 is electrically connected to the cathode 62, Sn ²⁺ and Bi ³⁺ in the plating solution 61 are ^contained at a predetermined ratio in the lead 4 shown in FIG. A metal film SD is formed by depositing on the exposed surface of the die pad 2.

  Further, as shown in FIG. 14, in the present embodiment, a half dicing process is performed before the plating process, and step portions 10 are formed on the respective leads 4 as shown in FIG. It is exposed from the sealing body 6. For this reason, in the main plating step, the metal film SD can be reliably formed on the exposed surface of the stepped portion 10. Although the film thickness of the metal film SD can be changed according to product specifications, for example, a film of about 10 μm to 20 μm is formed.

  Incidentally, as a method of forming a metal film by a plating method, there is an electroless plating method in addition to an electrolytic plating method. However, the electrolytic plating method is preferable in that the film quality of the metal film SD can be easily controlled by controlling the current during the formation of the metal film. Moreover, the electroplating method is preferable in that the formation time of the metal film SD can be made shorter than the electroless plating method.

7). Individualizing step (second cutting step);
Next, as an individualization step shown in FIG. 14, as shown in FIG. 32, the tie bar 40tb (see FIG. 34) connected to the dicing region 40c is cut, so that the plurality of device regions 40a are separated into individual pieces. To divide. FIG. 32 is an enlarged plan view showing a state where a metal film is formed on the lead frame shown in FIG. FIG. 33 is an enlarged cross-sectional view showing a state in which the lead frame shown in FIG. 30 is fixed to a dicing tape and separated into pieces. FIG. 34 is an enlarged cross-sectional view showing the periphery of the dicing region in FIG. 33 in a further enlarged manner. The overall view of the state in which the lead frame 40 is fixed to the tape 55 is the same as FIG.

  In this step, first, as shown in FIG. 28, the lead frame 40 on which the sealing body 6 (see FIG. 33) is formed is fixed to a frame (ring frame) 56 via a tape (dicing tape) 55. At this time, since cutting is performed from the lower surface side (back surface side, mounting surface side) of the lead frame 40, the upper surface 6a of the sealing body 6 is adhered to the tape 55 as shown in FIG. Fix so that the side (back side, mounting surface side) faces upward.

  Next, the blade (rotating blade) BD2 shown in FIGS. 33 and 34 is rotated along the dicing area 40c of the lead frame 40 while rotating. More specifically, a rotating blade (rotating blade) BD2 is inserted into the groove formed by the half dicing process (first cutting process), and the blade BD2 is caused to travel along the dicing area 40c of the lead frame 40. . As a result, the tie bar 40tb and a part of the sealing body formed immediately above the tie bar 40tb (part overlapping with the tie bar 40tb) are removed (cut), and the adjacent device regions 40a are separated. The blade BD2 is the same as the blade BD1 shown in FIG. 27 except for the cutting width. That is, the blade BD2 is a cutting jig having an annular (ring-shaped) or disk-shaped side surface shape, and a plurality of abrasive grains are fixed to a cutting portion arranged at the periphery of the circle. And a to-be-processed part can be cut and removed by pressing the cutting part of braid | blade BD2 to which the several abrasive grain was fixed to a to-be-processed object.

  Further, as shown in FIG. 34, the width W3 of the blade BD2, that is, the cutting width in the singulation process is larger (larger) than the width W2 of the tie bar 40tb, and the blade BD1 shown in FIG. It is thinner (smaller) than the width W1. In other words, the width W3 is thicker (larger) than the width W2 of the tie bar 40tb, and narrower than the groove width (width W2 shown in FIG. 27) of the groove (stepped portion 10) formed in the half dicing step. small). For example, the width W2 of the tie bar 40tb is 0.16 mm, the width W1 of the blade BD1 is 0.90 mm, and the width W3 of the blade BD2 is 0.30 mm, for example. By cutting the tie bar 40tb using the blade BD2 having the width W3 which is thicker than the width W2 and thinner than the width W1 as described above, the tie bar 40tb is surely removed and the stepped portion 10 is left. Can do.

  When cutting is performed from the lower surface 4b side of the lead 4 in this step, the side surface 4c not exposed to the metal film SD (exposed from the metal film SD) is exposed as shown in FIG. However, according to the present embodiment, since the side surface 4e constituting the step portion 10 is covered with the metal film SD, the mounting strength of the obtained semiconductor device 1 (see FIG. 1) can be improved.

  Further, as described above, the lead frame 40 of the present embodiment is provided with two marks 40m for each dicing line (dicing region 40c) as shown in FIG. For this reason, one of the two marks 40m is scraped off in the half dicing step described above, but in this step, the mark 40m provided at a position not overlapping with the extension line of the dicing line may be used as an alignment mark. it can.

  After this step, necessary inspections and tests such as an appearance inspection and an electrical test are performed, and what has passed is a completed semiconductor device 1 shown in FIGS. Then, the semiconductor device 1 is shipped or mounted on a mounting board (not shown).

<Modification>
Although the invention made by the inventors of the present application has been specifically described above based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, a plurality of leads 4 are arranged along each side of the sealing body 6 that forms a quadrilateral, and the lower surface of the lead 4 is exposed on the lower surface of the sealing body 6. The embodiment applied to this semiconductor device has been described. However, the applicable package form is not limited to QFN. For example, the present invention can be applied to a SON type semiconductor device in which a plurality of leads 4 are arranged along long sides facing each other of a sealing body having a rectangular shape in plan view.

  Further, for example, in the above embodiment, since the QFN type semiconductor device has been taken up and described, the example in which the plurality of leads 4 are provided in each of the plurality of device regions 40a has been described. However, as a modified example, as shown in FIG. 35, the present invention can be applied to a configuration in which one lead 4 is adjacently connected with a tie bar 40tb interposed therebetween. FIG. 35 is an enlarged plan view showing a modification to FIG.

  Further, as a modification of the dicing blade used in the half dicing process described in the above embodiment, a cutting portion having a V-shaped or trapezoidal tip shape can be used. 36 is an enlarged cross-sectional view for explaining the shape of the cutting portion of the dicing blade shown in FIGS. 26 and 27. FIG. 37 and 38 are enlarged cross-sectional views showing modifications to FIG.

  In the said embodiment, as a blade BD1 used at a half dicing process, the case where the cutting process part provided in the periphery has a shape called what is called a straight blade was demonstrated as an example. That is, as shown in FIG. 36, the cutting portion provided on the peripheral edge of the blade BD1 has a tip surface BDt1 that first comes into contact with the cut portion of the lead frame 40 in the above-described half dicing process. Further, the cutting portion of the blade BD1 has a side surface BDs1 orthogonal to the front end surface BDt1, and a side surface BDs2 positioned opposite to the side surface BDs1 and orthogonal to the front end surface BDt1. And a taper surface is not formed between front end surface BDt1 and side surface BDs1, and between front end surface BDt1 and side surface BDs2.

  On the other hand, the blade (dicing blade) BD3 shown in FIG. 37 and the blade (dicing blade) BD4 shown in FIG. Is different. That is, the blade BD3 has a V-shaped cutting portion provided on the periphery. In other words, the blade BD3 does not have the tip surface BDt1 like the blade BD1, and two tapered surfaces (inclined surfaces) BDk intersect at the tip of the blade BD3 to form a pointed pointed shape. The blade BD4 shown in FIG. 38 is different from the blade BD1 in that a tapered surface (inclined surface) BDk is formed between the front end surface BDt1 and the side surface BDs1, and between the front end surface BDt1 and the side surface BDs2. To do. Here, the tapered surface BDk refers to an inclined surface that is positively formed between the tip surface BDt1 and the side surfaces BDs1, BDs2, and between the tip surface BDt1 and the side surfaces BDs1, BDs2 due to wear during cutting. The curved surface formed in is excluded.

  When the half dicing process is performed with a straight blade that does not have a tapered surface BDk (see FIGS. 37 and 38) like the blade BD1, the cutting width can be made constant regardless of the cutting depth. This is more preferable in that the width W1 can be reduced compared to the case of using BD3 and BD4. Further, the cutting accuracy can be improved by reducing the width W1.

  In the above embodiment, as shown in FIG. 4, the so-called I suspension type suspension lead TL is described in which each of the plurality of suspension leads TL extends to the corner portion 6 k without branching in the middle. However, as a modified example, like the semiconductor device 70 shown in FIG. 39, each of the plurality of suspension leads TL branches at the corner 6k of the sealing body 6 toward two sides adjacent to the corner 6k. A so-called Y suspension type suspension lead may be employed. In the case of the I suspension type, for example, as shown in FIG. 29, the four suspension leads TL intersect each other between the device regions 40a arranged in a matrix. For this reason, in the half dicing process and the individualizing process, the blade passes through the intersection of the suspension leads TL twice (X direction and Y direction). For this reason, foreign matter (burrs) may be formed on the cut surface of the suspension lead TL. On the other hand, as shown in FIG. 39, in the case of the Y suspension type, a point where the four suspension leads intersect does not occur. For this reason, in order to suppress the generation | occurrence | production of the foreign material in a half dicing process or an individualization process, it is preferable to employ | adopt Y hanging type | mold which requires the frequency | count of a blade passing once.

  Furthermore, in the above-described embodiment, description is given of electrically connecting the pads (electrodes, bonding pads) PD and the leads (terminals, external terminals) 4 of the semiconductor chip 3 through the wires 5 as conductive members. did. However, as a modification, the pads PD of the semiconductor chip 3 and the leads 4 may be electrically connected via the bump electrodes BM as in the semiconductor device 71 shown in FIGS. 40 and 41. The semiconductor device 71 is mounted by a so-called flip-chip connection method so that the surface 3a on which the pad PD of the semiconductor chip 3 is formed faces the upper surfaces 4a of the leads 4. In the example shown in FIG. 41, since the semiconductor chip 3 is supported by a plurality of leads 4, the die pad 2 is not provided. However, as a further modification, for example, for the purpose of improving heat dissipation characteristics, A metal member (heat spreader) such as the die pad 2 shown in FIG. 5 can also be provided.

  In addition, a part of the contents described in the above embodiment will be described below.

[Appendix 1]
Semiconductor devices
A semiconductor chip;
A die pad on which the semiconductor chip is mounted;
A lead disposed next to the die pad and electrically connected to the semiconductor chip via a conductive member;
A suspension lead coupled to the die pad;
A first surface, a second surface located on the opposite side of the first surface, and the semiconductor chip, the conductive member, the die pad, the lead, so that a part of the die pad and the lead is exposed. And a sealing body for sealing the suspension lead,
Have
A stepped portion is provided on the periphery of the second surface of the sealing body so as to surround the periphery of the second surface,
In the step portion, a part of each of the lead and the suspension lead is exposed.

1, 70, 71, H1 Semiconductor device 2 Die pad (chip mounting portion, tab)
2a Top surface (chip mounting surface)
2b Bottom surface (mounting surface)
3 Semiconductor chip 3a surface (main surface)
3b Back side (main surface)
3c Side 4 Lead (terminal, external terminal)
4a Upper surface (surface, wire bonding surface)
4b Bottom surface (surface, mounting surface)
4c Side surface 4e Side surface 4f Step surface 5 Wire (conductive member)
6 Sealing body (resin body)
6a Upper surface (surface)
6b Bottom surface (surface, back surface, mounting surface)
6c Side surface 6e Side surface 6f Step surface 6k Corner portion 10 Step portion 20 Mounting substrate (motherboard, wiring substrate)
20a Top surface (mounting surface)
21 Land (terminal)
21a Land (Lead connection terminal)
21b Land (terminal for die pad connection)
21c Land (Hanging lead connection terminal)
22 Insulating film (solder resist film)
23, 24 Bonding material 30 Inspection device (Appearance inspection device)
31 Light Irradiation Unit 32 Imaging Unit 33 Control Unit 40 Lead Frame (Base Material)
40a Device area (product formation area)
40b Outer frame 40c Dicing area (dicing line)
40hf Thin part (half-etched part)
40m mark 40tb tie bar 50 mold 51 upper mold (mold)
51a Clamp surface (mold surface, pressing surface, surface)
51b Cavity (recessed part)
52 Lower mold (mold)
52a Clamp surface (mold surface, pressing surface, surface)
53 Resin film (film material)
55 tape (dicing tape)
56 frames (ring frames)
60 Plating tank 61 Plating solution 62 Cathode 63 Anode BD1, BD2, BD3, BD4 Blade,
BDk taper surface (inclined surface)
BDs1 Side surface BDs2 Side surface BDt1 Tip surface DB Die bond material (adhesive)
BM Bump electrode (conductive member)
PD pad (electrode, bonding pad)
SD metal film (exterior plating film, solder film)
TL Hanging lead TL1 Sealing part TL2 Exposed part W1, W2, W3 Width

Claims (7)

A semiconductor device manufacturing method including the following steps:
(A) a first device region having a first lead, a second device region having a second lead and provided adjacent to the first device region, the first device region, and the second device Providing a lead frame including a tie bar provided between the regions and connected to each of the first lead and the second lead;
(B) After the step (a), mounting the first semiconductor chip on the first device region and mounting the second semiconductor chip on the second device region;
(C) After the step (b), the first lead and the first semiconductor chip are electrically connected through a first conductive member, and the second lead and the second semiconductor chip are connected to each other. Electrically connecting via two conductive members;
(D) After the step (c), the first lead, the second lead, the tie bar, the first semiconductor chip, the second lead so that the lower surfaces of the first lead and the second lead are exposed. Forming a sealing body that collectively seals the semiconductor chip, the first conductive member, and the second conductive member;
(E) After the step (d), a part of each of the first lead, the second lead, and the tie bar is removed using a first blade having a first width larger than the width of the tie bar. The step of:
(F) After the step (e), a step of forming a metal film by plating on the exposed surface of the lead frame exposed from the sealing body formed by the step (d);
(G) After the step (f), using a second blade having a second width that is larger than the width of the tie bar and smaller than the first width, the tie bar and the sealing body Removing a part and separating the first device region and the second device region; In claim 1,
In the step (f), a method of manufacturing a semiconductor device, wherein the metal film is formed by an electrolytic plating method. In claim 1,
In the lead frame prepared in the step (a), the thickness of the tie bar is less than the thickness of the first and second leads. In claim 1,
In the step (e), a method of manufacturing a semiconductor device in which a lower surface side of the tie bar is exposed. In claim 1,
The cutting portion provided on the periphery of the first blade is:
In the step (e), the front end surface that first contacts the machined portion of the lead frame, the first side surface orthogonal to the front end surface, and the position opposite to the first side surface and orthogonal to the front end surface Having a second side;
A method of manufacturing a semiconductor device, wherein a tapered surface is not formed between the tip surface and the first side surface and between the tip surface and the second side surface. In claim 1,
The cutting portion provided on the periphery of the first blade is:
In the step (e), the front end surface that first contacts the machined portion of the lead frame, the first side surface orthogonal to the front end surface, and the position opposite to the first side surface and orthogonal to the front end surface Having a second side;
Manufacturing of a semiconductor device in which a tapered surface is formed between the tip surface and the first side surface and between the tip surface and the second side surface so as to face the part to be cut. Method. In claim 1,
The first device region is provided with a first die pad, and a first suspension lead that connects the first die pad and the tie bar,
The second device region is provided with a second die pad and a second suspension lead for connecting the second die pad and the tie bar,
In the step (e), a method of manufacturing a semiconductor device in which part of the first and second suspension leads is exposed.

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