JP2013101285A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make fine a pixel by reducing the number of transistors of the pixel.SOLUTION: A pixel 12A of a digital driving type liquid crystal display device is one pixel disposed at an intersection between a column data line D and a row scan line G, and includes a holding part 21, an output part 24, and a liquid crystal display element 27. The holding part 21 forms a first shift register including a first switching transistor 22 and a first inverter 23. The output part 24 forms a second shift register including a second switching transistor 25 and a second inverter 26. Sub-frame data are sampled by the first switching transistor and held in the first inverter 23 in each pixel 12A in a display part; then, trigger pulses are supplied to all the pixels 12A at the same time via a common signal line TRG, so that the data held in the first inverter 23 are collectively transferred via the output part 24 to a pixel electrode PE.

Description

  The present invention relates to a liquid crystal display device, and more particularly to a digital drive type liquid crystal display device used for a reflective liquid crystal projector device or the like for performing display based on a digital gradation signal.

  In recent years, a liquid crystal on silicon (LCOS) type liquid crystal display device is often used as a central part for projecting an image in a projector device or a projection television. In the display method of the liquid crystal display device such as LCOS, an analog video signal is conventionally input to a semiconductor element such as a CMOS (Complementary Metal Oxide Semiconductor), and the signal is held as it is on the pixel electrode of the liquid crystal display element for each pixel. A method of changing the orientation of the liquid crystal, a method of applying a video signal that has been subjected to pulse width modulation (PWM) by a digital signal to the pixel electrode of the liquid crystal display element, and driving by switching the orientation of the liquid crystal over time. is there. Among them, the pulse width modulation method using a digital signal has a feature of having high resistance to liquid crystal burn-in, and has been used in recent years.

  On the other hand, an analog driving method and a digital driving method are known as driving methods for liquid crystal display elements. In the analog drive type liquid crystal display device, each pixel samples a gradation signal, which is an analog signal of a level corresponding to the gradation supplied via the liquid crystal display element and the column data line, at the time of pixel selection. A switching unit; a storage capacitor for holding a gradation signal supplied via the first switching unit for a certain period; and a gradation signal that is switched on at a predetermined readout timing and held in the storage capacitor The thing of the structure provided with the 2nd switching means applied to these pixel electrodes is known (for example, refer patent document 1, 2).

  Also, in a digital drive type liquid crystal display device, each frame of a video signal to be displayed is composed of a plurality of subframes having a display period shorter than one frame period, and the plurality of subframes are to be displayed. Depending on the tone, the pixel is driven by a combination of subframes corresponding to the gradation to be displayed by selectively turning on and off with 1-bit subframe data which is a digital signal.

  In this digital drive type liquid crystal display device, each pixel is selected from a liquid crystal display element and two 1-bit subframe data of opposite logical values supplied via a pair of column data lines. First and second switching means for sampling at times, and two inverters whose output terminals are connected to the other input terminal, and are supplied to each other through the first and second switching means. Holding means for holding the subframe data for a certain period of time, and third switching means for applying the subframe data that is switched on at a predetermined readout timing and held in the holding means to the pixel electrode of the liquid crystal display element. The thing of the structure which exists is known (for example, refer patent document 3). The third switching means is composed of two transfer gates, the output terminals of which are connected in common to the pixel electrode, one gate input terminal is connected in common to one terminal of the holding means, and the other The gate input terminal is commonly connected to the other terminal of the holding means. One of the two transfer gates is supplied with a first voltage to the input terminal, and the other transfer gate is supplied with a second voltage to the input terminal. One of the two transfer gates is turned on to apply the first voltage or the second voltage from the output terminal to the pixel electrode.

JP 2001-272657 A JP 2001-077554 A Special Table 2002-515606

  However, the digital drive method has a feature that electrical adjustment is possible compared with the analog drive method, but the liquid crystal display device of the digital drive method has a problem in pixel miniaturization. For example, in the digital drive type liquid crystal display device described in Patent Document 3, each of the two inverters is composed of a CMOS inverter composed of two transistors, and each of the first and second switching means is composed of one transistor. In addition, since the third switching means is composed of four transistors composed of two transfer gates, a total of ten transistors are used, and the number of transistors constituting the pixel is large, which prevents miniaturization. It has become.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a digital drive type liquid crystal display device capable of miniaturizing pixels by reducing the number of transistors in the pixels.

In order to achieve the above object, in the liquid crystal display device of the present invention, pixels are arranged at each of a plurality of intersections where a plurality of column data lines and a plurality of row scanning lines intersect, It is composed of a plurality of subframes having a display period shorter than one frame period, and the plurality of subframes are selectively turned on / off by 1-bit digital data according to the gradation to be displayed. A display unit that displays the image by driving a pixel with a combination of subframes corresponding to the gradation to display the image, and a horizontal scanning unit that outputs digital data to each of a plurality of column data lines in units of one horizontal scanning period And a vertical scanning means for outputting a row selection signal for sequentially selecting a plurality of row scanning lines one by one in units of one horizontal scanning period, and a common connection to all of a plurality of pixels constituting the display unit Trigger pulse generating means for outputting a trigger pulse at a timing after the completion of writing digital data to all of the plurality of pixels in the display section via the common signal line, and each of the plurality of pixels in the display section ,
A liquid crystal display element having a structure in which a liquid crystal layer is sealed between a pixel electrode and a common electrode that are spaced apart from each other and digital data supplied via a column data line are sampled at the time of pixel selection by a row selection signal A second shift that transfers digital data held in the holding unit and applies it to the pixel electrode when the trigger pulse is supplied via the common signal line and the holding unit configured by the first shift register to hold And an output unit composed of a register.

  In order to achieve the above object, in the liquid crystal display device of the present invention, the first shift register includes a first switching transistor having a drain connected to a column data line and a gate connected to a row scanning line. And the first inverter having an input terminal connected to the source of the first switching transistor. The second shift register has a drain connected to the output terminal of the first inverter and a gate connected to the common signal line. And a second inverter having an input terminal connected to a source of the second switching transistor, and an output terminal of the second inverter is connected to the pixel electrode.

  In order to achieve the above object, according to the liquid crystal display device of the present invention, the first shift register has an input terminal connected to the column data line and is supplied with row selection signals having opposite logical values. A first transfer gate having a control terminal connected to one row scanning line, and a first inverter having an input terminal connected to the output terminal of the first transfer gate. An input terminal is connected to the output terminal of the inverter, a second transfer gate having a control terminal connected to two common signal lines to which trigger pulses of opposite logic values are supplied, and an input to the output terminal of the second transfer gate The second inverter is connected to the terminal, and the output terminal of the second inverter is connected to the pixel electrode.

  According to the present invention, it is possible to realize pixel miniaturization in a digital drive type liquid crystal display device.

1 is a schematic overall configuration diagram of an embodiment of a liquid crystal display device of the present invention. 1 is an equivalent circuit diagram of a first embodiment of a pixel in a liquid crystal display device of the present invention. FIG. 3 is a timing chart (part 1) for explaining an operation in FIG. 2; FIG. FIG. 3 is a timing chart (part 2) for explaining operations in FIG. 2; FIG. It is an equivalent circuit diagram of the second embodiment of the pixel in the liquid crystal display device of the present invention.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic overall configuration diagram of an embodiment of a liquid crystal display device according to the present invention. In the figure, the liquid crystal display device 10 according to the present embodiment has an intersection of j column data lines D1 to Dj extending in the vertical direction and k row scanning lines G1 to Gk extending in the horizontal direction. 1-bit sub-frame data for each of the display unit 11 including a plurality of pixels 12 arranged in a matrix in the unit and one row of pixels 12 in units of one horizontal scanning period (1H) is applied to the column data lines D1 to Dj. For the horizontal scanning circuit 13 to be output and the row scanning lines G1 to Gk, for example, one row selection signal is set in units of 1H in the direction of the row scanning line Gk at the lowest position on the screen from the row scanning line G1 at the highest position on the screen. And a trigger pulse generator (not shown) for simultaneously supplying trigger pulses to all of the plurality of pixels 12 constituting the display unit 11 at a predetermined timing via the common signal line TRG. It is roughly composed of . The liquid crystal display device 10 of this embodiment is a digital drive type liquid crystal display device characterized by the configuration of the pixels 12.

  Next, embodiments of the pixels constituting the main part of the present invention will be described.

  FIG. 2 shows an equivalent circuit diagram of the first embodiment of the main pixel of the liquid crystal display device according to the present invention. In the figure, the pixel 12A according to the first embodiment includes an arbitrary column data line D among the column data lines D1 to Dj and an arbitrary row among the row scanning lines G1 to Gk. One pixel arranged at the intersection with the scanning line G is composed of a holding unit 21, an output unit 24, and a liquid crystal display element 27.

  The holding unit 21 includes a first switching transistor 22 having a drain connected to the column data line D and a gate connected to the row scanning line, and a first inverter 23 having an input terminal connected to the source of the first switching transistor 22. And constitutes a first shift register as a whole. The output unit 24 has a drain connected to the output terminal of the first inverter 23, a gate connected to the common signal line TRG, and a second switching transistor 25 whose input terminal is connected to the source of the second switching transistor 25. 2 inverters 26 and constitutes a second shift register as a whole. The liquid crystal display element 27 includes a pixel electrode PE connected to the output terminal of the second inverter 26, a common electrode CE arranged to be opposed to the pixel electrode PE, and a space between the pixel electrode PE and the common electrode CE. And a liquid crystal layer LCM filled and sealed. Here, as an example, both the first switching transistor 22 and the second switching transistor 25 are N-channel MOS transistors (hereinafter referred to as NMOS transistors).

  Next, writing and reading operations of the pixel 12A of this embodiment will be described with reference to timing charts in FIGS.

  First, the write operation will be described. FIG. 3A schematically shows writing and reading with respect to all the pixels 12 constituting the display portion 11, and hatched portions in FIG. Now, as shown in FIG. 3B and FIG. 4A from the horizontal scanning circuit 13 to the column data line D connected to the pixel 12A, the 1-bit sub-frame data of the sub-frame B0 starts from the time t1. Assume that the period up to time t4 is output. At this time, the 1-bit subframe data of each subframe B0 is also output to the column data lines connected to the other pixels 12 in the same row as the pixel 12A. Note that the 1-bit subframe data illustrated in FIG. 4A has a logical value “1” for the sake of convenience of explanation. However, when the logical value is “0”, the 1-bit subframe data is set to the low level during the period from time t1 to t4.

  Subsequently, during the period from time t2 immediately after time t1 to time t3 immediately before time t4, as shown in FIGS. 3C and 4B, the vertical scanning circuit 14 supplies the row scanning line. A row selection signal at a high level (VDD) is input to G pixels 12 in one row including the pixels 12A through G, and these pixels 12 are selected. In this pixel selection state, the first switching transistor 22 in the pixel 12A is turned on, and the 1-bit subframe shown in FIGS. 3B and 4A supplied through the column data line D at this time is shown in FIG. Data is sampled and supplied to the first inverter 23.

  The first inverter 23 outputs data having an inverse logical value to the input subframe data. Here, as shown in FIG. 4C, since the trigger pulse is not inputted to the common signal line TRG from the time t1 to a read start time t5 described later, the common signal line TRG is at the low level. The second switching transistor 25 is turned off. For this reason, even when the row selection signal becomes low level at time t3 and the j pixels 12 in one row including the pixel 12A are in the non-selected state as shown in FIG. The subframe data sampled by the first transistor 22 at the time of selection is held.

  In the same manner, the subframe data corresponding to the subframe B0 is written to all the pixels 12 constituting the display unit 11 (these are the same as the configuration in FIG. 2), Subframe data is held in the first inverter 23.

  Next, the reading operation will be described. The period from time t5 to time t6 shown in FIG. 4C after the completion of the writing of the subframe data to all the pixels 12, and as shown schematically in FIG. 3D, via the common signal line TRG. A high-level trigger pulse is supplied, and the second switching transistors 25 of all the pixels 12 including the pixel 12A are turned on. As a result, the input subframe data held in the first inverter 23 in the pixel 12 </ b> A is read out through the second switching transistor 25 and applied to the second inverter 26.

  The second inverter 26 inverts the input sub-frame data having the opposite logical value, holds the sub-frame data having the same logical value as the sub-frame data of the column data line D, and the pixel electrode PE of the liquid crystal display element 27. Apply to.

  The potential of the pixel electrode PE of the liquid crystal display element 27 is positive as shown in FIG. 3E when the subframe data of the subframe B0 supplied via the column data line D has a logical value “1”. When the voltage is VDD and the logical value is “0”, it is 0 V as shown in FIG.

  On the other hand, in the liquid crystal display element 27, the common electrode voltage Vcom that is inverted every subframe period is applied to the common electrode CE. As shown in FIG. 3G, the common electrode voltage Vcom is a low-level voltage c in the display period of the subframe B0 (the period of the horizontal line portion schematically shown as b0 in FIG. 3A). This voltage c is a negative voltage of less than 0 V, and is −Vtt, for example, when the threshold voltage of the liquid crystal layer LCM is Vtt (> 0).

  The liquid crystal display element 27 performs display with gradation according to the absolute value of the potential difference between the potential of the pixel electrode PE applied to the liquid crystal layer LCM and the common electrode voltage Vcom of the common electrode CE. Here, the voltage applied to the liquid crystal layer LCM of the liquid crystal display element 27 is the positive large voltage V1b0 (= VDD) shown in FIG. 3H when the subframe data of the subframe B0 is the logical value “1”. −c), and when the logical value is “0”, the positive small voltage V0b0 (= 0−c) shown in FIG. Therefore, in the subframe B0, the pixel 12A whose subframe data has a logical value “1” displays white, and the pixel 12A whose subframe data has a logical value “0” displays black.

  When writing and reading (display) of the subframe B0 are completed, writing and reading (display) of the subframe nB0 are sequentially performed in the subsequent one subframe period, as schematically shown in FIG. . Writing of the subframe nB0 is started immediately after the trigger pulse of the common signal line TRG shown in FIGS. 3D and 4C changes from the high level to the low level. The subframe nB0 is written within the display time b0 of the previously written subframe B0.

  The subframe data written to each pixel of the subframe nB0 is inverted data having a reverse logical value from the subframe data written to the same pixel of the immediately preceding subframe B0. That is, when the subframe data of the subframe B0 written to the pixel 12A has a logical value “1”, the subframe data of the subframe nB0 written to the same pixel 12A has a logical value “0”. Further, when the subframe data of the subframe B0 written to the pixel 12A has a logical value “0”, the subframe data of the subframe nB0 written to the same pixel 12A has a logical value “1”.

  The writing operation of the subframe nB0 of the pixel 12A is the same as the writing operation of the subframe B0, and the corresponding subframe data of the subframe nB0 is written to all the pixels 12A constituting the display unit 11, and each pixel The subframe data of the subframe nB0 is held in the first inverter 23 in 12A. The hatched portion at nB0 in FIG. 3A indicates writing.

  Next, the reading operation of the pixel 12A will be described. After the writing of subframe data to all the pixels 12 is completed, a high-level trigger pulse is supplied through the common signal line TRG as schematically shown in FIG. 3D, and all the pixels 12 including the pixels 12A are supplied. The second switching transistor 25 is turned on. As a result, the subframe data having the opposite logical value to the subframe data of the subframe nB0 held in the first inverter 23 in the pixel 12A is read through the second switching transistor 25 and applied to the second inverter 26. The

  The second inverter 26 inverts the input sub-frame data of the opposite logical value, holds the sub-frame data having the same logical value as the sub-frame data of the sub-frame nB 0 of the column data line D, and the liquid crystal display element 27. To the pixel electrode PE.

  The potential of the pixel electrode PE of the liquid crystal display element 27 is 0 V as shown in FIG. 3E when the subframe data of the subframe nB0 supplied via the column data line D has a logical value “0”. Yes, when the logical value is “1”, it is a positive voltage VDD as shown in FIG.

  On the other hand, in the liquid crystal display element 27, the common electrode voltage Vcom that is inverted every subframe period is applied to the common electrode CE. As shown in FIG. 3G, the common electrode voltage Vcom is a high-level voltage d during the display period of the subframe nB0 (the period of the horizontal line portion schematically shown as nb0 in FIG. 3A). This voltage d is a predetermined voltage higher than VDD, and is, for example, the saturation voltage Vsat (> 0) of the liquid crystal layer LCM. The saturation voltage Vsat is a voltage that is higher than the threshold voltage Vtt by a specified voltage (for example, VDD). Note that the display period nb0 of the subframe nB0 is equal to the display period b0 of B0 of the subframe.

  The voltage applied to the liquid crystal layer LCM of the liquid crystal display element 27 is such that, in the pixel 12A to which the subframe data of the subframe B0 having the logical value “1” is applied, the subframe data of the next subframe nB0 has the logical value “0”. Therefore, the voltage V1nb0 (= −d) shown in FIG. 3H, which is a difference voltage between the applied voltage 0 V of the pixel electrode PE and the common electrode voltage Vcom (= d), which is larger in the negative direction than −VDD. Become. The voltage applied to the liquid crystal layer LCM of the liquid crystal display element 27 is the logical value of the subframe data of the next subframe nB0 in the pixel 12A to which the subframe data of the subframe B0 having the logical value “0” is applied. Since it is “1”, the negative voltage V0nb0 (= VDD−d) shown in FIG. 3I, which is a difference voltage between the applied voltage VDD of the pixel electrode PE and the common electrode voltage Vcom (= d). .

  When c = −Vtt and d = Vsat (= VDD + Vtt), the liquid crystal layer applied voltage V1b0 (= VDD−c = VDD + Vtt) and the subframe of the subframe B0 of the same pixel 12A shown in FIG. Since the voltage application direction to the liquid crystal layer LCM is opposite to the liquid crystal layer application voltage V1nb0 (= 0−d = − (VDD + Vtt)) of nB0, the absolute value is the same (VDD + Vtt). White display is also performed in subframes. On the other hand, the liquid crystal layer application voltage V0b0 (= 0−c = + Vtt) of the subframe B0 and the liquid crystal layer application voltage V0nb0 (= VDD−d = −Vtt) of the subframe nB0 of the same pixel 12A shown in FIG. Since the voltage application directions to the liquid crystal layer LCM are opposite to each other but have the same absolute value Vtt, the pixel 12A performs black display in both subframes. Further, since the voltage application direction with respect to the liquid crystal layer LCM is inverted between the subframe B0 and the subframe nB0, the liquid crystal display element 27 is AC driven.

  Subsequently, as schematically shown in FIG. 3A, the pixel 12A is subframes B1, nB1, B2, nB2, B3, nB3. The writing operation for each pixel row in the subframe as shown in I) and the simultaneous reading operation for all the pixels are performed to display each subframe. Here, the subframes nB1, nB2, and nB3 are subframes that transmit inverted data of the subframe data of the subframes B1, B2, and B3. In this way, by transmitting subframe data having opposite logical values to each other in two adjacent subframe units and the pixel 12A performs a write operation and a read operation, each pixel 12A is a pixel in two adjacent subframes. Since the same gradation display is performed every time and the liquid crystal display element 27 can be driven with an alternating current, the burn-in of the liquid crystal display element 27 can be prevented.

Further, the write times of the subframes B0, nB0, B1, nB1, B2, nB2, B3, and nB3 are the same. On the other hand, regarding the display time, if the display times of subframes B0, nB0, B1, nB1, B2, nB2, B3, nB3 are TB0, TnB0, TB1, TnB1, TB2, TnB2, TB3, TnB3, respectively. For example
(TB0 + TnB0) :( TB1 + TnB1) :( TB2 + TnB2) :( TB3 + TnB3) = 1: 2: 4: 8
By changing each value of each subframe data of B0 to B3 (nB0 to nB3), it is possible to express gradation in the 4-bit PWM method (that is, within one frame period). A desired gradation display is performed by a combination of eight subframes).

  As described above, according to the pixel 12A of the present embodiment, the inverters 23 and 26 can be constituted by CMOS inverters each composed of one PMOS transistor and one NMOS transistor whose drains and gates are connected to each other. Therefore, it can be composed of a total of six transistors, and the number of transistors can be reduced as compared with the number of transistors of ten pixels in a conventional digital drive type liquid crystal display device. For this reason, according to the pixel 12A of the present embodiment, the pixel pitch can be reduced as compared with the conventional case, so that the pixel can be miniaturized and the high definition by the fine pixel can be dealt with.

  Further, according to the pixel 12A of the present embodiment, a stable operation can be expected because the storage element is configured by the shift register. In addition, since the data output from the second inverter 26 is applied to the pixel electrode PE of the liquid crystal display element 27, the liquid crystal display element 27 can be driven with low impedance, so that no storage capacitor is required.

  Next, a second embodiment of the pixels constituting the main part of the present invention will be described.

  FIG. 5 shows an equivalent circuit diagram of a second embodiment of the main pixel of the liquid crystal display device according to the present invention. In the figure, the same components as those in FIG. In FIG. 5, the pixel 12B according to the second embodiment includes any one column data line D among the column data lines D1 to Dj and any one row among the row scanning lines G1 to Gk. One pixel arranged at the intersection with the scanning line G is composed of a holding unit 31, an output unit 34, and a liquid crystal display element 27.

  The holding unit 31 includes a first transfer gate 32 constituting a first switching means, and a first inverter 33 having an input terminal connected to the output terminal of the first transfer gate 32, and as a whole a first shift register. Is configured. The output unit 34 includes a second transfer gate 35 that constitutes a second switching means, and a second inverter 36 having an input terminal connected to the output terminal of the second transfer gate 35, and the second shift register as a whole. Is configured. The output terminal of the second inverter 36 is connected to the pixel electrode PE of the liquid crystal display element 27.

  The first transfer gate 32 includes one NMOS transistor NTr1 and one PMOS transistor PTr1 whose drains and sources are connected to each other, and each drain of the transistors NTr1 and PTr1 which are input terminals of the transfer gate 32. Is connected to the column data line D, and each source which is an output terminal of the transfer gate 32 is connected to an input terminal of the first inverter 33. Further, the gate of the NMOS transistor NTr1 and the gate of the PMOS transistor PTr1 which are control terminals of the transfer gate 32 are connected to the first row scanning line G and the second row scanning line NG, respectively. The first row scanning line G and the second row scanning line NG are connected to a plurality of pixel units in each row, and row selection signals having opposite logical values are supplied from a vertical scanning circuit (not shown).

  The second transfer gate 35 is composed of one NMOS transistor NTr2 and one PMOS transistor PTr2 whose drains and sources are connected to each other, and each drain of the transistors NTr2 and PTr2 which are input terminals of the transfer gate 35. Is connected to the output terminal of the first inverter 33, and each source which is the output terminal of the transfer gate 35 is connected to the input terminal of the second inverter 36. In addition, the gate of the NMOS transistor NTr2 and the gate of the PMOS transistor PTr2 which are control terminals of the transfer gate 35 are connected to the first common signal line TRG and the second common signal line NTR, respectively. The first common signal line TRG and the second common signal line NTR are connected in common to all the pixels 12 constituting the display unit 11, and trigger pulses having opposite logic values are supplied from a trigger pulse generator (not shown).

  Next, the operation of the pixel 12B of this embodiment will be described. The writing operation of the pixel 12B in the present embodiment is the same as the writing operation of the pixel 12A, except that pixel selection is performed by row selection signals having opposite logic values supplied via the row scanning lines G and NG. That is, the sub-frame data supplied to the column data line d is a high-level first row selection signal supplied through the row scanning line G and a low-level second data supplied through the row scanning line NG. Are sampled by the first transfer gate 32 and applied to the first inverter 33 and held there.

  In the reading operation of the pixel 12B, the second transfer gate 35 is turned on by trigger pulses having opposite logic values supplied via the first common signal line TRG and the second common signal line NTR after the writing of all the pixels is completed. Other than this, the reading operation of the pixel 12A is the same. In other words, the pixel 12B receives the high-level normal rotation trigger pulse and the second normal pulse supplied through the first common signal line TRG immediately after the subframe data writing to all the pixels including the pixel 12B in the display unit 11 is completed. The second transfer gate 35 is controlled to be turned on by a low-level inversion trigger pulse supplied via the common signal line NTR, and the inverted subframe data output from the first inverter 33 is supplied to the second inverter 36. . The second inverter 36 inverts the input subframe data, holds the subframe data having the same logical value as the subframe data of the column data line D, and applies it to the pixel electrode PE of the liquid crystal display element 27. Make a display.

  The pixel 12B according to the present embodiment has a transfer gate configuration including two transistors compared to the pixel 12A configured with one NMOS transistor as a switching unit, and therefore includes a pixel compared to the pixel 12A. Although the number of transistors slightly increases from 6 to 8, the number of transistors can be reduced as compared to the conventional 10 transistors. Further, according to the pixel 12B of the present embodiment, since the switching means is a transfer gate composed of two transistors, the voltages (subframe data) input to the first inverter 33 and the second inverter 36 through the switching means. Can be increased up to VDD, and the effect of stable operation is obtained.

  Note that the present invention is not limited to the above embodiment, and for example, the first switching transistor 22 and the second switching transistor 25 may be configured by PMOS transistors. However, in this case, it is necessary to invert the data of the column data line D, the row selection signal of the row scanning line G, and the polarity of the trigger pulse as compared with the case of the embodiment.

  Further, the number of subframes within one frame period and the time relationship between subframes are not limited to those of the embodiment described with reference to FIG. 3, but can be changed as appropriate according to the system. .

DESCRIPTION OF SYMBOLS 10 Liquid crystal display device 11 Display part 12,12A, 12B Pixel 13 Horizontal scanning circuit 14 Vertical scanning circuit 21,31 Holding part 22 1st switching transistor 23,33 1st inverter 24,34 Output part 25 2nd switching transistor 26,36 Second inverter 27 Liquid crystal display element 32 First transfer gate 35 Second transfer gate D1 to Dj, D column data lines G1 to GK, G, NG Row scanning lines TRG, NTR common signal lines

Claims (3)

A plurality of sub-frames in which pixels are arranged at each of a plurality of intersections where a plurality of column data lines and a plurality of row scanning lines intersect, and each frame has a display period shorter than one frame period A combination of subframes corresponding to the gradations for displaying one frame image by selectively turning on and off the 1-bit digital data according to the gradations for displaying the plurality of subframes. A display unit that performs display by driving the pixels;
Horizontal scanning means for outputting the digital data to each of the plurality of column data lines in units of one horizontal scanning period;
Vertical scanning means for outputting a row selection signal for sequentially selecting the plurality of row scanning lines one by one in units of one horizontal scanning period;
A trigger pulse is generated at a timing after completion of writing the digital data to all of the plurality of pixels in the display section via a common signal line commonly connected to all of the plurality of pixels constituting the display section. Trigger pulse generating means for outputting, each of the plurality of pixels in the display unit,
A liquid crystal display element having a structure in which a liquid crystal layer is sealed between a pixel electrode and a common electrode which are arranged to be spaced apart from each other;
A holding unit configured by a first shift register that samples and holds the digital data supplied via the column data line at the time of pixel selection by the row selection signal;
An output unit configured by a second shift register that transfers the digital data held in the holding unit and applies the digital data to the pixel electrode when the trigger pulse is supplied via the common signal line. A liquid crystal display device characterized by the above. The first shift register includes a first switching transistor having a drain connected to the column data line and a gate connected to the row scanning line, and a first switching transistor having an input terminal connected to a source of the first switching transistor. Consisting of an inverter,
The second shift register has a drain connected to the output terminal of the first inverter, a second switching transistor having a gate connected to the common signal line, and an input terminal connected to the source of the second switching transistor. The second inverter,
The liquid crystal display device according to claim 1, wherein an output terminal of the second inverter is connected to the pixel electrode. The first shift register includes a first transfer gate having an input terminal connected to the column data line and a control terminal connected to two row scanning lines to which row selection signals having opposite logical values are supplied. A first inverter having an input terminal connected to the output terminal of the first transfer gate,
The second shift register has a second transfer circuit in which an input terminal is connected to an output terminal of the first inverter, and a control terminal is connected to two common signal lines to which trigger pulses having opposite logic values are supplied. A gate and a second inverter having an input terminal connected to the output terminal of the second transfer gate,
The liquid crystal display device according to claim 1, wherein an output terminal of the second inverter is connected to the pixel electrode.

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