JP2014021302A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device employing a digital drive system which can supply a voltage between a ground potential and a power source voltage to pixels as a pixel drive voltage.SOLUTION: A holding part 21 selectively fetches and holds digital data output from a horizontal scan circuit through a column data line. An output part 22 selectively fetches and holds the digital data held in the holding part 21, and selectively outputs a high drive voltage V1 or a low drive voltage V0 which is arbitrarily set between a ground potential and a power source voltage according to a logical value of the digital data held. A pixel part 23 drives a liquid crystal LC according to a potential difference between the high drive voltage V1 or the low drive voltage V0 selectively output from the output part 22 and a voltage supplied to a common electrode CE.

Description

  The present invention relates to a digital drive type liquid crystal display device that displays an image based on a digital gradation signal.

  In a digital drive type liquid crystal display device, each frame of a video signal to be displayed is composed of a plurality of sub-frames having a display period shorter than one frame period. The plurality of subframes are selectively turned on and off by 1-bit subframe data which is a digital signal according to the gradation to be displayed. As a result, the pixels are driven by a combination of subframes corresponding to the gradation for displaying an image of one frame.

  As this type of digital drive type liquid crystal display device, for example, those described in the following documents are known (see Patent Document 1). In the device described in this document, a ground potential and a power supply voltage are supplied to both ends of a liquid crystal cell constituting a pixel, and the liquid crystal cell is driven. That is, the driving voltage for driving the liquid crystal cell is fixed to the ground potential and the power supply voltage.

JP-A-56-53487

  This causes a problem that a drive voltage other than the ground potential and the power supply voltage cannot be supplied to the pixel.

  An object of the present invention is to provide a digital drive type liquid crystal display device capable of supplying a voltage between a ground potential and a power supply voltage to a pixel as a pixel drive voltage.

  In the present invention, a pixel circuit (16) is arranged at each of a plurality of intersections where a plurality of column data lines (D) and a plurality of row scanning lines (G) intersect, and each frame is divided into one frame period. It is composed of a plurality of sub-frames having a short display period, and the pixel circuit (16) is driven by 1-bit digital data in accordance with the gradation to display each sub-frame, thereby displaying an image of one frame. A display unit (11) for performing display in a combination of subframes corresponding to the gradation to be obtained, a horizontal scanning circuit (12) for sequentially outputting digital data to a plurality of column data lines in units of one horizontal scanning period, A vertical scanning circuit (13) for outputting a row selection signal for sequentially selecting a plurality of row scanning lines one by one in units of one horizontal scanning period, and a common signal line (TRG) commonly connected to the plurality of pixel circuits. G And a trigger pulse generation circuit (14) for outputting a gas pulse, and the pixel circuit outputs from the horizontal scanning circuit via the column data line in response to a row selection signal output from the vertical scanning circuit via the row scanning line. And selectively holding the digital data held in the holding unit according to the trigger pulse output from the trigger pulse generation circuit via the common signal line. An output unit that captures, holds, and selectively outputs a high drive voltage (V1) or a low drive voltage (V0) arbitrarily set between the ground potential and the power supply voltage according to the logical value of the held digital data (22) and a pixel that drives the liquid crystal (LC) according to the potential difference between the high-level drive voltage or low-level drive voltage selectively output from the output unit and the voltage supplied to the common electrode (CE) To provide a liquid crystal display device, characterized in that it comprises (23) and.

  According to the present invention, in the liquid crystal display device, the holding unit includes a first transistor (24) having a gate terminal connected to the row scanning line, a drain terminal connected to the column data line, and an input terminal being the source of the first transistor. A first inverter (25) connected to the terminal, and the output section includes a second transistor (26) having a gate terminal connected to the common signal line and a drain terminal connected to the output terminal of the first inverter; A second inverter (27) having an input terminal connected to the source terminal of the second transistor, an output terminal connected to the pixel electrode, a high drive voltage supplied as a high power supply voltage, and a low drive voltage supplied as a low power supply voltage It is preferable to comprise.

  According to the liquid crystal display device of the present invention, a voltage between the ground potential and the power supply voltage can be supplied to the pixel as a pixel driving voltage.

It is a figure which shows the whole structure of the liquid crystal display device which concerns on 1st Embodiment of this invention. It is a figure which shows one circuit structure of a pixel circuit. 3 is a timing chart for explaining an example of a driving method of the liquid crystal display device according to the first embodiment of the present invention. It is a timing chart which shows the detailed timing of FIG.3 (b), (c), (d), (e).

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

(First embodiment)
With reference to FIG. 1, the structure of the liquid crystal display device which concerns on 1st Embodiment of this invention is demonstrated. In FIG. 1, the liquid crystal display device includes a display unit 11, a horizontal scanning circuit 12, a vertical scanning circuit 13, a trigger pulse generation circuit 14, and a pixel drive voltage supply circuit 15.

  The display unit 11 includes a plurality (j × k) of pixel circuits 16 arranged in a matrix at each intersection of the j column data lines D1 to Dj and the k row scanning lines G1 to Gk. Each frame of the video signal to be displayed on the display unit 11 includes a plurality of subframes having a display period that is shorter than one frame period. Each pixel circuit 16 displays an image with a combination of subframe data, which is a digital signal corresponding to the gradation at which an image of one frame is to be displayed.

  Column data lines D1 to Dj are connected to the horizontal scanning circuit 12. The horizontal scanning circuit 12 sequentially outputs 1-bit subframe data in units of subframes for each of the pixel circuits 16 to the column data lines D1 to Dj in units of one horizontal scanning period.

  Row scanning lines G <b> 1 to Gk are connected to the vertical scanning circuit 13. The vertical scanning circuit 13 sequentially supplies row selection signals to the row scanning lines G1 to Gk, for example, from the row scanning lines G1 to Gk in units of one horizontal scanning period.

  The trigger pulse generation circuit 14 supplies a trigger pulse for reading (display) simultaneously to all the pixel circuits 16 in the display unit 11 through a common signal line TRG (* not shown in FIG. 1).

  The pixel drive voltage supply circuit 15 supplies the pixel circuit 16 with a high drive voltage (V1) and a low drive voltage (V0) arbitrarily set between the ground voltage and the power supply voltage. The high level drive voltage (V1) and the low level drive voltage (V0) are arbitrarily set within the following ranges, assuming that the high level power supply voltage used in the device is VDD and the low level power supply voltage is the ground potential (0V). The

(Equation 1)
VDD ≧ V1> V0 ≧ 0
The configuration of the pixel circuit 16 shown in FIG. 2 will be described as a representative of a plurality of pixel circuits 16 arranged in a matrix. The pixel circuit 16 shown in FIG. 2 intersects any one column data line D among the column data lines D1 to Dj and any one row scanning line G among the row scanning lines G1 to Gk. One pixel circuit arranged in the unit. The pixel circuit 16 includes a holding unit 21, an output unit 22, and a pixel unit 23.

  The holding unit 21 selectively captures and holds the subframe data supplied via the column data line D according to the row selection signal supplied via the row scanning line G, and holds the held subframe data. Invert and output. The holding unit 21 includes a gate circuit 24 and a first inverter 25. The gate circuit 24 includes the first transistor 24. The first transistor 24 has a gate terminal connected to the row scanning line G and a drain terminal connected to the column data line D. The input terminal of the first inverter 25 is connected to the source terminal of the first transistor.

  The output unit 22 selectively captures and holds the subframe data that is inverted and output from the holding unit 21 in response to the trigger pulse supplied via the common signal line TRG. The output unit 22 selectively outputs a high drive voltage (V1) or a low drive voltage (V0) arbitrarily set between the ground potential and the power supply voltage according to the logical value of the held subframe data. .

  The output unit 22 includes a gate circuit 26 and a second inverter 27. The gate circuit 26 includes a second transistor 26. The second transistor 26 has a gate terminal connected to the common signal line TRG and a drain terminal connected to the output terminal of the first inverter 25.

  The second inverter 27 selectively selects the high drive voltage (V1) or the low drive voltage (V0) supplied from the pixel drive voltage supply circuit 15 according to the subframe data held and inverted by the holding unit 21. Output to. The second inverter 27 is composed of a CMOS inverter. The CMOS inverter includes a p-channel MOS transistor 28 and an n-channel MOS transistor 29.

  The gate terminal of the MOS transistor 28 is connected to the source terminal of the second transistor 26. The MOS transistor 28 has a source terminal connected to the pixel drive voltage supply circuit 15, and a high level drive potential (V1) is supplied to the source terminal. The MOS transistor 28 is supplied with a power supply voltage (VDD) as a substrate potential.

  The gate terminal of the MOS transistor 29 is connected to the source terminal of the second transistor 26. In the MOS transistor 29, the source terminal is connected to the pixel drive voltage supply circuit 15, and the low potential drive potential (V0) is supplied to the source terminal. The MOS transistor 29 is given a ground potential as a substrate potential.

  As the first and second transistors 24 and 26 constituting the gate circuits 24 and 26, n-channel MOS transistors can be used as an example. As the first inverter 25, a CMOS inverter composed of a p-channel MOS transistor and an n-channel MOS transistor in which the drain terminals and the gate terminals are connected to each other can be used.

  The pixel unit 23 performs gradation display according to the subframe data output from the output unit 22 for each subframe. The pixel unit 23 includes a pixel electrode PE connected to the output terminal of the second inverter 27, a common electrode CE that is spaced from and opposed to the pixel electrode PE, and a liquid crystal LC. The liquid crystal LC is filled and sealed between the pixel electrode PE and the common electrode CE.

  Next, an example of a driving method including writing and reading (display) of the pixel circuit 16 of the liquid crystal display device according to the first embodiment will be described with reference to timing charts of FIGS. B0, B1, B2, and B3 attached to the upper part of FIG. 3A indicate subframes, respectively, and one subframe is constituted by four subframes B0, B1, B2, and B3. Each subframe B0, B1, B2, B3 is divided into a first half subframe (bB0, bB1, bB2, bB3) and a second half subframe (nB0, nB1, nB2, nB3). The periods of the first half and the second half are the same.

  FIG. 3A schematically shows writing and reading (display) with respect to all the pixel circuits 16 in the display unit 11, where the hatched portion indicates writing and the horizontal line portion below the hatched portion reads (display). Indicates. TbB0, TbB1, TbB2, and TbB3 attached to the horizontal lines in FIG. 3A indicate display periods of the subframes bB0, bB1, bB2, and bB3, respectively. TnB0, TnB1, TnB2, and TnB3 attached to the horizontal lines in FIG. 3A indicate display periods of the subframes nB0, nB1, nB2, and nB3, respectively.

  Writing in the subframe B0 will be described. The subframe B0 is written in the first half subframe bB0, and then in the second half subframe nB0. In the first half subframe bB0, for example, when the high level drive voltage (V1) is output to the pixel electrode PE of the pixel unit 23, the timing shown in FIG. That is, at time t1 to t4 in FIG. 4, a high level (VDD) is supplied as 1-bit subframe data from the horizontal scanning circuit 12 to the column data line D. At this time, the same subframe data is also supplied to the column data lines connected to the other pixel circuits 16 in the same row as the pixel circuit 16.

  In this state, as shown in FIG. 3C and FIG. 4B, during the period from time t2 immediately after time t1 to time t3 immediately before time t4, the vertical scanning circuit 13 passes through the row scanning line G. A high level (VDD) row selection signal is output. This row selection signal is supplied to j pixel circuits 16 in one row including the pixel circuits 16, and these pixel circuits 16 are selected.

  As a result, the first transistor 24 in the pixel circuit 16 is turned on. The high-level subframe data supplied from the column data line D is supplied to the input terminal of the first inverter 25 through the first transistor 24. The first inverter 25 inverts and outputs the high-level subframe data. The high-level subframe data is held in the holding unit 21 when the row selection signal shifts from the high level to the low level at time t3 and the first transistor 24 is turned off.

  By performing the writing operation on all the pixel circuits 16 constituting the display unit 11, the subframe data corresponding to the subframe bB0 is written and held in the pixel circuit 16.

  When a low driving voltage (V0) is output to the pixel electrode PE of the pixel portion 23, the horizontal scanning circuit 12 applies a low level (ground potential) to the column data line D at times t1 to t4 in FIG. Is supplied. Thereby, the low-level subframe data is held in the holding unit 21.

  Next, the process proceeds to a read (display) operation. As shown in FIGS. 3D and 4C, a high-level trigger pulse is output via the common signal line TRG at time t5 after the writing to all the pixel circuits 16 is completed. This trigger pulse is supplied to the second transistor 26 of the pixel circuit 16, and the second transistor 26 is turned on. Thereby, the subframe data held in the holding unit 21 is inverted by the first inverter 25 and taken into the output unit 22.

  The subframe data captured by the output unit 22 is input to the second inverter 27 via the second transistor 26. The second inverter 27 selectively outputs a high drive voltage (V1) or a low drive voltage (V0) according to the level (logical value) of the input subframe data.

  That is, the second inverter 27 outputs the high level drive voltage (V1) when the low level (ground potential) subframe data is input. As a result, the voltage applied to the pixel electrode PE shifts from the low drive voltage (V0) to the high drive voltage (V1) as shown in FIG. On the other hand, when the high level (VDD) subframe data is input, the second inverter 27 outputs a low driving voltage (V0). The low driving voltage (V 0) output from the second inverter 27 is applied to the pixel electrode PE of the pixel unit 23.

  The subframe data output to the output unit 22 is held in the output unit 22 when the trigger pulse shifts to a low level at time t6 and the second transistor 26 is turned off. When the subframe data supplied via the column data line D is at a high level, the voltage of the pixel electrode PE of the pixel portion 23 becomes a high drive voltage (V1) as shown in FIG. On the other hand, when the subframe data supplied via the column data line D is at a low level, the voltage of the pixel electrode PE becomes a low driving voltage (V0) as shown in FIG.

  On the other hand, a common electrode voltage VC that is inverted every subframe period is applied to the common electrode CE of the pixel unit 23. As shown in FIG. 3G, the common electrode voltage VC is a low-level voltage e during the display period of the subframe bB0 (the period of the horizontal line portion indicated by TbB0 in FIG. 3A). This voltage e is a negative voltage less than 0V, and its absolute value is smaller than V0. The voltage e is −Vtt, for example, when the threshold voltage of the liquid crystal LC is Vtt (> 0).

  The pixel unit 23 performs display with gradation according to the absolute value of the potential difference between the voltage of the pixel electrode PE applied to the liquid crystal LC and the common electrode voltage VC of the common electrode CE. Here, the voltage applied to the liquid crystal LC becomes a large positive voltage V1b0 (= V1-e) shown in FIG. 3H when the subframe data is at the high level. On the other hand, when the subframe data is at a low level, the voltage applied to the liquid crystal LC is a small positive voltage V0b0 (= V0−e) shown in FIG. Accordingly, in the subframe bB0, the pixel circuit 16 whose subframe data is at a high level displays white, and the pixel circuit 16 whose subframe data is at a low level displays black.

  Thus, when the writing and reading (display) of the subframe bB0 are completed, the writing and reading (display) of the subframe nB0 are sequentially performed as schematically shown in FIG. The sub-frame nB0 is written after the trigger pulse of the common signal line TRG shown in FIGS. 3D and 4C shifts from the high level to the low level. The subframe nB0 is written within the display time TbB0 of the subframe bB0 written earlier.

  The subframe data written in each pixel circuit 16 in the subframe nB0 is data at a level opposite to that of the subframe data written in the same pixel circuit 16 in the immediately preceding subframe bB0. That is, when the subframe data of the subframe bB0 written to the pixel circuit 16 is at the high level, the subframe data of the subframe nB0 written to the same pixel circuit 16 is at the low level.

  On the other hand, when the subframe data of the subframe bB0 written to the pixel circuit 16 is at the low level, the subframe data of the subframe nB0 written to the same pixel circuit 16 is at the high level.

  The writing operation in the subframe nB0 of the pixel circuit 16 is the same as the writing operation in the subframe bB0. In the writing operation, the subframe data corresponding to the subframe nBO is written to all the pixel circuits 16 constituting the display unit 11. The hatched portion of the subframe nB0 in FIG. 3A indicates writing.

  Next, the process proceeds to a read (display) operation. As shown in FIGS. 3D and 4C, a high-level trigger pulse is output via the common signal line TRG at time t5 after the writing to all the pixel circuits 16 is completed. This trigger pulse is supplied to the second transistor 26 of the pixel circuit 16, and the second transistor 26 is turned on. Thereby, the subframe data held in the holding unit 21 is inverted by the first inverter 25 and taken into the output unit 22.

  The subframe data captured by the output unit 22 is input to the second inverter 27 via the second transistor 26. The second inverter 27 selectively outputs a high level drive voltage (V1) or a low level drive voltage (V0) according to the level of the input subframe data. That is, the second inverter 27 outputs the high level drive voltage (V1) when the low level (ground potential) subframe data is input. As a result, the voltage applied to the pixel electrode PE shifts from the low drive voltage (V0) to the high drive voltage (V1) as shown in FIG.

  On the other hand, when the high level (VDD) subframe data is input, the second inverter 27 outputs a low driving voltage (V0). The low driving voltage (V 0) output from the second inverter 27 is applied to the pixel electrode PE of the pixel unit 23.

  The subframe data output to the output unit 22 is held in the output unit 22 when the trigger pulse shifts to a low level at time t6 and the second transistor 26 is turned off.

  When the subframe data supplied via the column data line D is at a low level, the voltage of the pixel electrode PE of the pixel portion 23 becomes a low drive voltage (V0) as shown in FIG. On the other hand, when the subframe data supplied via the column data line D is at a high level, the voltage of the pixel electrode PE becomes a high drive voltage (V1) as shown in FIG.

  On the other hand, a common electrode voltage VC that is inverted every subframe period is applied to the common electrode CE of the pixel unit 23. As shown in FIG. 3G, the common electrode voltage VC is a high-level voltage f during the display period of the subframe nB0 (the period of the horizontal line portion indicated by TnB0 in FIG. 3A). This voltage f is a predetermined voltage higher than V1, for example, the saturation voltage Vsat (> 0) of the liquid crystal LC. The saturation voltage Vsat is a voltage that is higher than the threshold voltage Vtt by a specified voltage (for example, V1).

  The voltage applied to the liquid crystal LC of the pixel portion 23 becomes a large negative voltage V1nb0 (= V0−f) shown in FIG. 3H when low-level subframe data is written. On the other hand, the voltage applied to the liquid crystal LC is a small negative voltage V0nb0 (= V1-f) shown in FIG. 3I when high-level subframe data is written. Thereby, in the subframe nB0, the pixel circuit 16 whose subframe data is at a high level displays black, and the pixel circuit 16 whose subframe data is at a low level displays white.

  In the pixel circuit 16 in which high-level subframe data is written in the subframe bB0, low-level subframe data is written in the subframe nB0. In the subframe nB0, the polarity of the common electrode voltage VC is inverted with respect to the subframe bB0. As a result, the potential difference applied to the liquid crystal LC increases in any case, and white is displayed in any display period TbB0, TnB0 of the subframe B0.

  On the other hand, in the pixel circuit 16 in which the low-level subframe data is written in the subframe bB0, the high-level subframe data is written in the subframe nB0. In the subframe nB0, the polarity of the common electrode voltage VC is inverted with respect to the subframe bB0. As a result, the potential difference applied to the liquid crystal LC is reduced in any case, and black is displayed in any of the display periods TbB0 and TnB0 of the subframe B0.

  Further, the polarity of the voltage applied to the liquid crystal LC is inverted between the subframe bB0 and the subframe nB0 as shown in FIG. 3 (h) and FIG. 3 (i). Thereby, in the sub-frame B0, the pixel unit 23 is AC-driven, and the burn-in of the pixel unit 23 can be suppressed.

  When the writing operation and the reading operation of the subframe B0 are completed, the writing operation and the reading (display) are subsequently performed in the order of the subframes B1, B2, B3,... Shown in FIG. ) Operation is performed. .. Are written within the display periods TnB0, TnB1, TnB2,... Of the previous subframes B0, B1, B2,. As a result, an image of one frame is displayed.

  The subframes B0, B1, B2, and B3 have the same write time. On the other hand, the display periods (TbB0 + TnB0), (TbB1 + TnB1), (TbB2 + TnB2), and (TbB3 + TnB3) for each of the subframes B0, B1, B2, and B3 are different. For example, (TbB0 + TnB0) :( TbB1 + TnB1) :( TbB2 + TnB2) :( TbB3 + TnB3) = 1: 2: 4: 8. As a result, by changing the value of the subframe data of each of the subframes B0, B1, B2, and B3, gradation expression by a 4-bit PWM method becomes possible. That is, the liquid crystal display device can perform a desired gradation display by a combination of four subframes B0, B1, B2, and B3 within one frame period.

  As described above, according to the first embodiment, the high level drive voltage and the low level drive voltage that are arbitrarily set between the ground potential (0 V) and the power supply voltage (VDD) used by the apparatus are set. It can be supplied to the pixel circuit 16. As a result, it is possible to supply the pixel electrode PE with a higher driving voltage and a lower driving voltage different from the ground potential and the power supply voltage (VDD). As a result, it is possible to supply the liquid crystal LC with an optimum driving voltage for light-emitting display.

  The holding unit 21 can be realized with a small and simple configuration of the first transistor and the first inverter 25 constituting the gate circuit 24.

  The output unit 22 can be realized with a small and simple configuration of the second transistor and the second inverter 27 constituting the gate circuit 26.

  In the first embodiment, the gate circuits 24 and 26 can be configured by p-channel MOS transistors instead of n-channel MOS transistors. In this case, the row selection signal and the trigger pulse have the opposite polarity to that when an n-channel MOS transistor is used. Alternatively, the gate circuits 24 and 26 may be configured by transfer gates in which a p-channel MOS transistor and an n-channel MOS transistor transistor are connected in parallel. In this case, the higher voltage of the subframe data taken into the holding unit 21 and the output unit 22 can be the power supply voltage (VDD). Thereby, the stability of the operation can be improved.

  Further, the high drive voltage (V1) and the low drive voltage (V0) supplied to the pixel circuit 16 may be supplied from the outside of the liquid crystal display device instead of being supplied from the pixel drive voltage supply circuit 15. Good.

  The liquid crystal display device of the first embodiment can be applied to, for example, a projection display device that displays a color image with a three-plate type. In this case, the projection display device includes a liquid crystal display device for R (red), a liquid crystal display device for G (green), and a liquid crystal display device for B (blue). The projection display device performs color display by optically combining images displayed on a liquid crystal display device corresponding to each color.

  As described above, when the liquid crystal display device of the first embodiment is applied to a projection display device, the pixel drive voltage supply circuit 15 of the liquid crystal display device corresponding to each color has a higher drive voltage of a different voltage. Output low drive voltage.

  In other words, the high-level driving voltage (V1R) and the low-level driving voltage (V0R) are supplied to the pixel circuit 16 of the R liquid crystal display device. A high drive voltage (V1G) and a low drive voltage (V0G) are supplied to the pixel circuit 16 of the G liquid crystal display device. A high drive voltage (V1B) and a low drive voltage (V0B) are supplied to the pixel circuit 16 of the B liquid crystal display device.

  For each of the high-level driving voltage and the low-level driving voltage, values suitable for driving the liquid crystal having the respective emission wavelengths are selected. In general, higher drive voltages are required in the order of RGB. Therefore, the magnitude relationship between the high-level drive voltages is, for example, V1R> V1G> V1B, and the magnitude relationship between the low-level drive voltages is, for example, V0R <V0G <V0B.

  As a result, an optimum driving voltage corresponding to the wavelength of each luminescent color can be supplied to the liquid crystal LC of each pixel circuit 16 of the liquid crystal display device for R, G, and B. As a result, the dynamic range of color display can be improved as compared with the conventional three-plate color projection display device that uniformly supplies the ground potential and the power supply voltage (VDD).

DESCRIPTION OF SYMBOLS 11 ... Display part 12 ... Horizontal scanning circuit 13 ... Vertical scanning circuit 14 ... Trigger pulse generation circuit 15 ... Pixel drive voltage supply circuit 16 ... Pixel circuit 21 ... Holding part 22 ... Output part 23 ... Pixel part 24, 26 ... Gate circuit 24 ... 1st transistor 25 ... 1st inverter 26 ... 2nd transistor 27 ... 2nd inverter 28, 29 ... MOS transistor B0, B1, B2, B3 ... Sub-frame CE ... Common electrode D ... Column data line G ... Row scanning line LC ... Liquid crystal PE ... Pixel electrode TRG ... Common signal line

Claims (2)

A pixel circuit is arranged at each of a plurality of intersections where a plurality of column data lines and a plurality of row scanning lines intersect, and each frame is composed of a plurality of subframes having a display period shorter than one frame period. The pixel circuit is driven by 1-bit digital data in accordance with the gradation to be displayed for each subframe, and display is performed with a combination of subframes in accordance with the gradation for displaying an image of one frame. A display unit;
A horizontal scanning circuit that sequentially outputs the digital data to the plurality of column data lines in units of one horizontal scanning period;
A vertical scanning circuit for outputting a row selection signal for sequentially selecting the plurality of row scanning lines one by one in units of one horizontal scanning period;
A trigger pulse generating circuit that outputs a trigger pulse to a common signal line commonly connected to the plurality of pixel circuits;
The pixel circuit includes:
A holding unit that selectively captures and holds digital data output from the horizontal scanning circuit via the column data line in response to a row selection signal output from the vertical scanning circuit via the row scanning line;
In accordance with a trigger pulse output from the trigger pulse generation circuit via the common signal line, the digital data held in the holding unit is selectively captured and held, and according to the logical value of the held digital data, An output unit that selectively outputs a high-level drive voltage or a low-level drive voltage arbitrarily set between a ground potential and a power supply voltage;
A liquid crystal display device comprising: a pixel portion that drives liquid crystal in accordance with a potential difference between a high drive voltage or low drive voltage selectively output from the output portion and a voltage supplied to a common electrode. The holding unit includes a first transistor having a gate terminal connected to the row scanning line, a drain terminal connected to the column data line, and a first inverter having an input terminal connected to the source terminal of the first transistor; With
The output unit has a gate terminal connected to the common signal line, a drain terminal connected to the output terminal of the first inverter, an input terminal connected to the source terminal of the second transistor, and an output. The terminal according to claim 1, further comprising: a second inverter connected to the pixel electrode, to which the high-level driving voltage is supplied as a high-level power supply voltage, and to which the low-level driving voltage is supplied as a low-level power supply voltage. Liquid crystal display device.

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