KR102509878B1 - Method for time division driving and device implementing thereof - Google Patents

Abstract

The present invention relates to a time-division driving method and an apparatus implementing the same. According to an embodiment of the present invention, sub-pixels of gate lines of a first group emit light in response to a corresponding gray level during a frame period, and A time-division driving method and a device implementing the same are included so that the sub-pixels of the gate lines emit light corresponding to a representative value of a corresponding gray level.

Description

Time division driving method and device implementing the same {METHOD FOR TIME DIVISION DRIVING AND DEVICE IMPLEMENTING THEREOF}

The present invention relates to a time division driving method and an apparatus implementing the same.

A display device (or display device) is a device that visually displays data, such as a liquid crystal display, an electrophoretic display, an organic light emitting display, and an inorganic EL display. , (Electro Luminescent Display), Field Emission Display, Surface-conduction Electron-emitter Display, Plasma Display, and Cathode Ray, display), etc.

A liquid crystal display device (LCD) is an electronic device that converts various electrical information generated from various devices into visual information by using a change in liquid crystal transmittance according to an applied voltage and transmits it. The liquid crystal display has the advantages of mass production possibility, ease of driving means, realization of high image quality, and realization of a large-area screen, and is widely used as an alternative means that can overcome the disadvantages of the conventionally used CRT (Cathode Ray Tube). am.

Meanwhile, in an organic light emitting display device, a light emitting layer is formed between two different electrodes, and when electrons generated from one electrode and holes generated from the other electrode are injected into the light emitting layer, the injected electrons and holes are combined to form axcitons. A display device that displays an image by emitting light while the generated exciton falls from an excited state to a ground state, and can realize low-power driving, thin structure, and excellent image quality .

The aforementioned display devices may apply a time division driving method in which frames displaying one image are divided and displayed. When the time division driving method is applied, an image is output on a portion of a display panel including a light emitting area corresponding to image data in a display device. However, when an image is output in the time division method, there is a portion where black data (black image) is output, which may cause a loss of overall luminance of the screen.

Therefore, there is a need for a driving method for outputting an image in a time division manner while reducing luminance loss and a display device implementing the driving method.

The present invention proposes a method of increasing the luminance of a display device in interlaced digital driving.

The present invention proposes a method of reducing power consumption applied to a display device in interlaced digital driving.

The present invention proposes a method in which sub-pixels of a gate line corresponding to a rest period in interlaced digital driving are maintained in an on state for a predetermined frame period.

The present invention proposes a method of increasing image quality by reducing a frame period and a scan time in interlaced digital driving.

A display device according to an embodiment of the present invention provides a first group of gate lines for applying grayscale data signals to sub-pixels within a frame period in interlaced digital driving and a data signal corresponding to a representative value of grayscale data. and a timing controller controlling gate lines of the second group applied to each sub-pixel.

The timing controller according to an embodiment of the present invention includes a subframe converting unit that converts one frame period into K subframes each including an addressing period and a light emitting period, and a data signal of gray level within the frame period to each subpixel. and an interlace controller for controlling a first group of gate lines to be applied and a second group of gate lines to apply data signals corresponding to representative values of grayscale data to sub-pixels, respectively.

A time division driving method according to an embodiment of the present invention includes applying a data signal corresponding to each of K subframes to a first group of subpixels connected to a first group of gate lines within a frame period; and applying a data signal corresponding to each of the L subframes smaller than K to a second group of subpixels connected to a second group of gate lines during a frame period.

When the present invention is applied, overall luminance can be increased by allowing sub-pixels of gate lines not to emit light at all in a specific frame in the interlace method to emit light corresponding to a representative value of data.

When the present invention is applied, black data is not output to the gate lines corresponding to the idle phase in interlaced digital driving, and representative values of gray levels such as MSB maintaining constant luminance are output to reduce power consumption applied to the display device. can make it

The effects of the present invention are not limited to the above-mentioned effects, and those skilled in the art can easily derive various effects of the present invention from the configuration of the present invention.

1 is a diagram showing a display device to which an exemplary embodiment of the present invention is applied.
2 is a diagram showing an interlace driving method.
3 is a diagram showing a subframe driving method.
FIG. 4 is a diagram showing an interlace digital driving method combining the interlace method of FIG. 2 and the digital driving method of FIG. 3 of the present invention.
5 is a diagram showing a configuration for applying MSB data during a frame period instead of black data according to an embodiment of the present invention.
6 is a timing diagram showing signals applied to each gate line in Frame_Odd according to an embodiment of the present invention.
7 is a diagram showing a configuration for applying MSB data during a subframe interval instead of black data according to another embodiment of the present invention.
8 is a diagram showing an example of excluding the output of black data according to another embodiment of the present invention.
9 is a diagram showing light emission levels of each sub-pixel of a display panel according to an exemplary embodiment of the present invention.
10 is a diagram showing light emission levels of each sub-pixel of a display panel according to another exemplary embodiment of the present invention.
11 is a diagram showing light emission levels of each sub-pixel of a display panel according to another exemplary embodiment of the present invention.
12 is a diagram showing the configuration of the timing controller 140 according to an embodiment of the present invention.
13 is a diagram showing a process of time division driving of a display device according to an embodiment of the present invention.
14 is a diagram showing a configuration for applying MSB data during a subframe interval instead of black data according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings so that those skilled in the art can easily carry out the present invention. This invention may be embodied in many different forms and is not limited to the embodiments set forth herein.

In order to clearly describe the present invention, parts irrelevant to the description are omitted, and the same reference numerals are assigned to the same or similar components throughout the specification. In addition, some embodiments of the present invention are described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

Hereinafter, the display device will be described focusing on an organic light emitting display device, but the present invention is not limited thereto, and can be applied to various display devices such as a liquid crystal display device in addition to an organic light emitting display device.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the corresponding component is not limited by the term. When an element is described as being “connected,” “coupled to,” or “connected” to another element, that element is or may be directly connected to that other element, but intervenes between each element. It will be understood that may be "interposed", or each component may be "connected", "coupled" or "connected" through other components.

In addition, in implementing the present invention, components may be subdivided for convenience of explanation, but these components may be implemented in one device or module, or one component may be implemented in a plurality of devices or modules. It may be implemented by dividing into .

1 is a diagram showing a display device to which an exemplary embodiment of the present invention is applied. A display device 100 to which the embodiments are applied includes a display panel 110 in which gate lines GL1 to GLn and data lines DL1 to DLm are crossed, and a display panel 110 disposed on the display panel 110. The gate driver 120 for driving the gate lines, the data driver 130 for driving the data lines arranged on the display panel 110, and the driving timing of the gate driver 120 and the data driver 130 are controlled. It includes a timing controller (Timing Controller, 140) and the like.

In the display panel 110 , gate lines GL1 to GLn and data lines DL1 to DLm intersect to define each sub-pixel P. The sub-pixel is for displaying one color and can display any one color among red (R), green (G), blue (B), and selectively white (W). The aforementioned colors may be replaced according to embodiments.

The data driver 130 may be implemented with a plurality of source drive integrated circuits (ICs). The data driver 130 receives digital video data RGB from the timing controller 140 . The data driver 130 generates a data voltage by converting the digital video data RGB into a gamma compensation voltage in response to a source timing control signal from the timing controller 140, and displays the data voltage in synchronization with the gate signal. It is supplied to the data lines DL of the panel 110 . The data driver 130 may be connected to the data lines DL of the display panel 110 through a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The gate driver 120 drives the gate lines GL1 to GLn by sequentially supplying scan signals to the gate lines GL1 to GLn. GL1 to GLn) are sequentially supplied with scan signals.

The timing controller 140 may be configured on a source printed circuit board (PCB), and a gate drive integrated circuit (hereinafter referred to as 'gate drive IC') is connected to a display panel using a Tape Automated Bonding (TAB) method. It may be configured on a display panel in a COG (Chip On Glass) method or electrically connected to the display panel in a COF (Chip On Film) method.

The timing controller 140 receives digital video data (RGB) from an external host system through an interface such as a Low Voltage Differential Signaling (LVDS) interface, a Transition Minimized Differential Signaling (TMDS) interface, or a Mobile Industrial Processor Interface (MIPI). . The timing controller 140 transmits digital video data (RGB) input from the host system to the data driver 130.

The timing controller 140 receives timing signals such as video data (RGB), a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a main clock signal (MCLK), and a data enable signal (DE) from the outside, Based on this timing signal, the gate control signal (GCS) is applied to the gate driver 120, and the data control signal (DCS) and the above-described image data (RGB) are applied to the data driver 130 as an image for sub-pixels to display. Data (R'G'B') is applied. A plurality of integrated circuits (source drive ICs) constituting the data driver 130 are controlled to apply signals to data lines within a predetermined area.

Although not shown in FIG. 1 , the display device 100 further includes a power supply unit, which supplies voltage or current by applying power to the data driver 130 , the gate driver 120 , and the display panel 110 .

When the interlace driving method is applied to the display panel 110 of FIG. 1 , a time division method in which a specific gate line is driven rather than all gate lines may be applied during one frame period. For example, divided into an odd-numbered gate line and an even-numbered gate line, sub-pixels connected to the odd-numbered gate line output an image during the first frame period, and sub-pixels connected to the even-numbered gate line output an image during the second frame period. Can be configured to print. Of course, the time-division method can be applied by dividing the gate lines in various ways, such as 3 groups or 4 groups, in addition to odd/even numbers. Hereinafter, a method of outputting an image for each frame section of odd-numbered gate lines and even-numbered gate lines among all gate lines according to an embodiment of the present invention will be described. However, the present invention is not limited thereto, and gate lines may be grouped in various ways so that only some of the gate lines output an image during one frame period.

2 is a diagram showing an interlace driving method. There are an odd frame 210 that outputs images from odd-numbered gate lines and an even frame 220 that outputs images from even-numbered gate lines. video is output. The interlace driving method as shown in FIG. 2 is a method of sequentially driving odd-numbered lines/even-numbered lines without driving all gate lines in one frame. This driving method can reduce the driving time by half, so it is suitable for digital driving that requires a lot of driving time (1H Scan Time). However, since black data is applied to gate lines that are not driven, and half of the gate lines do not emit light during one frame period, luminance loss may occur.

Hereinafter, in the present invention, while dividing a frame into subframes, a method of increasing luminance in an interlace method using subframe information will be described. In addition, although an odd frame outputs an image on an odd-numbered gate line and an even frame outputs an image on an even-numbered gate line, conversely, an odd frame does not output an image on an odd-numbered gate line and outputs an image on an even-numbered gate line. A frame outputting an image on an even-numbered gate line may be indicated, and an even frame may indicate a frame outputting an image on an odd-numbered gate line without outputting an image on an even-numbered gate line. This may vary depending on how to group gate lines that output frames and images.

A digital driving method using a subframe may be divided into an address display separation (ADS) method and an address while display (AWS) method. The AWD method has high time efficiency because an addressing time and an emission time partially overlap. Hereinafter, the AWD will be mainly described among the subframe methods, but the present invention is not limited thereto and can be applied to various digital driving methods.

When n subframes are arranged corresponding to n bits, each subframe may correspond to a bit at a specific position.

3 is a diagram showing a subframe driving method.

310 of FIG. 3 shows a case where a 6-bit data signal is configured and 6 subframes are applied, MSB to LSB of the data signal are allocated to the first subframe to the sixth subframe.

The display device 100 may set an emission time in each subframe, which may apply a weight for each subframe. For example, in a 6-bit data signal, the subframe corresponding to the most significant bit (MSB) is the first subframe (SF1), the next bit is the second subframe (SF2), and so on. The bit (Least Significant Bit, LSB) can be configured to be the 6th subframe (SF6). A light emitting period of each subframe may have a different weight depending on the location of a corresponding bit. For example, if the gradation value is 20 in decimal, if it is converted into a 6-bit binary number, it becomes “010100” and controls to emit light at the second subframe SF2 and the fourth subframe SF4.

320 of FIG. 3 shows a case in which a 6-bit data signal is configured and 6 subframes are applied, and LSB to MSB of the data signal are allocated to the first subframe to the sixth subframe.

The display device 100 may set an emission time in each subframe, which may apply a weight for each subframe. For example, in a 6-bit data signal, the subframe corresponding to the least significant bit (LSB) is the first subframe (SF1), the next bit is the second subframe (SF2), and so on. The bit (Most Significant Bit, MSB) can be configured to be the 6th subframe (SF6). A light emitting period of each subframe may have a different weight depending on the location of a corresponding bit. For example, if the gradation value is 20 in decimal, if it is a 6-bit binary number, it becomes “010100” and controls to emit light at the third subframe SF3 and the fifth subframe SF5.

A driving method using such a subframe is referred to as a digital driving method. In this case, the luminance of the organic light emitting diode in each subframe is the same, but the gray level can be adjusted due to the difference in the length of the light emitting section.

FIG. 4 is a diagram showing an interlace digital driving method combining the interlace method of FIG. 2 and the digital driving method of FIG. 3 of the present invention. For convenience of description, an embodiment in which four subframes constitute one frame will be mainly described. It was reviewed in FIG. 3 that one subframe includes an addressing section and an emission section. In the interlace driving method of FIG. 4 , the first frame (Frame_Odd) outputs an image on odd-numbered gate lines and does not output an image on even-numbered gate lines. In the second frame (Frame_Even), images are output from even-numbered gate lines, and images are not output from odd-numbered gate lines. However, as shown in FIG. 4, the non-driving parts do not emit light like 410 and 420, so overall luminance is insufficient, and EVDD or SVDD must be further applied to compensate for this. This reduces the overall power consumption reduction effect, and many of the advantages of digital driving may be offset.

Accordingly, in the present specification, a method of calculating and applying representative data instead of black data to a line that is not driven is proposed to solve the above-mentioned problem of luminance reduction. As an embodiment of the invention, as an embodiment, MSB data is applied as representative data. The MSB corresponds to the most important part of the entire gray level and is a bit value representing the corresponding gray level. Accordingly, when the MSB is reflected instead of representing the entire gray level, a detailed color outline can be expressed rather than outputting black data. In addition, since the luminance can be secured by increasing the luminance of the entire panel, it is not necessary to compensate the luminance, or the EVDD or SVDD can be reduced by reducing the luminance compensation.

Hereinafter, a time division driving method and an apparatus implementing the time division driving method will be described in more detail. According to an embodiment of the present invention, during a frame period, the sub-pixels of the gate lines of the first group emit light corresponding to the corresponding gray level, and the sub-pixels of the gate lines of the second group emit light corresponding to the representative value of the corresponding gray level. It includes a time division driving method and an apparatus implementing the same.

5 is a diagram showing a configuration for applying MSB data during a frame period instead of black data according to an embodiment of the present invention. Grayscale is represented by a total of 4 bits, and accordingly, a total of 4 subframes constitute one frame.

In the first frame (Frame_Odd), an image is output on odd-numbered gate lines, and MSB is reflected in data of a corresponding sub-pixel on even-numbered gate lines to emit light for the entire frame period (see 520). Conversely, in the second frame (Frame_Even), an image is output on even-numbered gate lines, and MSB is reflected in data of a corresponding sub-pixel on odd-numbered gate lines to emit light for the entire frame period (see 510).

6 is a timing diagram showing signals applied to each gate line in Frame_Odd according to an embodiment of the present invention.

As in 610, one gate line includes an addressing period (Addressing Time) and an emission period (Emission Time).

In Frame_Odd, a total of 4 subframes operate. In the first subframe period, the MSB of each data of the subpixels connected to GL1 is output. In response to whether the MSB is 1 or 0 in the addressing section in GL1, the light emitting diode emits light or does not emit light. During the first subframe period, subpixels of GL1 emit light according to MSB values.

Next, GL2 outputs the MSB of each data of the sub-pixels connected to GL2 during the addressing period. In response to whether the MSB is 1 or 0 in the addressing section in GL2, the light emitting diode emits light or does not emit light. During the entire frame period, sub-pixels of GL1 emit light according to MSB values. Unlike GL1, GL2 is a line that does not emit light at all in the previous interlaced method, but in the embodiment of FIG. 5, it is controlled to emit light for one frame period corresponding to the MSB during one addressing period.

Next, like GL1, GL3 outputs the MSB of data of each sub-pixel during the first sub-frame period. Like GL2, in GL4, sub-pixels emit light according to the MSB of data during the entire frame period.

5 and 6 show that in the case of using the conventional interlace method, data signals are applied to half of the gate lines during one frame period, unlike the method in which data signals are applied to only half of the gate lines during one frame period to emit light, A value corresponding to a representative value among data of a corresponding sub-pixel, such as MSB among data signals, is applied to the gate line of the other half to increase overall luminance and reduce power consumption. That is, in the other half of the gate line, each subpixel can be continuously turned on or off according to the MSB during the frame period. In this case, once addressing is performed, separate addressing is not required as shown in FIG. The method provides an effect of sufficiently saving addressing time.

5 and 6 show an embodiment in which odd-numbered gate lines perform digital driving for each sub-frame period in an odd frame in the interlaced digital driving method, and even-numbered gate lines perform digital driving corresponding to the MSB of each sub-pixel during the entire frame period. I looked at examples.

7 is a diagram showing a configuration for applying MSB data during a subframe interval instead of black data according to another embodiment of the present invention. Unlike FIGS. 5 and 6, this is a method of emitting light as much as the light emitting section (first subframe section) corresponding to the existing MSB. Looking more closely, it is as follows.

In the first frame (Frame_Odd), an image is output on odd-numbered gate lines, and MSB is reflected in data of a corresponding sub-pixel on even-numbered gate lines to emit light during the first sub-frame period (see 721). Black data is output during the second to fourth subframe intervals (SF2 to SF4) (see 722).

Conversely, in the second frame (Frame_Even), an image is output on even-numbered gate lines, and MSB is reflected in data of a corresponding sub-pixel on odd-numbered gate lines to emit light during the first sub-frame period (see 711). Black data is output during the second to fourth subframe intervals (SF2 to SF4) (see 712).

Outputting the black data during the second to fourth subframe intervals corresponds to an MSB only in the first subframe interval.

7 shows that, in the case of using the conventional interlace method, data signals are applied to half of the gate lines during one frame period, and the other half of the A value corresponding to a representative value among data of a corresponding subpixel, such as MSB among data signals, is applied to the gate line in a partial interval (eg, the first subframe interval) to increase overall luminance and reduce power consumption.

That is, in the remaining half of the gate lines, each subpixel may be continuously turned on or off according to the MSB during the first subframe period. 5 and 6, some sub-pixels are turned on/off instead of black data corresponding to the MSB of gray level during a frame period, but in FIG. 7, some sub-pixels in some section of the frame period correspond to MSB of gray level instead of black data On/off can be set. Compared to FIGS. 5 and 6, the luminance may be slightly lower, but it has an effect of not being brighter than the original gray level.

Accordingly, it is possible to select between the frame interval method of FIGS. 5 and 6 and the subframe interval method of FIG. 7 according to the luminance of the screen and the characteristics of the image. Such selection may be determined by the aforementioned timing controller 140 or the interlace controller 1220 constituting the timing controller 140 . By calculating the luminance of the entire image, the method of FIG. 7 can be applied when the luminance is below a certain level, and the method of FIG. 5 can be applied when the luminance of the entire image is above a certain level.

8 is a diagram showing an example of excluding the output of black data according to another embodiment of the present invention. Each sub-pixel of the even-numbered gate lines in the first frame (Frame_Odd) period of the odd-numbered gate line emits light in response to the MSB during the first sub-frame period. In addition, during the second to fourth subframe intervals SF2 to SF4 of the first frame Frame_Odd of the odd-numbered gate line, the even-numbered gate lines operate as the first subframe interval of the second frame Frame_Even ( 821).

Similarly, in the first subframe section (refer to 821) of the second frame (Frame_Even) section of the even-numbered gate line, odd-numbered gate lines operate as the second to fourth sub-frame sections, as described above. And, during the second to fourth subframe intervals (SF2 to SF4) of the second frame (Frame_Even) of the even-numbered gate lines, each sub-pixel of the odd-numbered gate lines emits light in response to MSB instead of black data. (see 810).

The configuration of FIG. 8 provides an effect of reducing the entire frame section compared to the configurations of FIGS. 5 to 7 . Also, since black data is not output, luminance loss does not occur. Compared to FIG. 7 , since a scan for applying black data is not required, the overall number of scans is reduced, so that more 1H scan time can be secured.

Hereinafter, an example in which each subpixel of the display panel emits light among subframe sections within a frame section according to an embodiment of the present invention will be described.

Data applied to the entire display panel is shown in Table 1 below. A subpixel is defined at a point where one gate line GL and one data line DL intersect, and Table 1 shows the size of a gray level to be output by each subpixel. For convenience of explanation, it is assumed that n is an even number. The first subframe corresponds to the first bit of each gray level, the second subframe corresponds to the second bit of each gray level, the third subframe corresponds to the third bit of each gray level, and the fourth subframe corresponds to the fourth bit of each gray level. . For example, the gradation of the subpixel defined by GL1-DL1 is "1101", ON during the first and second subframe periods, OFF during the third subframe period, and during the fourth subframe period. keep ON

DL1 DL2 … DLm GL1 1101 1001 0110 GL2 0101 1000 1110 GL3 0110 1010 1001 … GLn 1100 0100 0011

9 is a diagram showing light emission levels of each sub-pixel of a display panel according to an exemplary embodiment of the present invention.

When the embodiment of FIG. 5 is applied, 910 to 940 indicate emission or non-emission of each sub-pixel during the first frame period (Frame_Odd). When the corresponding subpixel is turned on during the corresponding subframe period, it is indicated as ON, and when it is not turned on, it is indicated as OFF.

910 shows the first subframe period. Accordingly, the subpixels connected to the odd-numbered gate lines GL1, GL3, ..., GL(n-1) are turned ON or OFF only for the first subframe period according to the MSB of each gray level. On the other hand, the subpixels connected to the even-numbered gate lines GL2, GL4, ..., GLn are turned on or off according to the MSB of each gray level, but this section is the second subframe of the first frame section, such as 920 to 940 to the fourth subframe (see 520 in FIG. 5).

920 shows the second subframe period. Accordingly, the subpixels connected to the odd-numbered gate lines GL1, GL3, ..., GL(n-1) are turned ON or OFF only for the second subframe period according to the second bit of each gray level. On the other hand, sub-pixels connected to even-numbered gate lines GL2, GL4, ..., GLn remain on or off according to the MSB of each gray level addressed at 910 (see 520 in FIG. 5).

930 shows the third subframe period. Accordingly, subpixels connected to odd-numbered gate lines GL1, GL3, ..., GL(n-1) are turned ON or OFF only for the third subframe period according to the third bit of each gray level. On the other hand, sub-pixels connected to even-numbered gate lines GL2, GL4, ..., GLn remain on or off according to the MSB of each gray level addressed at 910 (see 520 in FIG. 5).

940 shows the fourth subframe period. Accordingly, the subpixels connected to the odd-numbered gate lines GL1, GL3, ..., GL(n-1) are turned ON or OFF only for the fourth subframe period according to the second bit of each gray level. On the other hand, sub-pixels connected to even-numbered gate lines GL2, GL4, ..., GLn remain on or off according to the MSB of each gray level addressed at 910 (see 520 in FIG. 5).

10 is a diagram showing light emission levels of each sub-pixel of a display panel according to another exemplary embodiment of the present invention.

When the embodiment of FIG. 7 is applied, 1010 to 1040 indicate emission or non-emission of each sub-pixel in the first frame section (Frame_Odd). When the corresponding subpixel is turned on during the corresponding subframe period, it is indicated as ON, and when it is not turned on, it is indicated as OFF.

Since the odd-numbered gate lines in the first frame period (Frame_Odd) operate in the same way as 910 to 940 in FIG. 9, descriptions thereof are omitted.

1010 shows the first subframe period. The subpixels connected to the even-numbered gate lines GL2, GL4, ..., GLn turn on or off according to the MSB of each gray level, but this section is maintained only during the first subframe section of the first frame section (Fig. 7 of 721).

1020 shows the second subframe period. Sub-pixels connected to even-numbered gate lines GL2, GL4, ..., GLn operate as black data, that is, OFF (see 722 of FIG. 7). This is also maintained in the third subframe period 1030 and the fourth subframe period 1040.

10 shows a configuration in which subpixels connected to even-numbered gate lines GL2, GL4, ..., GLn are turned on or off by the size of the first subframe period of the odd-numbered gate line, that is, the period corresponding to the MSB. While increasing the overall luminance, this has the advantage of consuming less power compared to FIG. 9 .

10 shows that, in the case of using the conventional interlacing method, data signals are applied to half of the gate lines during one frame period, and the other half of the A value corresponding to a representative value among data of a corresponding subpixel, such as MSB among data signals, is applied to the gate line in a partial interval (eg, the first subframe interval) to increase overall luminance and reduce power consumption.

That is, in the remaining half of the gate lines, each subpixel may be continuously turned on or off according to the MSB during the first subframe period. 5 and 6, some sub-pixels are turned on/off instead of black data corresponding to the MSB of gray level during a frame period, but in FIG. 7, some sub-pixels in some section of the frame period correspond to MSB of gray level instead of black data On/off can be set. Compared to FIG. 9 , the luminance may be slightly lower, but there is an effect that the gray level is not brighter than the original gray level.

Therefore, it is possible to select between the frame interval method of FIG. 9 and the subframe interval method of FIG. 10 according to the luminance of the screen and the characteristics of the image. Such selection may be determined by the aforementioned timing controller 140 or the interlace controller 1220 constituting the timing controller 140 . By calculating the luminance of the entire image, the method of FIG. 10 may be applied when the luminance is below a certain level, and the method of FIG. 9 may be applied when the luminance of the entire image is above a certain level.

11 is a diagram showing light emission levels of each sub-pixel of a display panel according to another exemplary embodiment of the present invention. When the embodiment of FIG. 8 is applied, the emission or non-emission of each sub-pixel in the first frame section (Frame_Odd) is the same as that of FIG. 9 . In FIG. 11 , emission or non-emission of sub-pixels of respective gate lines corresponding to the second frame period (Frame_Even) in odd-numbered gate lines is examined.

First, in the second frame period (Frame_Even) indicated by 810 of FIG. 8, odd-numbered gate lines emit or do not emit light in response to the MSB of each gray level instead of black data. Meanwhile, a section corresponding to this section (810 in FIG. 8) is a section corresponding to the second subframe to the fourth subframe in the even-numbered gate line. That is, the odd-numbered gate lines GL1, GL3, ..., GL(n-1) remain ON or OFF according to the MSB. Sections to be maintained are sections 1110, 1120, and 1130 corresponding to the second to fourth subframes of even-numbered gate lines, corresponding to section 810 in FIG.

A light emitting state of the subpixels in the display panel during the second subframe SF2 of the even-numbered gate lines GL2, GL4, ..., GLn is 1110. Depending on the second bit, ON or OFF is maintained during the second subframe period.

A light emission state of the subpixels in the display panel during the third subframe SF3 of the even-numbered gate lines GL2, GL4, ..., GLn is 1120. According to the third bit, ON or OFF is maintained during the third subframe period.

A light emitting state of the subpixels in the display panel during the fourth subframe SF4 of the even-numbered gate lines GL2, GL4, ..., GLn is 1130. According to the fourth bit, ON or OFF is maintained during the fourth subframe period.

The embodiments of FIGS. 5 to 11 are summarized as follows. In interlaced digital driving, sub-pixels are controlled to emit or not emit light using a representative value corresponding to a corresponding gradation instead of black data, thereby reducing scan time while preventing luminance loss, thereby increasing overall power consumption reduction effect.

Hereinafter, a display device according to an embodiment of the present invention has the same configuration as shown in FIG. 1, and has a first group of gate lines and gray levels for applying gray level data signals to sub-pixels within a frame period in interlaced digital driving. and a timing controller 140 that controls gate lines of a second group for applying data signals corresponding to representative values of data of to each sub-pixel.

12 is a diagram showing the configuration of the timing controller 140 according to an embodiment of the present invention. The timing controller 140 includes a subframe converter 1210, an interlace controller 1220, a gate driver controller 1230, and a data driver controller 1240.

The subframe conversion unit converts one frame period into K subframes each including an addressing period and an emission period. As described above, one frame period may be composed of a plurality of subframes. For example, when the gray level of a subpixel is represented by 8 bits, it can be converted into 8 subframes.

The interlace controller 1220 controls the gate driver 120 and the data driver 130 to apply data signals corresponding to each of the K subframes to the subpixels connected to the first group of gate lines during the first frame period. and controls the gate driver 120 and the data driver 130 to apply data signals corresponding to each of the L subframes smaller than K to the subpixels connected to the gate lines of the second group during the first frame period. can do. Here, the gate driver 120 and the data driver 130 can be controlled through the gate driver controller 1230 and the data driver controller 1240 described above. In another embodiment, the interlace controller 1220 directly controls the gate driver 120 ) and the data driver 130 may be controlled. That is, in this specification, the meaning that the interlace controller 1220 controls the driver 120 and the data driver 130 includes all methods directly or indirectly through the driver controller 1230 and the data driver controller 1240.

In an embodiment, the data signal indicates a state in which each subpixel is turned on/off during a specific subframe. In addition, as an example, the data signal indicates a state and time when each subpixel is turned on/off within a specific subframe. This may vary depending on whether each subframe corresponds to one bit representing a gray level or a plurality of bits.

In more detail, the interlace control unit 1220 applies data signals corresponding to each of the K subframes to the gate lines of the first group among the gate lines divided into two or more groups to obtain subpixels connected to the gate lines of the first group. This means a case where the gradation of data can be expressed as it is. Referring to FIG. 5 above, OddLine in Frame_Odd corresponds to the first group.

Next, for the second group of gate lines that do not correspond to the first group, the interlace controller 1220 provides L subpixels smaller than K to subpixels connected to the second group of gate lines during the first frame period. The gate driver and the data driver are controlled to apply a data signal corresponding to a frame period. For example, it means a method of applying data signals corresponding to some of the K subframes. In one embodiment, the gray level of data may be expressed in a subframe corresponding to the MSB. In this case, data signals may be applied to subframes corresponding to the MSB in the entire first frame period. In another embodiment, a data signal may be applied to a subframe corresponding to the MSB in part of the first frame period (eg, as long as the length of the longest subframe period).

In addition, in another embodiment, the gray level of data may be expressed in a subframe corresponding to the MSB and the next two bits. For example, a data signal may be applied to subframes corresponding to upper two bits among a total of four bits. For example, a data signal may be applied to corresponding subpixels during a subframe period corresponding to the upper two bits of the first frame period.

Referring to the embodiments of FIGS. 5 and 6 , L may be 1. That is, the data signal may be applied in one subframe corresponding to the most significant bit (MSB). In an embodiment, the interlace control unit 1220 operates the gate driver 120 and the gate driver 120 to apply a data signal corresponding to a representative value of a gray level to be applied to each of the sub-pixels connected to the gate lines of the second group during the first frame period. The data driver 130 may be controlled. In FIGS. 5 and 6 , among subpixels connected to the gate line of the second group of the first frame period, a subpixel having an MSB of 1 may maintain an on state. The MSB is a representative value of the gray level, and the MSB and the next higher order bit can be selected according to the number of L's. That is, the representative value of the gray level may be composed of one or more most important bits among a plurality of bits constituting the corresponding gray level.

In FIGS. 5 and 6 , subpixels connected to gate lines of the second group are expressed as representative values of gray levels in the entire frame period. 7 is an embodiment in which the temporal length is limited to a section of a subframe corresponding to a representative value. In more detail, the interlace control unit 1220 applies a data signal corresponding to a representative value of a grayscale to be applied to each of the subpixels connected to the gate lines of the second group during some subframes of the first frame period. The gate driver 120 and the data driver 130 may be controlled. When L is 1 as an example, some subframe intervals are data signals corresponding to MSBs, which are representative values of gray levels to be applied to each of the subpixels connected to the gate lines of the second group during the subframe intervals corresponding to the MSB. As a result, as shown in FIG. 7, while the subpixels of the gate lines of the first group maintain an on state corresponding to the grayscale data of the corresponding subframe in each of the K subframe periods, the second group of Subpixels of the gate lines maintain an on state corresponding to grayscale data of a corresponding subframe during a portion, that is, one subframe period (first subframe period).

In summary, among the K subframe sections of the first group, corresponding to the subframe sections corresponding to the representative grayscale values, the gate lines of the second group are turned on corresponding to the representative grayscale values of the subpixels in the L subframes. state can be maintained.

Next, referring to the embodiment of FIG. 8 , an embodiment in which the interlace control unit 1220 configures frame sections to overlap has been described. That is, the first frame section may be divided into a first time section and a second time section. In FIG. 8 , the first frame section is Frame_Odd with the gate line of the first group as the center. In Odd_Line, SF1 corresponds to the first time section and SF2 to SF4 correspond to the second time section. The interlace control unit 1220 applies data signals corresponding to P number of subframe periods smaller than K to subpixels connected to the first group of gate lines (for example, OddLine in FIG. 8) during the first time period; A data signal corresponding to one or more subframe periods is applied to the subpixels connected to the gate lines of the second group (see 820 of FIG. 8 ). To this end, the interlace controller 1220 controls the gate driver 120 and the data driver 130 .

In the second time interval, data signals corresponding to (K-P) subframe intervals are applied to subpixels connected to the gate lines of the first group (SF2 to SF4 at Frame_Odd in FIG. 8), and the gate lines of the second group The interlace controller 1220 controls the gate driver 120 and the data driver 130 to apply data signals corresponding to one or more subframe periods to subpixels connected to the subpixels (see 821 of FIG. 8 ).

That is, as described in the embodiments of FIGS. 8 and 11 , the frame intervals are set to be different for each group of gate lines, and the frame intervals for each group overlap, thereby reducing the total scan time. As a result, the entire frame section is reduced, and since there is no section in which black data is output, overall luminance is improved, providing a good effect in terms of driving speed and power consumption.

In summary, in an embodiment of the present invention, when interlace driving is applied, sub-pixels of gate lines of a group output as black data are also kept in an on state for a specific time according to a representative value of a gray level. Here, an example of the representative value includes the most significant bit or the most significant L bits of data expressing the gray level.

In addition, the time to maintain the on state may be the entire frame period examined in FIGS. 5 and 6 or a part of the frame period reviewed in FIG. 7 . In addition, an embodiment in which frame sections are overlapped by different groups of gate lines has been reviewed in FIG. 8 .

In this specification, two groups have been described, but the present invention is not limited thereto, and may be applied to three or more groups of gate lines. In this case, two groups of gate lines may correspond to the first group, and the remaining one group of gate lines may correspond to the second group. Or vice versa.

When the configuration of FIG. 12 is applied, a data signal corresponding to a representative value of a gray scale such as MSB is applied instead of black data to a sub-pixel of gate lines corresponding to an idle state in interlaced digital driving, thereby reducing luminance loss according to the interlace driving method. can reduce power consumption and secure driving time.

Summarizing the timing controller 140 of FIG. 12, the subframe converting unit 1210 converts one frame period into K subframes each including an addressing period and a light emitting period, and a grayscale data signal within the frame period. An interlace controller 1220 is provided to control a first group of gate lines applied to each sub-pixel and a second group of gate lines respectively applying data signals corresponding to representative values of grayscale data to sub-pixels. Optionally, the timing controller 140 may include a gate driver controller 1230 and a data driver controller 1240 . In another embodiment, the interlace controller 1220 may provide functions of the gate driver controller 1230 and the data driver controller 1240 .

13 is a diagram showing a process of time division driving of a display device according to an embodiment of the present invention.

13 illustrates the steps of applying a data signal corresponding to each of K subframes to the first group of subpixels connected to the first group of gate lines within the frame period and the steps of applying the data signal to the second group of gate lines during the frame period. A method of implementing interlaced digital driving, which is time division driving, is shown, including the step of applying a data signal corresponding to each of the L subframes smaller than K to the second group of subpixels.

First, the first group of gate lines and the second gate lines are classified during a frame period consisting of K subframes (S1310). This can be set by the subframe conversion unit 1210 of the timing controller 140 in consideration of the number of bits of the gray level.

Next, data signals corresponding to each of the K subframes are applied to the first group of subpixels connected to the first group of gate lines in a preset order (S1320). This may be controlled according to how many gate lines the interlace controller 1220 of the timing controller 140 applies scan signals to during one frame period. The first group refers to gate lines displaying all gray levels.

During the above-described frame period, data signals corresponding to each of L subframes smaller than K are applied to the subpixels of the second group connected to the gate lines of the second group (S1330). According to an embodiment, sub-pixels of the second group, which should be turned off during one frame period, are turned on or off corresponding to the representative value of the gray level. As discussed above, L may be 1 or more. In order to shorten the frame period in consideration of temporal characteristics of interlace, L may be set to 1. In addition, L may be set to 2 or more to accurately express image grayscale rather than temporal characteristics of interlace.

In more detail, the gate lines of the first group and the gate lines of the second group may alternately receive scan signals. And, as described above in the embodiment of FIG. 6 , the first group of gate lines may receive K scan signals to apply data signals corresponding to K subframes to the first group of subpixels. . On the other hand, the gate lines of the second group receive scan signals L times so that data signals corresponding to the L subframes can be applied to the subpixels of the second group. In FIG. 6, an example in which GL2, GL4, ... receives one scan signal while GL1, GL3, ..., GL(n) receives four scan signals has been described. 6, while GL2, GL4, ... receive one scan signal instead of black data, it can be expressed by turning on/off in the subframe section corresponding to the MSB of the gray level of the corresponding subpixels, thereby increasing luminance. can

Also, as shown in FIG. 6 , in step S1330 of applying a data signal to the sub-pixels of the second group, a data signal corresponding to a representative value of a gray level to be applied to each of the sub-pixels of the second group is applied during the frame period. It includes steps to In this case, L may be 1.

As shown in FIG. 7 , in step S1330 of applying a data signal to the sub-pixels of the second group, a data signal corresponding to a representative value of a gray level to be applied to each of the sub-pixels of the second group is transmitted during a partial sub-frame period among frame periods. Include the steps to authorize. In this case, L becomes 1, and the representative value of the gray level may be the MSB among bits of data representing the gray level.

Also, as shown in FIG. 8, a structure in which frame sections overlap may be used. That is, the frame period includes a first time period and a second time period, and the step of applying the data signal to the sub-pixels of the first group (S1320) is connected to the gate lines of the first group in the first time period. Applying data signals corresponding to P number of subframe periods smaller than K to subpixels, and in a second time period, to subpixels connected to the gate lines of the first group corresponding to (K−P) number of subframe periods. and applying a data signal (Frame_Odd section of OddLine in FIG. 8).

In addition, the step of applying a data signal to the subpixels of the second group (S1330) is a step of applying a data signal corresponding to one or more subframe sections to the subpixels of the second group in the first time interval (FIG. 8 820 of) and applying data signals corresponding to K subframe sections to the subpixels of the second group in the second time interval (see 821 of FIG. 8).

The division of the frame intervals in this way is the same even when the first group and the second group are switched. 8, it can be seen that Frame_Odd of OddLine overlaps the whole of Frame_Odd of EvenLine and a part of Frame_Even. Similarly, Frame_Evne of EvenLine overlaps a part of Frame_Odd of OddLine and the whole of Frame_Even. Through this, the time required to apply the data signal to all of the gate lines of the two groups can be reduced by about 25% compared to the conventional interlace method, and thus the scan time can be reduced.

The process of FIG. 13 may be controlled by the timing controller 140 .

When the embodiment of the present invention is applied, when driving in an interlace method during digital driving, a signal is applied to turn on or off subpixels corresponding to representative values of grayscale data instead of black data in the idle period in the idle period. do.

In particular, the representative value includes MSB data of grayscale data as an example, and includes all data representing the value (pixel value) of the sub-pixel.

An embodiment of the present invention can be applied to all driving methods that perform time division, such as PDP driving, in addition to digital driving. In addition, a representative value such as MSB may be applied to the entire frame period (see FIGS. 5 and 6), or may be applied only to the driving time of a subframe representing the corresponding MSB (see FIG. 7).

As reviewed in FIG. 8 , when a signal is applied only during the driving time of a subframe representing a corresponding MSB, driving can be performed by reducing the overall driving time.

14 is a diagram showing a configuration for applying MSB data during a subframe interval instead of black data according to another embodiment of the present invention. Unlike FIG. 7, it is a method of emitting light as much as the light emitting period (first subframe period) corresponding to the existing MSB, but it is an embodiment in which the light emitting period is different.

In the first frame (Frame_Odd), an image is output from odd-numbered gate lines, and black data is output from even-numbered gate lines (see 1421). Then, during the second to fourth subframe periods (SF2 to SF4), odd-numbered gate lines output images, and even-numbered gate lines reflect the MSB of the corresponding sub-pixel data to emit light (1422). reference).

Conversely, in the second frame Frame_Even, images are output on even-numbered gate lines and black data is output on odd-numbered gate lines (see 1411). During the second to fourth subframe periods (SF2 to SF4), even-numbered gate lines output images, and odd-numbered gate lines reflect the MSB of the corresponding sub-pixel data and emit light from the sub-pixels (see 1412). ).

FIG. 14 shows an embodiment in which subframe sections 1412 and 1422 outputting representative values of gray levels, such as MSB, in gate lines set to idle do not coincide with subframes of gate lines outputting images.

In the past, in the interlaced method, specific gate lines did not emit light, so overall luminance was insufficient, and to compensate for this, there was a problem that more EVDD or SVDD had to be applied. Many of the advantages have been offset. However, when the present invention is applied, overall luminance can be increased by causing sub-pixels of gate lines not to emit light at all in a specific frame in the interlace method to emit light corresponding to a representative value of data. In addition, since the total luminance is increased, the effect of reducing power consumption can be enhanced.

Although the above has been described based on the embodiments of the present invention, various changes or modifications may be made at the level of those skilled in the art. Accordingly, it will be understood that such changes and modifications are included within the scope of the present invention as long as they do not depart from the scope of the present invention.

100: display device 110: display panel
120: gate driver 130: data driver
140: timing controller 1210: subframe converter
1220: interlace control unit

Claims (15)

a display panel on which a plurality of sub-pixels defined by intersections of gate lines and data lines are arranged;
a gate driver applying a first signal to the gate line;
a data driver applying a second signal to the data line; and
A subframe converting unit that converts one frame period into K subframes each including an addressing period and a light emitting period; and each of the K subframes to subpixels connected to the gate lines of the first group during the first frame period. Controls the gate driver and the data driver to apply a corresponding data signal, and data corresponding to each of the L subframes smaller than K to subpixels connected to the gate lines of the second group during the first frame period. a timing controller including an interlace control unit controlling the gate driver and the data driver to apply a signal;
The interlace control unit controls the gate driver and the data driver to apply a data signal corresponding to a representative value of a gray level to be applied to each of the sub-pixels connected to the gate line of the second group during the first frame period. Device.
According to claim 1,
Wherein L is 1, a display device.
delete delete a display panel on which a plurality of sub-pixels defined by intersections of gate lines and data lines are arranged;
a gate driver applying a first signal to the gate line;
a data driver applying a second signal to the data line; and
A subframe converting unit that converts one frame period into K subframes each including an addressing period and a light emitting period; and each of the K subframes to subpixels connected to the gate lines of the first group during the first frame period. Controls the gate driver and the data driver to apply a corresponding data signal, and data corresponding to each of the L subframes smaller than K to subpixels connected to the gate lines of the second group during the first frame period. a timing controller including an interlace control unit controlling the gate driver and the data driver to apply a signal;
The first frame section includes a first time section and a second time section,
The interlace control unit
During the first time interval, data signals corresponding to P number of subframe intervals smaller than K are applied to subpixels connected to the gate lines of the first group, and one data signal is applied to the subpixels connected to the gate lines of the second group. controlling the gate driver and the data driver to apply a data signal corresponding to the above subframe period;
During the second time interval, data signals corresponding to (KP) number of subframe periods are applied to the subpixels connected to the gate lines of the first group, and one data signal is applied to the subpixels connected to the gate lines of the second group. A display device controlling the gate driver and the data driver to apply a data signal corresponding to the above subframe period.
Controlling a gate driver for applying a first signal to the gate line and a data driver for applying a second signal to the data line of a display panel in which a plurality of subpixels defined by crossing a plurality of gate lines and data lines are disposed In the timing controller,
a subframe converting unit for converting one frame period into K subframes each including an addressing period and an emission period; and
Controls the gate driver and the data driver to apply data signals corresponding to each of the K subframes to subpixels connected to a first group of gate lines during a first frame period; An interlace control unit controlling the gate driver and the data driver to apply a data signal corresponding to each of the L subframes smaller than K to subpixels connected to the gate lines of the group;
The interlace controller controls the gate driver and the data driver to apply a data signal corresponding to a representative value of a gray level to be applied to each of the subpixels connected to the gate line of the second group during the first frame period. controller.
According to claim 6,
Wherein L is 1, the timing controller.
delete delete Controlling a gate driver for applying a first signal to the gate line and a data driver for applying a second signal to the data line of a display panel in which a plurality of subpixels defined by crossing a plurality of gate lines and data lines are disposed In the timing controller,
a subframe converting unit for converting one frame period into K subframes each including an addressing period and an emission period; and
Controls the gate driver and the data driver to apply data signals corresponding to each of the K subframes to subpixels connected to a first group of gate lines during a first frame period; An interlace control unit controlling the gate driver and the data driver to apply a data signal corresponding to each of the L subframes smaller than K to subpixels connected to the gate lines of the group;
The first frame section includes a first time section and a second time section,
The interlace control unit
During the first time interval, data signals corresponding to P number of subframe intervals smaller than K are applied to subpixels connected to the gate lines of the first group, and one data signal is applied to the subpixels connected to the gate lines of the second group. controlling the gate driver and the data driver to apply a data signal corresponding to the above subframe period;
During the second time interval, data signals corresponding to (KP) number of subframe periods are applied to the subpixels connected to the gate lines of the first group, and one data signal is applied to the subpixels connected to the gate lines of the second group. A timing controller controlling the gate driver and the data driver to apply a data signal corresponding to the above subframe period.
classifying a first group of gate lines and a second gate line to be controlled during a frame period consisting of K subframes;
applying a data signal corresponding to each of the K subframes to a first group of subpixels connected to the first group of gate lines in a preset order; and
applying a data signal corresponding to each of the L subframes smaller than K to a second group of subpixels connected to a second group of gate lines during the frame period;
The step of applying a data signal to the sub-pixels of the second group
and applying a data signal corresponding to a representative value of a gray level to be applied to each of the sub-pixels of the second group during the frame period.
According to claim 11,
The gate lines of the first group and the gate lines of the second group alternately receive scan signals;
receiving K scan signals so that the gate lines of the first group can apply data signals corresponding to the K subframes to the subpixels of the first group; and
and receiving L scan signals so that the gate lines of the second group can apply data signals corresponding to the L subframes to the subpixels of the second group.
According to claim 11,
The time division driving method of the display device, wherein L is 1.
delete classifying a first group of gate lines and a second gate line to be controlled during a frame period consisting of K subframes;
applying a data signal corresponding to each of the K subframes to a first group of subpixels connected to the first group of gate lines in a preset order; and
applying a data signal corresponding to each of the L subframes smaller than K to a second group of subpixels connected to a second group of gate lines during the frame period;
The frame interval includes a first time interval and a second time interval,
In the step of applying the data signal to the subpixels of the first group, in the first time interval, the data signals corresponding to P number of subframe intervals smaller than K are applied to the subpixels connected to the gate lines of the first group. and, in the second time interval, applying data signals corresponding to (KP) number of subframe intervals to subpixels connected to the first group of gate lines,
The step of applying a data signal to the subpixels of the second group may include applying a data signal corresponding to one or more subframe sections to the subpixels of the second group in the first time period; and applying data signals corresponding to K subframe periods to the second group of subpixels in the period.

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