CN119360795A - Pixel unit, display panel and display device - Google Patents
Pixel unit, display panel and display device Download PDFInfo
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Abstract
本发明提出一种像素单元、显示面板和显示装置，其中，像素单元包括像素电极、第一存储电容、第二存储电容、第一切换电路、第二切换电路、数据开关和极性切换电路，在前一帧中，像素单元可接收到行扫描信号和数据信号，极性切换电路可切换输出第一电平信号，此时，数据开关、第一切换电路和第二切换电路对应切换，并输出数据信号至像素电极，在下一帧中，极性切换电路切换输出第二电平信号，数据开关无数据信号输出，第一切换电路和第二切换电路切换输出，此时，像素电极接收到相反极性的数据信号，实现极性切换，并且在相邻两帧内，两个存储电容存储同极性的数据电压，避免了大幅度的电压充放，降低了充放电功耗。
The present invention proposes a pixel unit, a display panel and a display device, wherein the pixel unit includes a pixel electrode, a first storage capacitor, a second storage capacitor, a first switching circuit, a second switching circuit, a data switch and a polarity switching circuit. In the previous frame, the pixel unit can receive a row scanning signal and a data signal, and the polarity switching circuit can switch to output a first level signal. At this time, the data switch, the first switching circuit and the second switching circuit are switched accordingly and output the data signal to the pixel electrode. In the next frame, the polarity switching circuit switches to output a second level signal, the data switch has no data signal output, and the first switching circuit and the second switching circuit switch output. At this time, the pixel electrode receives a data signal of opposite polarity to achieve polarity switching, and in two adjacent frames, the two storage capacitors store data voltages of the same polarity, thereby avoiding large-scale voltage charging and discharging and reducing charging and discharging power consumption.
Description
Technical Field
The invention belongs to the technical field of display panels, and particularly relates to a pixel unit, a display panel and a display device.
Background
The liquid crystal display panel has the advantages of high resolution, accurate color reproduction, simple structure, high stability and the like, and the traditional liquid crystal display panel realizes different gray scale display by controlling the deflection of liquid crystal molecules so as to control the throughput of polarized light.
In the liquid crystal display panel, liquid crystal molecules are driven to rotate by applying voltages across the liquid crystal layer. If a unidirectional electric field is applied to the liquid crystal molecules for a long period of time, polarization of the liquid crystal molecules occurs. After the liquid crystal molecules are polarized, the response characteristics of the liquid crystal are changed, for example, the response speed is lowered, and the display is not uniform. Therefore, polarity switching is required to avoid polarization of the liquid crystal molecules.
When the polarity is switched, the storage capacitor in the pixel unit needs to perform a large-amplitude charging and discharging action to ensure that the liquid crystal pixel displays according to the correct polarity, and the large-amplitude charging and discharging action increases the circuit power consumption.
Disclosure of Invention
The invention aims to provide a pixel unit and aims to solve the problem that the power consumption of the traditional pixel unit is high when the polarity is switched.
A first aspect of an embodiment of the present invention provides a pixel unit, including:
A pixel electrode;
a first storage capacitor;
a second storage capacitor;
The first input end of the first switching circuit is connected with the first end of the first storage capacitor, the second input end of the first switching circuit, the second end of the first storage capacitor and the first end of the second storage capacitor are connected, the output end of the first switching circuit is connected with the pixel electrode, and the first switching circuit is triggered by a first level signal to be communicated with the first input end and the output end or triggered by a second level signal to be communicated with the second input end and the output end;
The input end of the second switching circuit is connected with the common electrode end, the first output end of the second switching circuit, the second end of the first storage capacitor and the first end of the second storage capacitor are connected, the second output end of the second switching circuit is connected with the second end of the second storage capacitor, and the second switching circuit is triggered by the first level signal to be communicated with the input end and the first output end or is triggered by the second level signal to be communicated with the input end and the second output end;
The input end of the data switch is connected with a data line, the output end of the data switch, the first end of the first storage capacitor and the second end of the second storage capacitor are connected, and the data switch is used for transmitting data signals of the data line when line scanning signals of the rows are received at intervals of one frame;
The polarity switching circuit is respectively connected with the scanning line, the first switching circuit and the second switching circuit and is used for switching the polarity of the output level when a row of scanning signals transmitted by the scanning line are received.
Optionally, the first switching circuit includes a first transistor and a second transistor;
The first end of the first transistor forms a first input end of the first switching circuit, the first end of the second transistor forms a second input end of the first switching circuit, the second end of the first transistor and the second end of the second transistor form an output end of the first switching circuit, and the control end of the first transistor and the control end of the second transistor are connected to form a control end of the first switching circuit.
Optionally, the second switching circuit includes a third transistor and a fourth transistor;
The first end of the third transistor and the first end of the fourth transistor are connected to form an input end of the second switching circuit, the second end of the third transistor forms a first output end of the second switching circuit, and the second end of the fourth transistor forms a second output end of the second switching circuit.
Optionally, the data switch includes a fifth transistor;
The first end of the fifth transistor is connected with the data line, the control end of the fifth transistor is connected with the scanning line, the second end of the fifth transistor forms the output end of the data switch, and the data line receives one data signal every other frame.
Optionally, the polarity switching circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a first resistor, a first capacitor, a second capacitor, and an and gate;
The first input end of the AND gate is connected with the scanning line, the second input end of the AND gate, the first end of the first capacitor and the first end of the eighth transistor are connected, the output end of the AND gate is connected with the first end of the sixth transistor, the second end of the sixth transistor is connected with the control end of the seventh transistor, the control end of the sixth transistor, the control end of the eighth transistor and the enabling signal end are connected, the first end of the seventh transistor is connected with the common electrode end, the second end of the seventh transistor, the first end of the first resistor, the second end of the eighth transistor and the first end of the second capacitor are connected to form the output end of the polarity switching circuit, the second end of the first resistor is connected with a first positive voltage end, and the second end of the first capacitor and the second end of the second capacitor are grounded;
The enabling signal end is used for inputting enabling signals, and the enabling signals are identical to the line scanning signals input by the scanning lines in phase.
Optionally, the and gate includes a first diode, a second diode, and a second resistor;
the cathode of the first diode forms a first input end of the AND gate, the cathode of the second diode forms a second input end of the AND gate, the anode of the first diode, the anode of the second diode and the first end of the second resistor are connected to form an output end of the AND gate, and the second end of the second resistor is connected with a second positive voltage end.
Optionally, the polarity of the enable signal is opposite to that of the row scan signal input by the scan line, and the enable signal end is connected with the scan line connected with the pixel unit in the next row.
Optionally, the pixel unit further includes a voltage stabilizing capacitor, a first end of the voltage stabilizing capacitor is connected to the output end of the polarity switching circuit, and a second end of the voltage stabilizing capacitor is grounded.
A second aspect of the embodiments of the present invention provides a display panel, including a plurality of scan lines, a plurality of data lines, and a plurality of pixel units as described above, where the pixel units are respectively connected to one of the scan lines and one of the data lines.
A third aspect of an embodiment of the present invention provides a display device including a driving circuit of a display panel and the display panel described above, the driving circuit of the display panel being connected to the display panel.
Compared with the prior art, the pixel unit has the advantages that the pixel unit comprises a pixel electrode, a first storage capacitor, a second storage capacitor, a first switching circuit, a second switching circuit, a data switch and a polarity switching circuit, wherein in the previous frame, the pixel unit can receive a row scanning signal and a data signal, the polarity switching circuit can switch and output a first level signal, at the moment, the data switch, the first switching circuit and the second switching circuit are correspondingly switched and output a data signal to the pixel electrode, in the next frame, the polarity switching circuit is switched and output a second level signal, the data switch does not have a data signal output, the first switching circuit and the second switching circuit are switched and output, at the moment, the pixel electrode receives data signals with opposite polarities, polarity switching is realized, and in two adjacent frames, the two storage capacitors store data voltages with the same polarities, so that voltage charge and discharge of a large amplitude are avoided, and charge and discharge power consumption is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a display panel according to a first embodiment and a third embodiment of the present invention;
Fig. 2 is a schematic structural diagram of a pixel unit according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of signal timing of a pixel unit according to a first embodiment of the present invention;
fig. 4 is a schematic circuit diagram of a first circuit of a pixel unit according to a second embodiment of the invention;
FIG. 5 is a schematic diagram of signal timing of a pixel unit according to a second embodiment of the present invention;
Fig. 6 is a second circuit schematic of a pixel unit according to the second embodiment of the invention;
fig. 7 is a schematic structural diagram of a display device according to a fourth embodiment of the present invention.
Wherein, each reference sign in the figure is:
100. Display panel, 200, driving circuit of display panel, 210, source driving circuit, 220, gate driving circuit, 230, time schedule controller, 10, pixel unit, 11, pixel electrode, 12, first switching circuit, 13, second switching circuit, 14, data switch, 15, polarity switching circuit;
T1, a first transistor, T2, a second transistor, T3, a third transistor, T4, a fourth transistor, T5, a fifth transistor, T6, a sixth transistor, T7, a seventh transistor, T8, an eighth transistor, C1, a first capacitor, C2, a second capacitor, cst1, a first storage capacitor, cst2, a second storage capacitor, cboost, a voltage stabilizing capacitor, R1, a first resistor, R2, a second resistor, U1, an AND gate, D1, a first diode, D2, a second diode, S, a data line, G and a scanning line;
t1, first time sequence, t2, second time sequence, t3, third time sequence, t4, fourth time sequence, t5, fifth time sequence, t6, sixth time sequence, t7, seventh time sequence, t8, eighth time sequence;
scan1, line Scan signal, vdata, data signal, vcom1, first common electrode voltage, vcom2, second common electrode voltage, EN, enable signal.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Example 1
In a first aspect of the embodiment of the present invention, as shown in fig. 1, a pixel unit 10 is provided, wherein the pixel unit 10 is arranged on an array substrate of a display panel 100 in an array manner, the array substrate further includes a plurality of Scan lines G, a plurality of data lines S and a common electrode terminal, the common electrode terminal has a first common electrode voltage Vcom1, each pixel unit 10 is respectively connected with a data line S and a Scan line G, the display panel 100 further includes a color film substrate disposed opposite to the array substrate and a liquid crystal layer disposed between the array substrate and the color film substrate, as shown in fig. 2, the pixel unit 10 includes a pixel electrode 11, the color film substrate is disposed with a color film layer and a common electrode layer, the common electrode layer has a second common electrode voltage Vcom2, the plurality of Scan lines G are used for inputting the line Scan signals Scan1 to the pixel units 10 of each line by line, and when the pixel units 10 of each line receive the line Scan signals Scan1, the data lines S output corresponding data signals Vdata to the pixel units 10 of the corresponding lines, the pixel units 10 of each line are connected to the corresponding lines, the pixel units 10 generate corresponding data signals Vdata to the pixel signals of the pixel units, and the pixel signals 10 of each line are driven by the pixel signals of the pixel units 10, and the pixel units generate corresponding pixel signals data signals and the pixel signals are corresponding to the pixel electrode data signals 11, and drive the pixel signals 2, and form a pixel electrode data signals.
In an alternative embodiment, the first common electrode voltage Vcom1 is equal to the second common electrode voltage Vcom2, for example, 5V, 8V, etc.
The line Scan signal Scan1 mainly refers to a line on signal, and the line off signal is opposite to the line on signal, and when scanning line by line, the plurality of Scan lines G sequentially receive the line on signal according to a corresponding timing sequence, and other lines not selected for scanning input the line off signal.
In order to reduce the power consumption of the pixel unit 10, in the present embodiment, the pixel unit 10 includes:
a pixel electrode 11;
A first storage capacitor Cst1;
A second storage capacitor Cst2;
the first switching circuit 12, the first input end of the first switching circuit 12 is connected with the first end of the first storage capacitor Cst1, the second input end of the first switching circuit 12, the second end of the first storage capacitor Cst1 and the first end of the second storage capacitor Cst2 are connected, the output end of the first switching circuit 12 is connected with the pixel electrode 11, and the first switching circuit 12 is triggered by a first level signal to be communicated with the first input end and the output end, or triggered by a second level signal to be communicated with the second input end and the output end;
The input end of the second switching circuit 13 is connected with the common electrode end, the first output end of the second switching circuit 13, the second end of the first storage capacitor Cst1 and the first end of the second storage capacitor Cst2 are connected, the second output end of the second switching circuit 13 is connected with the second end of the second storage capacitor Cst2, and the second switching circuit 13 is triggered by a first level signal to be communicated with the input end and the first output end or triggered by a second level signal to be communicated with the input end and the second output end;
The input end of the data switch 14 is connected with the data line S, the output end of the data switch 14, the first end of the first storage capacitor Cst1 and the second end of the second storage capacitor Cst2 are connected, and the data switch 14 is used for transmitting the data signal Vdata of the data line S every one frame and when receiving the row scanning signal Scan1 of the row;
The polarity switching circuit 15 is connected to the Scan line G, the first switching circuit 12, and the second switching circuit 13, respectively, and the polarity switching circuit 15 is configured to switch the polarity of the output level every time a line Scan signal Scan1 transmitted by the Scan line G is received.
In this embodiment, the first level signal and the second level signal are high and low level signals with opposite polarities.
As shown in fig. 3, it is assumed that in the first timing t1, when the pixel unit 10 of the current row receives the row Scan signal Scan1 in the ith frame, the polarity switching circuit 15 may switch and output a first level signal, at this time, the first switching circuit 12 switches and communicates the first input terminal and the output terminal of the first storage capacitor Cst1 with the pixel electrode 11, and the second switching circuit 13 switches and communicates the input terminal and the first output terminal of the first storage capacitor Cst1 with the second terminal of the first storage capacitor Cst1, the first common electrode voltage Vcom1 of the common electrode terminal is output to the second terminal of the first storage capacitor Cst1, meanwhile, the data switch 14 may receive the data signal Vdata in the row in the frame, and transmit the data signal Vdata to the first terminal of the first storage capacitor Cst1 and the second terminal of the second storage capacitor Cst2, the data signal Vdata charges the first storage capacitor Cst1 and the second storage capacitor Cst2, and the first common electrode voltage Vcom1 is output to the second terminal of the first storage capacitor Cst1 and the second terminal of the second storage capacitor Cst2, and the voltage difference between the first terminal and the first terminal of the second capacitor Cst2 is reached:
ΔV=Vdata-Vcom1;
Meanwhile, the data signal Vdata is output to the pixel electrode 11 through the first switching circuit 12, the voltage of the pixel electrode 11 is equal to the voltage of the data signal Vdata, that is, vdata, the voltage of the pixel electrode 11 and the second common electrode voltage Vcom2 form a first driving voltage of a first polarity, the first driving voltage is Vdata-Vcom2, for example, assuming that the first common electrode voltage Vcom1 and the second common electrode voltage Vcom2 are 8V, the data signal Vdata is 10V, and correspondingly, the first driving voltage is 2V.
In the second timing t2, when the current frame and the next line are scanned, the row no-line Scan signal Scan1 is input to the pixel unit 10 and the data switch 14, and accordingly, the data switch 14 outputs no data signal Vdata, the polarity switching circuit 15 maintains the output of the first level signal, and the voltage of the pixel electrode 11 is maintained at the voltage of the data signal Vdata.
In the third timing t3, when the pixel unit 10 switched to the i+1th frame and the current row receives the row Scan signal Scan1, since the data switch 14 outputs the data signal Vdata due to the interval frame, at this time, the data switch 14 outputs no data signal Vdata, the polarity switching circuit 15 switches the polarity of the output level, i.e., outputs the second level signal, after receiving the next row Scan signal Scan1, the second switching circuit 13 switches the input terminal and the second output terminal of the first common electrode voltage Vcom1 to the second terminal of the second storage capacitor Cst2, and the first switching circuit 12 switches the first terminal and the output terminal of the second storage capacitor Cst2 to the pixel electrode 11, at this time, the second storage capacitor Cst2 stores the voltage difference stored in the previous frame, the voltage at the first end of the second storage capacitor Cst2 and the voltage at the pixel electrode 11 are Vcom1- (Vdata-Vcom 1) =2vcom 1-Vdata, correspondingly, the voltage at the pixel electrode 11 and the voltage at the second common electrode Vcom2 form a second driving voltage with a second polarity, the second driving voltage is 2Vcom1-Vdata-Vcom2, and further, because Vcom 1=vcom 2, the second driving voltage is equal to Vcom2-Vdata, the second driving voltage and the first driving voltage are of opposite polarity, and the values are equal, so that polarity switching of driving signals is realized, for example, assuming that the first common electrode voltage Vcom1 and the second common electrode voltage Vcom2 are 8V, the data signal Vdata is 10V, correspondingly, the voltage at the first end of the second storage capacitor Cst2 and the voltage at the pixel electrode 11 are 6V, the second driving voltage is-2V, and 10V is 8V is positive with respect to the data signal ata with 8V being negative polarity, 6V is opposite to the data signal Vdata with 8V being negative polarity, the difference between them and the first common electrode voltage Vcom1 is equal.
In the adjacent frames, the first storage capacitor Cst1 and the second storage capacitor Cst2 simultaneously store the data signal Vdata with the same polarity, and when the polarities are switched, the first storage capacitor Cst1 and the second storage capacitor Cst2 do not have a large-amplitude polarity voltage charging and discharging process, so that the purpose of reducing power consumption is achieved.
In the fourth timing t4, when the pixel unit 10 of the current row does not receive the row Scan signal Scan1 and scans the next row, the polarity switching circuit 15 maintains the output of the second level signal, and at the same time, the data switch 14 outputs no data signal Vdata, and the voltage of the pixel electrode 11 is maintained at 2Vcom1-Vdata.
In the fifth timing t5, in the i+2 frame, the row Scan signal Scan1 is output to the pixel unit 10 of the current row for the third time, the polarity switching circuit 15 switches to output the first level signal, and the data switch 14 may output the data signal Vdata, that is, the pixel unit 10 in the fifth timing t5 repeats the operation state in the first timing t1, and outputs the reloaded data signal Vdata to the pixel electrode 11, wherein the polarity of the reloaded data signal Vdata is the same as the polarity of the data signal Vdata loaded in the i frame, that is, the polarity of the data line S connected to the pixel unit 10 may remain unchanged.
Also, in the sixth timing t6, when the row Scan signal Scan1 is scanned to the next row in the i+2 frame, the pixel unit 10 of the current row does not receive the row Scan signal Scan1, and the pixel unit 10 repeats the operation state in the second timing t2 in the sixth timing t6 and maintains the output of the reloaded data signal Vdata to the pixel electrode 11.
By providing the first switching circuit 12, the second switching circuit 13, and the polarity switching circuit 15, two adjacent frames can be realized as one frame cycle, and the polarity on the data line S can be kept unchanged during the frame scanning process, and the polarity of the driving voltage of the liquid crystal layer is switched during the frame cycle, so that the polarization of the liquid crystal layer is reduced, and the operational reliability of the liquid crystal layer is improved.
The first switching circuit 12, the second switching circuit 13, and the data switch 14 may be corresponding switching circuits, switching devices, etc., and the polarity switching circuit 15 may be a latch, a flip-flop, a logic gate, etc., and the specific structure is not limited.
Further, in order to maintain the output level of the polarity switching circuit 15 in each frame, in an alternative embodiment, as shown in fig. 2, the pixel unit 10 further includes a voltage stabilizing capacitor Cboost, a first end of the voltage stabilizing capacitor Cboost is connected to the output end of the polarity switching circuit 15, a second end of the voltage stabilizing capacitor Cboost is grounded, and the voltage stabilizing capacitor Cboost can be charged when the polarity switching circuit 15 outputs different levels, and maintain the continuous output of the first level signal or the second level signal in each frame.
Compared with the prior art, the pixel unit 10 has the advantages that the pixel unit 10 comprises the pixel electrode 11, the first storage capacitor Cst1, the second storage capacitor Cst2, the first switching circuit 12, the second switching circuit 13, the data switch 14 and the polarity switching circuit 15, in the previous frame, the pixel unit 10 can receive the row scanning signal Scan1 and the data signal Vdata, the polarity switching circuit 15 can switch and output the first level signal, at the moment, the data switch 14, the first switching circuit 12 and the second switching circuit 13 are correspondingly switched and output the data signal Vdata to the pixel electrode 11, in the next frame, the polarity switching circuit 15 switches and outputs the second level signal, the data switch 14 does not have the data signal Vdata to be output, and the first switching circuit 12 and the second switching circuit 13 switch and output the data signal Vdata with opposite polarities, at the moment, the pixel electrode 11 receives the data signal Vdata with the same polarity, the polarity is switched, in the two adjacent frames, the two storage capacitors store the data voltages with the same polarity, and the large voltage charge and discharge are avoided.
Example two
In an alternative embodiment, as shown in fig. 4, the first switching circuit 12 includes a first transistor T1 and a second transistor T2;
The first end of the first transistor T1 forms a first input end of the first switching circuit 12, the first end of the second transistor T2 forms a second input end of the first switching circuit 12, the second end of the first transistor T1 and the second end of the second transistor T2 form an output end of the first switching circuit 12, and the control end of the first transistor T1 and the control end of the second transistor T2 are connected to form a control end of the first switching circuit 12.
The second switching circuit 13 includes a third transistor T3 and a fourth transistor T4;
The first terminal of the third transistor T3 and the first terminal of the fourth transistor T4 are connected to form an input terminal of the second switching circuit 13, the second terminal of the third transistor T3 forms a first output terminal of the second switching circuit 13, and the second terminal of the fourth transistor T4 forms a second output terminal of the second switching circuit 13.
The data switch 14 includes a fifth transistor T5;
the first end of the fifth transistor T5 is connected to the data line S, the control end of the fifth transistor T5 is connected to the scan line G, and the second end of the fifth transistor T5 forms an output end of the data switch 14, and the data line S receives a data signal Vdata every one frame.
The polarity switching circuit 15 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first resistor R1, a first capacitor C1, a second capacitor C2, and an and gate U1;
The first input end of the AND gate U1 is connected with the scanning line G, the second input end of the AND gate U1, the first end of the first capacitor C1 and the first end of the eighth transistor T8 are connected, the output end of the AND gate U1 is connected with the first end of the sixth transistor T6, the second end of the sixth transistor T6 is connected with the control end of the seventh transistor T7, the control end of the eighth transistor T8 and the enabling signal end, the first end of the seventh transistor T7 is connected with the common electrode end, the second end of the seventh transistor T7, the first end of the first resistor R1, the second end of the eighth transistor T8 and the first end of the second capacitor C2 are connected to form the output end of the polarity switching circuit 15, the second end of the first resistor R1 is connected with the first end VDD1, and the second end of the first capacitor C1 and the second end of the second capacitor C2 are grounded to a positive voltage;
The enable signal terminal is used for inputting an enable signal EN, and the enable signal EN has the same phase as the row Scan signal Scan1 input by the Scan line G.
In this embodiment, as shown in fig. 5, it is assumed that in the first time sequence T1, when the pixel unit 10 of the current row receives the row Scan signal Scan1, the row Scan signal Scan1 is at a high level, the initial terminal voltage of the first capacitor C1 is at a low level, the and gate U1 outputs a low level, the enable signal EN is at a low level at the first time sequence T1, the sixth transistor T6 is turned on, the seventh transistor T7 and the eighth transistor T8 are turned off, at this time, the polarity switching circuit 15 switches and outputs a first level signal of a high potential, the first transistor T1 and the third transistor T3 are turned on, the second transistor T2 and the fourth transistor T4 are turned off, the first switching circuit 12 switches the first terminal of the first storage capacitor Cst1 to the pixel electrode 11, the first common electrode voltage Vcom1 is output to the second terminal of the first storage capacitor Cst1, simultaneously, the fifth transistor T5 can control the voltage difference between the first terminal of the first storage capacitor Cst1 and the second storage capacitor Cst2 of the first storage capacitor Cst1 and the second electrode 1, the first terminal of the first storage capacitor Cst2 and the second electrode voltage data signal data is triggered by the first voltage difference between the first terminal of the first capacitor Cst2 and the second electrode 1, the first terminal of the first voltage of the first storage capacitor Cst2 and the second voltage signal data is triggered by the first voltage difference between the first terminal of the first voltage and the first voltage of the first voltage capacitor Cst1 and the first voltage, and the first voltage of the first voltage capacitor electrode 1 is, and the first voltage is turned off.
ΔV=Vdata-Vcom1;
Meanwhile, the data signal Vdata is output to the pixel electrode 11 through the first switching circuit 12, the voltage of the pixel electrode 11 is equal to the voltage of the data signal Vdata, that is, vdata, the voltage of the pixel electrode 11 and the second common electrode voltage Vcom2 form a first driving voltage of a first polarity, and the first driving voltage is Vdata-Vcom2.
In the second timing T2, the enable signal EN is at a high level, the row Scan signal Scan1 is at a low level, the eighth transistor T8 is turned on, the polarity switching circuit 15 is maintained at a high level due to the presence of the second capacitor C2, the first transistor T1 and the third transistor T3 are turned on, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are turned off, the second capacitor C2 charges the first capacitor C1, and the terminal voltage of the first capacitor C1 is gradually increased to a high level.
In the third timing T3, when the pixel unit 10 switched to the i+1th frame and the current row receives the row Scan signal Scan1, since the data line S outputs the data signal Vdata at intervals, at this time, the data switch 14 outputs no data signal Vdata, the polarity switching circuit 15 outputs a high level to the gate U1 after receiving the next row Scan signal Scan1, the sixth transistor T6 is turned on, the eighth transistor T8 is turned off, the seventh transistor T7 receives a high level trigger on, the polarity switching circuit 15 switches a second level signal outputting a low level, the second transistor T2 and the fourth transistor T4 are turned on, the first transistor T1 and the third transistor T3 are turned off, the second switching circuit 13 switches an input terminal and a second output terminal communicating itself, and outputs the first common electrode voltage Vcom1 to the second terminal of the second storage capacitor Cst2, and the first switching circuit 12 switches the second input end and the output end of the second storage capacitor Cst2 to connect the first end of the second storage capacitor Cst2 with the pixel electrode 11, at this time, the second storage capacitor Cst2 stores the voltage difference stored in the previous frame, the voltage at the first end of the second storage capacitor Cst2 and the voltage at the pixel electrode 11 are Vcom1- (Vdata-Vcom 1) =2vcom 1-Vdata, correspondingly, the voltage at the pixel electrode 11 and the second common electrode voltage Vcom2 form a second driving voltage with a second polarity, the second driving voltage is 2Vcom1-Vdata-Vcom2, and further, since Vcom 1=vcom 2, the second driving voltage is equal to Vcom2-Vdata, the second driving voltage and the first driving voltage are opposite in polarity, and the values are equal, so that polarity switching of the driving signals is realized.
In the adjacent frames, the first storage capacitor Cst1 and the second storage capacitor Cst2 simultaneously store the data signal Vdata with the same polarity, and when the polarities are switched, the first storage capacitor Cst1 and the second storage capacitor Cst2 do not have a large-amplitude polarity voltage charging and discharging process, so that the purpose of reducing power consumption is achieved.
In the fourth timing T4, when the pixel unit 10 of the current row does not receive the row Scan signal Scan1 at the next frame and scans the next row, the polarity switching circuit 15 maintains to output the second level signal due to the presence of the second capacitor C2, and at the same time, the fifth transistor T5 outputs no data signal Vdata, and the voltage of the pixel electrode 11 is maintained at 2Vcom1-Vdata.
In the fifth timing T5, in the i+2 frame, the row Scan signal Scan1 is output to the pixel unit 10 of the current row for the third time, the polarity switching circuit 15 switches to output the first level signal, the fifth transistor T5 is triggered to be turned on, the data line S may output the data signal Vdata, the fifth transistor T5 may transmit the newly loaded data signal Vdata, that is, the pixel unit 10 in the fifth timing T5 repeats the operation state in the first timing T1 and outputs the reloaded data signal Vdata to the pixel electrode 11, and the reloaded data signal Vdata has the same polarity as the data signal Vdata loaded in the i frame, that is, the polarity of the data line S connected to the pixel unit 10 may remain unchanged.
Also, in the sixth timing t6, when the row Scan signal Scan1 is scanned to the next row in the i+2 frame, the pixel unit 10 of the current row does not receive the row Scan signal Scan1, and the pixel unit 10 repeats the operation state in the second timing t2 in the sixth timing t6 and maintains the output of the reloaded data signal Vdata to the pixel electrode 11.
By providing the first switching circuit 12, the second switching circuit 13, and the polarity switching circuit 15, two adjacent frames can be realized as one frame cycle, and the polarity on the data line S can be kept unchanged during the frame scanning process, and the polarity of the driving voltage of the liquid crystal layer is switched during the frame cycle, so that the polarization of the liquid crystal layer is reduced, and the operational reliability of the liquid crystal layer is improved.
The sixth transistor T6 and the eighth transistor T8 are transistors of opposite types, for example, the sixth transistor T6 is an N-channel transistor, the eighth transistor T8 is a P-channel transistor, or the sixth transistor T6 is a P-channel transistor, the eighth transistor T8 is an N-channel transistor, the seventh transistor T7 receives a high trigger on, and the seventh transistor T7 may be an N-channel transistor.
Correspondingly, according to the triggering manner of the level signal, the first transistor T1, the third transistor T3 and the fifth transistor T5 may be the same type of transistor, in an alternative embodiment, the first transistor T1, the third transistor T3 and the fifth transistor T5 may be N-channel transistors, the second transistor T2 and the fourth transistor T4 may be the same type of transistor, and the first transistor T1 and the second transistor T2 may be opposite type of transistors, in an alternative embodiment, the second transistor T2 and the fourth transistor T4 may be P-channel transistors.
Wherein, the and gate U1 may be a logic gate in a logic circuit, or may be a component, in an alternative embodiment, in order to simplify the circuit structure, as shown in fig. 6, the and gate U1 includes a first diode D1, a second diode D2, and a second resistor R2;
The cathode of the first diode D1 forms a first input end of the AND gate U1, the cathode of the second diode D2 forms a second input end of the AND gate U1, the anode of the first diode D1, the anode of the second diode D2 and the first end of the second resistor R2 are connected to form an output end of the AND gate U1, and the second end of the second resistor R2 is connected with the second positive voltage end VDD 2.
In this embodiment, in the previous frame, when the cathode of the first diode D1 inputs the row Scan signal Scan1, the first diode D1 is turned off, and the second diode D2 is turned on because the terminal voltage of the first capacitor C1 is at a low level, and the second diode D2 outputs low levels to the sixth transistor T6.
And in the previous frame, when the cathode of the first diode D1 does not input the row Scan signal Scan1 of the current row, the first diode D1 is turned on, the terminal voltage of the first capacitor C1 is at a high potential, the second diode D2 is turned on or off, and the first diode D1 outputs a low level.
And in the next frame, the row Scan signal Scan1 is input at the cathode of the first diode D1, and the terminal voltage of the first capacitor C1 is at a high level, at this time, the first diode D1 and the second diode D2 are turned off, and the and gate U1 outputs high levels to the sixth transistor T6, and by adopting the first diode D1 and the second diode D2 and the second resistor R2, the and gate U1 function can be realized, and the line structure is simplified.
The enable signal EN may use a clock signal, and the enable signal EN may have the same polarity or different polarity as the row Scan signal Scan1 input in the present row, for example, the sixth transistor T6 is adjusted to be an N-channel transistor, the eighth transistor T8 is adjusted to be a P-channel transistor, the sixth transistor T6 is turned on when the row Scan signal Scan1 is input in the present row, the eighth transistor T8 is turned off, and the sixth transistor T6 is turned off when the row Scan signal Scan1 is not input in the present row, i.e., when the row off signal is input.
Conversely, when the polarities are opposite, the sixth transistor T6 may be adjusted to be a P-channel transistor, the eighth transistor T8 may be adjusted to be an N-channel transistor, the sixth transistor T6 may be turned on when the row Scan signal Scan1 is input to the present row, the eighth transistor T8 may be turned off, and the sixth transistor T6 may be turned off when the row Scan signal Scan1 is not input to the present row.
In order to reduce the setting of the additional signal terminals, the circuit structures of the pixel unit 10 and the array substrate are simplified, in an alternative embodiment, the enable signal EN is opposite in polarity to the row Scan signal Scan1 input by the Scan line G, the enable signal EN is connected to the Scan line G connected to the next row of pixel units 10, the enable signal EN is input to the row Scan signal Scan1 input by the next row of Scan line G, when the Scan is performed to the present row, the row Scan signal Scan1 of the present row is at a high level, the row Scan signal Scan1 input by the next row of pixel units 10 is at a low level, and when the Scan is performed to the next row, the row Scan signal Scan1 of the present row is at a low level, the row Scan signal Scan1 input by the next row of pixel units 10 is at a high level, and the polarities of both are opposite in the same frame.
Example III
As shown in fig. 1, the second aspect of the embodiment of the present invention provides a display panel 100, where the display panel 100 includes a plurality of scan lines G, a plurality of data lines S and a plurality of pixel units 10, and the specific structure of the pixel units 10 refers to the foregoing embodiment, and since the display panel 100 adopts all the technical solutions of all the foregoing embodiments, at least all the beneficial effects caused by the technical solutions of the foregoing embodiments are not described herein in detail. The pixel unit 10 is respectively connected to a scan line G and a data line S.
The pixel units 10 are arranged on an array substrate of the display panel 100 in an array manner, the array substrate further comprises a plurality of scanning lines G, a plurality of data lines S and a common electrode terminal, the common electrode terminal is provided with a first common electrode voltage Vcom1, each pixel unit 10 is respectively connected with one data line S and one scanning line G, the display panel 100 further comprises a color film substrate opposite to the array substrate and a liquid crystal layer arranged between the array substrate and the color film substrate, as shown in fig. 2, the pixel units 10 comprise pixel electrodes 11, the color film substrate is provided with a color film layer and a common electrode layer, the common electrode layer is provided with a second common electrode voltage Vcom2, the plurality of scanning lines G are used for inputting a line scanning signal Scan1 to the pixel units 10 of each line row by row, when the pixel units 10 of each line receive the line scanning signal Scan1, the data lines S output corresponding data signals Vdata to the pixel units 10 of the corresponding line, the pixel units 10 generate corresponding voltage signals to the pixel electrodes 11 based on the received line scanning signals Scan1 and the data signals Vdata, the pixel units 10 are input to the pixel electrodes 11, the voltage signals are formed to the pixel electrodes 11, the voltage signals are matched with the second common electrode voltage signals and the pixel electrodes 10 are used for driving the liquid crystal layers, and the pixel electrodes 10 are correspondingly driven by the liquid crystal layers, and the pixel electrodes are driven by the liquid crystal layers.
In an alternative embodiment, the first common electrode voltage Vcom1 is equal to the second common electrode voltage Vcom2, for example, 5V, 8V, etc.
Example IV
As shown in fig. 7, the third aspect of the embodiment of the present invention provides a display device, which includes a driving circuit 200 of a display panel and the display panel 100, where the specific structure of the display panel 100 refers to the foregoing embodiment, and since the display device adopts all the technical solutions of all the foregoing embodiments, at least all the beneficial effects brought by the technical solutions of the foregoing embodiments are not described herein again. The display panel driving circuit 200 is connected to the display panel 100.
In this embodiment, the driving circuit 200 of the display panel may include a timing controller 230, a source driving circuit 210 and a gate driving circuit 220, where the timing controller 230 is used to control the gate driving circuit 220 to output the row Scan signal Scan1 to each row Scan line G row by row and control the source driving circuit 210 to output the data signal Vdata to each column data line S, and the timing controller 230 is further used to control the source driving circuit 210 to output the data signal Vdata every other frame, so that two adjacent frames can be implemented as one frame cycle, and the polarity on the data line S can be kept unchanged during the frame Scan, and the pixel unit 10 switches the polarity of the driving voltage of the liquid crystal layer in the frame cycle, so that the polarization of the liquid crystal layer is reduced and the working reliability of the liquid crystal layer is improved.
The foregoing embodiments are merely illustrative of the technical solutions of the present invention, and not restrictive, and although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that modifications may still be made to the technical solutions described in the foregoing embodiments or equivalent substitutions of some technical features thereof, and that such modifications or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A pixel cell, comprising:
A pixel electrode;
a first storage capacitor;
a second storage capacitor;
The first input end of the first switching circuit is connected with the first end of the first storage capacitor, the second input end of the first switching circuit, the second end of the first storage capacitor and the first end of the second storage capacitor are connected, the output end of the first switching circuit is connected with the pixel electrode, and the first switching circuit is triggered by a first level signal to be communicated with the first input end and the output end or triggered by a second level signal to be communicated with the second input end and the output end;
The input end of the second switching circuit is connected with the common electrode end, the first output end of the second switching circuit, the second end of the first storage capacitor and the first end of the second storage capacitor are connected, the second output end of the second switching circuit is connected with the second end of the second storage capacitor, and the second switching circuit is triggered by the first level signal to be communicated with the input end and the first output end or is triggered by the second level signal to be communicated with the input end and the second output end;
The input end of the data switch is connected with a data line, the output end of the data switch, the first end of the first storage capacitor and the second end of the second storage capacitor are connected, and the data switch is used for transmitting data signals of the data line when line scanning signals of the rows are received at intervals of one frame;
The polarity switching circuit is respectively connected with the scanning line, the first switching circuit and the second switching circuit and is used for switching the polarity of the output level when a row of scanning signals transmitted by the scanning line are received.
2. The pixel cell of claim 1, wherein the first switching circuit comprises a first transistor and a second transistor;
The first end of the first transistor forms a first input end of the first switching circuit, the first end of the second transistor forms a second input end of the first switching circuit, the second end of the first transistor and the second end of the second transistor form an output end of the first switching circuit, and the control end of the first transistor and the control end of the second transistor are connected to form a control end of the first switching circuit.
3. The pixel cell of claim 1, wherein the second switching circuit comprises a third transistor and a fourth transistor;
The first end of the third transistor and the first end of the fourth transistor are connected to form an input end of the second switching circuit, the second end of the third transistor forms a first output end of the second switching circuit, and the second end of the fourth transistor forms a second output end of the second switching circuit.
4. The pixel cell of claim 1, wherein the data switch comprises a fifth transistor;
The first end of the fifth transistor is connected with the data line, the control end of the fifth transistor is connected with the scanning line, the second end of the fifth transistor forms the output end of the data switch, and the data line receives one data signal every other frame.
5. The pixel cell of any one of claims 1-4, wherein the polarity switching circuit comprises a sixth transistor, a seventh transistor, an eighth transistor, a first resistor, a first capacitor, a second capacitor, and an and gate;
The first input end of the AND gate is connected with the scanning line, the second input end of the AND gate, the first end of the first capacitor and the first end of the eighth transistor are connected, the output end of the AND gate is connected with the first end of the sixth transistor, the second end of the sixth transistor is connected with the control end of the seventh transistor, the control end of the sixth transistor, the control end of the eighth transistor and the enabling signal end are connected, the first end of the seventh transistor is connected with the common electrode end, the second end of the seventh transistor, the first end of the first resistor, the second end of the eighth transistor and the first end of the second capacitor are connected to form the output end of the polarity switching circuit, the second end of the first resistor is connected with a first positive voltage end, and the second end of the first capacitor and the second end of the second capacitor are grounded;
The enabling signal end is used for inputting enabling signals, and the enabling signals are identical to the line scanning signals input by the scanning lines in phase.
6. The pixel cell of claim 5, wherein the and gate includes a first diode, a second diode, and a second resistor;
the cathode of the first diode forms a first input end of the AND gate, the cathode of the second diode forms a second input end of the AND gate, the anode of the first diode, the anode of the second diode and the first end of the second resistor are connected to form an output end of the AND gate, and the second end of the second resistor is connected with a second positive voltage end.
7. The pixel cell of claim 5, wherein the enable signal is of opposite polarity to a row scan signal input by the scan line, the enable signal terminal being connected to a scan line to which the pixel cell of a next row is connected.
8. The pixel cell of claim 1, further comprising a voltage stabilizing capacitor, wherein a first terminal of the voltage stabilizing capacitor is connected to the output terminal of the polarity switching circuit, and wherein a second terminal of the voltage stabilizing capacitor is grounded.
9. A display panel, comprising a plurality of scan lines, a plurality of data lines, and a plurality of pixel units according to any one of claims 1 to 8, wherein the pixel units are respectively connected to one of the scan lines and one of the data lines.
10. A display device comprising a drive circuit of a display panel and the display panel of claim 9, the drive circuit of the display panel being connected to the display panel.
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| CN202411933042.0A CN119360795A (en) | 2024-12-26 | 2024-12-26 | Pixel unit, display panel and display device |
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| CN202411933042.0A CN119360795A (en) | 2024-12-26 | 2024-12-26 | Pixel unit, display panel and display device |
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| JP2006343563A (en) * | 2005-06-09 | 2006-12-21 | Sharp Corp | Liquid crystal display device |
| JP2013101285A (en) * | 2011-11-10 | 2013-05-23 | Jvc Kenwood Corp | Liquid crystal display device |
| CN105632440A (en) * | 2016-01-12 | 2016-06-01 | 京东方科技集团股份有限公司 | Pixel circuit, driving method for the same, display panel |
| CN114495856A (en) * | 2022-01-29 | 2022-05-13 | 北京奕斯伟计算技术有限公司 | Pixel circuit, driving method thereof and display device |
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2024
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006343563A (en) * | 2005-06-09 | 2006-12-21 | Sharp Corp | Liquid crystal display device |
| JP2013101285A (en) * | 2011-11-10 | 2013-05-23 | Jvc Kenwood Corp | Liquid crystal display device |
| CN105632440A (en) * | 2016-01-12 | 2016-06-01 | 京东方科技集团股份有限公司 | Pixel circuit, driving method for the same, display panel |
| CN114495856A (en) * | 2022-01-29 | 2022-05-13 | 北京奕斯伟计算技术有限公司 | Pixel circuit, driving method thereof and display device |
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