JP2013003223A - Liquid crystal display device and method for driving same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a residual image (color-mixing) phenomenon, enabling improvement of the quality of displaying and the quality of motion video displaying.SOLUTION: Immediately after the pixel data of the entire screen is retained in transfer capacitors Ct of all pixels 14 in a pixel part, a transistor Tr3 is turned on by a reset voltage applied via a reset voltage controlling-wiring rst, and a black-side voltage supplied via a reset voltage setting-wiring rsv is supplied to a wiring capacitor Cp to be retained therein. After the period in which the black-side voltage is retained in the wiring capacitor Cp, the transistor Tr3 is turned off; within a period before the pixel data of the next screen are supplied to plural column-signal lines, a transistor Tr2 is turned on by a pixel selection signal supplied via a pixel selecting-signal wiring tri, so that the pixel data of the entire screen retained in the transfer capacitors Ct of all the pixels 14 in the pixel part are transferred to the wiring capacitor Cp in a lump to be retained therein and are also applied to pixel electrodes PE.

Description

  The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device used in a reflective liquid crystal projector device and the like and a driving method thereof.

  In recent years, a liquid crystal on silicon (LCOS) type liquid crystal display device is often used as a central part for projecting an image in a projector device or a projection television. In the display method of the liquid crystal display device such as LCOS, an analog video signal is conventionally input to a semiconductor element such as a CMOS (Complementary Metal Oxide Semiconductor), and the signal is held as it is on the pixel electrode of the liquid crystal display element for each pixel. A method of changing the orientation of the liquid crystal, a method of applying a video signal that has been subjected to pulse width modulation (PWM) by a digital signal to the pixel electrode of the liquid crystal display element, and driving by switching the orientation of the liquid crystal over time. is there. Many of these systems require three liquid crystal panels, and a color separation optical system and a color synthesis optical system are necessary. Therefore, conventionally, in order to realize a liquid crystal display device with a single plate, a liquid crystal display device that can write another signal while displaying one signal and switch it all over the screen has been proposed (for example, Patent Document 1).

  6 is an overall configuration diagram of an example of a conventional liquid crystal display device described in Patent Document 1, and FIG. 7 is a circuit diagram of an example of a pixel of the liquid crystal display device of FIG. The basic configuration is the same as that of an active matrix liquid crystal panel. In FIG. 6, the liquid crystal display device 20 includes a vertical shift register 21, a horizontal shift register 22, a pixel portion 23 in which a plurality of pixels are arranged in a matrix, and video switches h1 to hj.

  In the vertical shift register 21, k output terminals are separately connected to the k row selection lines G1 to Gk in the horizontal direction on a one-to-one basis, and are connected to the row scanning lines G1 to Gk in one horizontal scanning period cycle. Row selection signals are supplied sequentially from top to bottom. The horizontal shift register 22 sequentially supplies switching signals from the j output terminals to the gates of the video switches h1 to hj in synchronization with the horizontal shift clock. The video switches h1 to hj are composed of switching field effect transistors, their drains are connected in common to the horizontal signal lines vid, and their sources are one-to-one with the j column signal lines D1 to Dj in the vertical direction. Correspondingly connected separately. The pixel unit 23 is composed of a total of j × k pixels 24 arranged at intersections of the column signal lines D1 to Dj and the row scanning lines G1 to Gk, and the pixels 24 are arranged in a matrix as a whole. Yes.

  As shown in FIG. 7, the pixel 24 includes a transfer transistor Tr1, a pixel selection transistor Tr2, a transfer capacitor Ct, a pixel capacitor Cp, and a liquid crystal display element LC. The liquid crystal display element LC has a known structure in which a liquid crystal layer LCM is sealed in a space between a pixel electrode PE and a common electrode CE that are arranged to face each other. Each pixel 24 has a configuration in which one transfer transistor Tr1 and one transfer capacitor Ct are added in series. One end of the transfer capacitor Ct is connected to the connection point between the source of the transfer transistor Tr1 and the drain of the pixel selection transistor Tr2, and one end of the pixel capacitor Cp and the pixel electrode PE are connected to the source of the pixel selection transistor Tr2. Yes. Further, the gate of the transfer transistor Tr1 is connected to one row scanning line G corresponding to the pixel among the row scanning lines G1 to Gk. On the other hand, the gate of the pixel selection transistor Tr2 is connected to the wiring tri in common for all the pixels.

  Next, the operation of the conventional liquid crystal display device 20 will be described.

  First, the vertical shift register 21 outputs a row scanning signal only to the row scanning line G1, and thereby the j pixels 24 in the first row (first line) connected to the row scanning line G1 are simultaneously turned on. In this state, the horizontal shift register 22 operates, and the video switches h1, h2, h3,..., Hj are sequentially switched by switching signals output from the respective output terminals of the horizontal shift register 22 sequentially within one horizontal scanning period. Each pixel data (signal voltage) of the image data supplied from the signal line vid is sampled by the video switch turned on in accordance with that, and each column signal line D1, D2, D3,. , Dj are sequentially written. At this time, since the transfer transistor Tr1 shown in FIG. 7 in the j pixels 24 of the first row (first line) connected to the row scanning line G1 is turned on, Each pixel 24 writes each pixel data of the first line supplied via the column signal lines D1, D2, D3,..., Dj to the transfer capacitor Ct.

  Next, a row scanning signal is output from the vertical shift register 21 only to the row scanning line G2, whereby j pixels 24 in the second row (second line) connected to the row scanning line G2 are simultaneously turned on. . In this state, the horizontal shift register 22 operates, and in the same manner as in the operation of one line, the j pixels 24 in the second row (second line) connected to the row scanning line G2 are shown in FIG. Since the transfer transistor Tr1 is on, each pixel 24 on the second line is connected to each pixel on the second line supplied via the column signal lines D1, D2, D3,. Data is written to the transfer capacity Ct. Thereafter, the same operation as described above is repeated up to each pixel 24 in the k-th row (k-th line).

  In this way, when the pixel data is written to the transfer capacitors Ct in all the pixels 24 in the pixel unit 23, the output of the row scanning signals from the vertical shift register 21 to all the row scanning lines G1 to Gk is stopped. In addition, the signal on the signal line tri is set to the high level in a state where output of all the switching signals from the horizontal shift register 22 to h1 to hj is stopped. As a result, the pixel selection transistor Tr2 in each pixel 24 is turned on, and charge transfer is performed from the transfer capacitor Ct to the pixel capacitor Cp. The charge transferred and held in the pixel capacitor Cp is applied to the corresponding pixel electrode PE in the same pixel, and pixel data corresponding to the difference potential from the common electrode voltage Vcom applied to the common electrode CE is displayed on the liquid crystal display element. Displayed as LC. Since the signal on the signal line tri turns on the pixel selection transistors Tr2 in all the pixels 24 of the pixel portion 23, the pixel data is rewritten simultaneously on the entire screen.

  The liquid crystal display device 20 can write another image signal while displaying one image signal, and can switch the entire image simultaneously. Therefore, it is possible to perform a frame sequential operation, and it is possible to realize a single plate that displays the primary color signals of red (R), green (G), and blue (B) on one liquid crystal display device. In addition to miniaturization, weight reduction, cost reduction, and simplification of adjustment can be realized at the same time.

Japanese Patent Laid-Open No. 11-84419

  However, in the conventional liquid crystal display device 20 described above, an afterimage due to a residual transfer becomes a problem. In the liquid crystal display device 20, the holding voltage is transferred from the transfer capacitor Ct to the pixel capacitor Cp according to the capacitance ratio of the transfer capacitor Ct and the pixel capacitor Cp. There is no problem if the transfer capacity Ct is sufficiently larger than the pixel capacity Cp. However, if the capacity ratio between the transfer capacitor Ct and the pixel capacitor Cp is about 10: 1, the transfer from the transfer capacitor Ct is not performed completely, and a so-called transfer residue that is affected by the previous pixel voltage occurs. Accordingly, in the conventional liquid crystal display device 20, afterimages due to residual transfer and color mixing in the case of sequential RGB planes occur.

  The present invention has been made in view of the above points, and provides a liquid crystal display device capable of improving display quality by eliminating the afterimage (color mixing) phenomenon and improving the quality of moving image display, and a driving method thereof. Objective.

In order to achieve the above object, a liquid crystal display device according to the present invention includes a pixel unit in which pixels are arranged at each of a plurality of intersections where a plurality of column signal lines and a plurality of row scanning lines intersect, A plurality of video switches provided respectively corresponding to the column signal lines; a vertical driving means for outputting a row selection signal for sequentially selecting a plurality of row scanning lines one by one in units of one horizontal scanning period; Horizontal driving means for sequentially turning on the video switch within one horizontal scanning period, reset voltage setting wiring, reset voltage control wiring, and pixel selection signal commonly connected to all of the plurality of pixels in the pixel portion Wiring for each of the plurality of pixels in the pixel portion,
A liquid crystal display element having a structure in which a liquid crystal layer is sealed between a pixel electrode and a common electrode, a wiring capacitor having one end connected to the pixel electrode, a transfer capacitor for holding pixel data, and a plurality of column signal lines Connected to the corresponding column signal line and connected to the corresponding video switch among the plurality of video switches, and in the horizontal direction within a period controlled by the row selection signal output from the vertical driving means The corresponding video switch turned on by the signal output from the driving means and the transfer transistor for sampling and holding the pixel data supplied through the column signal line in the transfer capacitor, and the transfer capacitor in all the pixels in the pixel portion Immediately after the pixel data of the screen is held, it is turned on by the reset voltage applied via the reset voltage control wiring, and the reset voltage setting wiring is A reset transistor that supplies and holds the predetermined voltage supplied to the wiring capacitor and is applied to the pixel electrode, and after the period during which the predetermined voltage is held in the wiring capacitor, the reset transistor is turned off, and In the time before the pixel data of the next screen is supplied to the plurality of column signal lines, it is turned on by the pixel selection signal supplied via the pixel selection signal wiring and transferred within all the pixels in the pixel portion. It has a pixel selection transistor that collectively transfers and holds pixel data of the entire screen held in the capacitor to the wiring capacitor and applies it to the pixel electrode.

  In order to achieve the above object, according to the liquid crystal display device of the present invention, the pixel data supplied to the plurality of video switches has a higher level as the gradation value becomes larger at the minimum level at the minimum gradation value. The positive polarity pixel data that has the maximum level at the maximum gradation value, and the negative polarity that has the minimum level at the maximum gradation value, the level decreases as the gradation value increases at the maximum level at the minimum gradation value. Pixel data is alternately supplied for each frame (or field), and the common electrode voltage applied to the common electrode is driven at the same value when the positive pixel data and the negative pixel data have the same gradation value. The voltage is switched to a high level or a low level every frame (or field) so that a voltage is applied to the liquid crystal layer, and the predetermined voltage is a liquid crystal during a period in which positive pixel data is applied to a plurality of video switches. This is the voltage of the positive polarity pixel data at the time of the minimum gradation display of the display element, and the period of the negative polarity pixel data applied to the plurality of video switches is the voltage of the negative polarity pixel data at the time of minimum gradation display of the liquid crystal display element It is characterized by being.

  In order to achieve the above object, the liquid crystal display device of the present invention determines whether the brightness of the screen displayed by the pixel unit is brighter than a predetermined threshold based on the pixel data supplied to the plurality of video switches. Brightness detection means for detecting the image, and when the brightness detection means detects that the screen brightness is brighter than a predetermined threshold value, the positive pixel data is applied to a plurality of video switches with a predetermined voltage. The period of the positive polarity pixel data at the time of intermediate gradation display of the liquid crystal display element is used, and the negative polarity pixel data of the liquid crystal display element at the time of intermediate gradation display is the period during which the negative polarity pixel data is applied to the plurality of video switches. It is characterized by the above-mentioned voltage.

In order to achieve the above object, the liquid crystal display method of the present invention includes a pixel portion in which pixels are arranged at each of a plurality of intersections where a plurality of column signal lines and a plurality of row scanning lines intersect; A plurality of video switches provided respectively corresponding to a plurality of column signal lines; and a vertical driving means for outputting a row selection signal for sequentially selecting a plurality of row scanning lines one by one in units of one horizontal scanning period; Horizontal driving means for sequentially turning on a plurality of video switches within one horizontal scanning period, reset voltage setting wiring, reset voltage control wiring, and pixels commonly connected to all of the plurality of pixels in the pixel portion A selection signal wiring, and each of the plurality of pixels in the pixel portion includes:
A liquid crystal display element having a structure in which a liquid crystal layer is sealed between a pixel electrode and a common electrode, a wiring capacitor having one end connected to the pixel electrode, a transfer capacitor for holding pixel data, and a plurality of column signal lines Connected to the corresponding column signal line and connected to the corresponding video switch among the plurality of video switches, and for transferring the pixel data supplied through the corresponding video switch and the column signal line to the transfer capacitor by sampling. A transistor, a reset transistor that supplies and holds a predetermined voltage to the wiring capacitor and applies it to the pixel electrode, and a pixel that transfers and holds the pixel data held in the transfer capacitor to the wiring capacitor and applies it to the pixel electrode For a liquid crystal display device having a selection transistor,
The signal is supplied through the corresponding video switch and column signal line which are turned on by the signal output from the horizontal driving means within the period in which the transfer transistor is controlled to be turned on by the row selection signal output from the vertical driving means. A data holding step for sampling and holding the pixel data in the transfer capacity, and a transfer capacity in all pixels in the pixel unit are reset via the reset voltage control wiring immediately after holding the pixel data of the entire screen by the data holding step. A voltage is applied to the reset transistors in all the pixels in the pixel portion to turn them on, and the predetermined voltage from the reset voltage setting wiring is supplied to the wiring capacitance through the reset transistors that are turned on and is applied to the pixel electrodes. And a predetermined voltage is held in the wiring capacitance by the reset step. After the period, the reset transistor is turned off and the pixel selection transistor is selected via the pixel selection signal wiring within the time before the pixel data of the next screen is supplied to the plurality of column signal lines. A signal is supplied to turn on the pixel selection transistor, and the pixel data of the entire screen held in the transfer capacitor in all the pixels in the pixel portion is transferred to the wiring capacitor and held, and applied to the pixel electrode. And a step.

  According to the present invention, the display quality can be improved by eliminating the afterimage (color mixing) phenomenon, and the quality of the moving image display can be improved.

1 is an overall configuration diagram of an embodiment of a liquid crystal display device of the present invention. It is a circuit diagram of one embodiment of one pixel in the liquid crystal display device of the present invention. 3 is a timing chart illustrating the driving operation of FIGS. 1 and 2. It is a timing chart explaining operation | movement of other embodiment of the liquid crystal display device of this invention. It is a figure explaining an example of the relationship between the positive polarity and negative polarity pixel signal, and a common electrode voltage in the liquid crystal display device of this invention. It is a block diagram of an example of the conventional liquid crystal display device. It is a circuit diagram of an example of one pixel in the conventional liquid crystal display device.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is an overall configuration diagram of an embodiment of a liquid crystal display device according to the present invention, and FIG. 2 is a circuit diagram of an embodiment of a pixel of the liquid crystal display device according to the present invention. In FIG. 1 and FIG. 2, the same components as those in FIG. 6 and FIG. The basic structure of the liquid crystal display device of this embodiment is the same as that of an active matrix liquid crystal panel. In FIG. 1, a liquid crystal display device 10 according to the present embodiment includes a vertical shift register 11, a horizontal shift register 12, a pixel portion 13 in which a plurality of pixels are arranged in a matrix, and video switches h1 to hj. . The vertical shift register 11 constitutes the vertical driving means of the present invention, and the horizontal shift register 12 constitutes the horizontal driving means of the present invention.

  In the vertical shift register 11, k output terminals are separately connected to the k row selection lines G1 to Gk in the horizontal direction in a one-to-one correspondence, and are connected to the row scanning lines G1 to Gk in one horizontal scanning period cycle. Row selection signals are supplied sequentially from top to bottom. The horizontal shift register 12 sequentially supplies switching signals from the j output terminals to the gates of the video switches h1 to hj in synchronization with the horizontal shift clock. The video switches h1 to hj are composed of switching field effect transistors, their drains are connected in common to the horizontal signal lines vid, and their sources are one-to-one with the j column signal lines D1 to Dj in the vertical direction. Correspondingly connected separately.

  The pixel unit 13 is arranged at each intersection of the j column signal lines D1 to Dj and the k row selection lines G1 to Gk, so that a total of j × k pixels arranged in a matrix form. 14. Three wirings tri, rsv, and rst are commonly connected to all the pixels 14 in the pixel unit 13.

  As shown in the circuit diagram of FIG. 2, each pixel 14 has a configuration of a conventional pixel 24 including a transfer transistor Tr1, a pixel selection transistor Tr2, a transfer capacitor Ct, a pixel capacitor Cp, and a liquid crystal display element LC. In this configuration, a transistor Tr3 is added. The transfer transistor Tr1 has a gate connected to one row scanning line G corresponding to the pixel among the row scanning lines G1 to Gk, and a drain corresponding to one of the column signal lines D1 to Dj corresponding to the pixel. An N-channel MOS field effect transistor (hereinafter referred to as an NMOS transistor) is connected to the column signal line D and has a source connected to one end of the transfer capacitor Ct. The pixel selection transistor Tr2 has a gate connected to the pixel selection signal wiring tri, a drain connected to one end of the transfer capacitor Ct, and a source connected to one end of the pixel capacitor Cp and the pixel electrode PE of the liquid crystal display element LC. This is an NMOS transistor connected to.

  Further, the reset transistor Tr3 has a gate connected to the reset voltage control wiring rst, a drain connected to the reset voltage setting wiring rsv, and a source connected to one end of the pixel capacitor Cp and the pixel electrode PE of the liquid crystal display element LC. An NMOS transistor connected to the connection point. The liquid crystal display element LC has a known structure in which a liquid crystal layer LCM is sealed in a space between a pixel electrode PE and a common electrode CE that are arranged to face each other. When a constant voltage is applied to the liquid crystal layer LCM of the liquid crystal display element LC for a long time, problems such as liquid crystal burn-in occur. Therefore, as will be described later in this embodiment, for example, a common electrode voltage Vcom having a symmetrical square wave that is alternately inverted between a high level and a low level in a frame period is applied to the common electrode CE, and the pixel electrode PE is common. In synchronization with the inversion of the frame period of the electrode voltage Vcom, the liquid crystal display element LC is AC driven by applying pixel data that is alternately inverted between positive and negative in the frame period to the central potential of the common electrode voltage Vcom. To do.

  For example, as shown by I in FIG. 5, the positive polarity pixel data indicates black that is the minimum gradation value at the minimum value, white that is the maximum gradation value at the maximum value, and level This is data having a characteristic that the gradation value increases as (data value) increases. On the other hand, the negative pixel data is data obtained by inverting the value of the positive pixel data. For example, as indicated by II in FIG. 5, white is the maximum gradation value at the minimum value. The maximum value is black, which is the minimum gradation value, and the gradation value decreases as the level (data value) increases.

  In a frame period in which a voltage corresponding to positive pixel data is applied to the pixel electrode PE, a low level common electrode voltage Vcom + is applied to the common electrode CE, and a voltage corresponding to negative pixel data is applied to the pixel electrode PE. In the frame period in which is applied, a high level common electrode voltage Vcom− is applied to the common electrode CE. The liquid crystal display element LC performs gradation display according to the absolute value of the difference voltage between the applied voltage of the pixel electrode PE, which is a voltage applied to the liquid crystal layer LCM, and the common electrode voltage Vcom.

  The voltage applied to the liquid crystal layer LCM is a first difference voltage (la−Vcom +) between a voltage corresponding to positive pixel data (for example, la) in FIG. 5 and a low-level common electrode voltage Vcom + in a certain frame period. In the next one frame period, the second differential voltage (Vcom--lb) between the voltage corresponding to the negative pixel data (for example, lb in FIG. 5) and the high-level common electrode voltage Vcom-. . Therefore, although the application direction of the voltage applied to the liquid crystal layer LCM is alternately different in each frame, when pixel data of the same gradation is applied, as shown in FIG. 5, the absolute value A (= | la −Vcom + |) and the absolute value B (= | lb−Vcom |) of the second differential voltage have the same value, so that the same gradation is applied when positive pixel data is applied and when negative pixel data is applied. Can be displayed.

  Next, the operation of the liquid crystal display device 10 of the present embodiment will be described with reference to the timing chart of FIG.

  In the odd frame, which is an odd frame, as shown in FIG. 3A, a high-level row selection signal is supplied from the vertical shift register 11 to the row scanning line G1 of the first row for a period of time t1 to t2. As a result, the transfer transistor Tr1 in the j pixels 14 of the first line connected to the row scanning line G1 is turned on. In this state, the horizontal shift register 12 operates, and the video switches h1, h2, h3,..., Hj are switched by switching signals sequentially output from the output terminals of the horizontal shift register 12 within one horizontal scanning period. Each pixel data (signal voltage) of the image data of the first line that is sequentially turned on and supplied serially from the signal line vid is sampled by the video switch that is turned on, and each column signal line D1. , D2, D3,..., Dj are written in order. At this time, since the transfer transistor Tr1 in the j pixels 14 of the first line connected to the column signal lines D1, D2, D3,. Data is written to the transfer capacitor Ct through the transistor Tr1.

  Note that the pixel data supplied to the signal line vid is pixel data in which the gradation value monotonously increases in one line period as shown in FIG. 3C as an example, and is a positive pixel in the Odd frame. It is assumed to be data.

  Similarly, as shown in FIG. 3B, when a high-level row selection signal is supplied from the vertical shift register 11 to the x-th row scanning line Gx during the period from time t3 to t4, FIG. The pixel data (signal voltage) of the image data of the x-th line supplied serially from the signal line vid shown in FIG. 6 is sampled by the video switches h1 to hj that are turned on, and the column signal lines D1, D2, D3, ...,..., Are written into the transfer capacitor Ct through the turned-on transfer transistor Tr1 in the j pixels 14 of the x-th line connected to Dj. Similarly, the image of the kth line is transferred to the transfer capacitor Ct through the turned-on transfer transistor Tr1 in the j pixels 14 of the kth line connected to the last kth row scanning line Gk. Each pixel data (signal voltage) of data is written at time t5. That is, at time t5, the pixel data (signal voltage) of the odd frame is written to the transfer capacitors Ct of all the pixels 14 in the pixel unit 13, and the vertical shift register 11 and the horizontal shift register 12 are all turned off. It becomes.

  In this state, since a high level control voltage is applied to the reset voltage control wiring rst as shown in FIG. 3D for a short time immediately after time t5, all the pixels 14 in the pixel portion 13 are reset. The transistor Tr3 is turned on. At this time, as shown in FIG. 3F, the voltage bll supplied to the reset voltage setting wiring rsv is written into the pixel capacitor Cp through the drain / source of the transistor Tr3 which is turned on and simultaneously applied to the pixel electrode PE. Is done.

  Here, as shown in FIG. 5, the voltage bll is equal to the black signal voltage (hereinafter referred to as the low-side black signal voltage) which is the minimum gradation value of the positive pixel data. On the other hand, the common electrode voltage Vcom is switched to a low level (corresponding to Vcom + in FIG. 5) as shown in FIG. Therefore, after time t5, black is displayed on the entire screen by applying a driving voltage having an absolute value represented by | bll-Vcom + | to the liquid crystal layers LCM in all the pixels 14.

  After a period of time in this state, high-level pixel selection is performed on the pixel selection signal line tri as shown in FIG. 3E for a short time from time t6 immediately before the pixel writing start time t7 of the next Even frame. A signal is supplied. Thereby, the pixel selection transistors Tr2 in all the pixels 14 of the pixel unit 13 are simultaneously turned on, and the signal of the odd frame written in the transfer capacitors Ct in all the pixels 14 within the period from time t1 to time t5. The voltage (positive pixel data) is simultaneously transferred to the corresponding pixel capacitor Cp through the drain and source of the pixel selection transistor Tr2 that is turned on (that is, transferred in a lump) and held. Thereby, after time t6, the signal voltage (positive pixel data) of the Odd frame held in the pixel capacitor Cp is applied to each pixel electrode PE of the liquid crystal display element LC in all the pixels 14 of the pixel unit 13. At the same time, since the common electrode voltage Vcom (Vcom +) at the low level is commonly applied to the common electrode CE as shown in FIG. 3G, display by the signal voltage of the Odd frame for each pixel 14 is started. Is done.

  Subsequently, even-numbered pixels of even frames are written from time t7. As in the case of pixel writing in the odd frame, as shown in FIG. 3A, a high-level row selection signal is supplied from the vertical shift register 11 to the row scanning line G1 of the first row for a period of time t7 to t8. As a result, the transfer transistor Tr1 in the j pixels 14 of the first line connected to the row scanning line G1 is turned on. In this state, the horizontal shift register 12 operates, and the video switches h1, h2, h3,..., Hj are switched by switching signals sequentially output from the output terminals of the horizontal shift register 12 within one horizontal scanning period. Each pixel data (signal voltage) of the image data of the even frame of the first line that is sequentially turned on and supplied serially from the signal line vid is sampled by the video switch that is turned on, and is connected to each column. .., Dj are sequentially written to the signal lines D1, D2, D3,..., Dj, and further overwritten on the transfer capacitor Ct through the transfer transistor Tr1 in the j pixels 14 of the first line.

  Note that the pixel data supplied to the signal line vid during the period from time t7 to time t13 monotonically increases in one line period as shown in FIG. 3C as an example (the signal level monotonously decreases). It is assumed that the pixel data is negative polarity.

  Similarly, when a high-level row selection signal is supplied from the vertical shift register 11 to the x-th row scanning line Gx during the period from time t9 to t10 as shown in FIG. 3B, FIG. The pixel data (signal voltage) of the image data of the x-th line supplied serially from the signal line vid shown in FIG. 6 is sampled by the video switches h1 to hj that are turned on, and the column signal lines D1, D2, D3, ...,..., Are written into the transfer capacitor Ct through the turned-on transfer transistor Tr1 in the j pixels 14 of the x-th line connected to Dj. Similarly, the image of the kth line is transferred to the transfer capacitor Ct through the turned-on transfer transistor Tr1 in the j pixels 14 of the kth line connected to the last kth row scanning line Gk. Each pixel data (signal voltage) of data is written at time t11. That is, at time t11, the even frame pixel data (signal voltage) is written to the transfer capacitors Ct of all the pixels 14 in the pixel unit 13, and the vertical shift register 11 and the horizontal shift register 12 are all turned off. It becomes.

  In this state, since a high-level control voltage is applied to the reset voltage control wiring rst as shown in FIG. 3D for a short time immediately after time t11, all the pixels 14 in the pixel portion 13 are reset. The transistor Tr3 is turned on. At this time, as shown in FIG. 3F, the voltage blh supplied to the reset voltage setting wiring rsv is written into the pixel capacitor Cp through the drain / source of the transistor Tr3 which is turned on and simultaneously applied to the pixel electrode PE. Is done.

  Here, as shown in FIG. 5, the voltage blh is equal to a black signal voltage (hereinafter referred to as a high-side black signal voltage) which is the minimum gradation value of the negative pixel data. On the other hand, at time t11, as shown in FIG. 3G, the common electrode voltage Vcom is switched to a high level (corresponding to Vcom− in FIG. 5). Therefore, after time t11, black is displayed on the entire screen by applying the absolute value of the drive voltage represented by | blh−Vcom− | to the liquid crystal layers LCM in all the pixels 14.

  After a period of time in this state, high-level pixel selection is performed on the pixel selection signal line tri as shown in FIG. 3E for a short time from time t12 immediately before pixel writing start time t13 of the next Even frame. A signal is supplied. As a result, the pixel selection transistors Tr2 in all the pixels 14 of the pixel unit 13 are simultaneously turned on, and the Even frame signal written in the transfer capacitors Ct in all the pixels 14 within the period from time t7 to t11. The voltage (negative pixel data) is simultaneously transferred and held in the corresponding pixel capacitor Cp through the drain and source of the pixel selection transistor Tr2 that is turned on. Thereby, the signal voltage (negative pixel data) of the Even frame held in the pixel capacitor Cp is applied to each pixel electrode PE of the liquid crystal display element LC in all the pixels 14 of the pixel unit 13 after time t12. At the same time, as shown in FIG. 3G, a high level common electrode voltage Vcom (Vcom−) is commonly applied to the common electrode CE, so that display by the signal voltage of the Even frame for each pixel 14 is performed. Be started.

  As described above, according to the liquid crystal display device 10 of the present embodiment, the writing of the signal voltage of the odd frame or the even frame is started after the predetermined voltage is written in advance to the pixel capacitor Cp. The influence of the signal voltage of the frame on the pixel capacitance Cp can be eliminated. As a result, the afterimage (color mixture) phenomenon can be improved and the display quality can be improved.

  Further, in the present embodiment, the low-side black signal voltage bll and the high-side black signal voltage blh are set as the above-described predetermined voltage, so that the reset transistor Tr3 is turned on and the black signal voltage is written into the pixel capacitor Cp. The time from time t5 (t11) to time t6 (t12) when the pixel selection transistor Tr2 is turned on and signal voltage transfer to the pixel capacitor Cp is started can be black insertion. The video characteristics can be improved by inserting black.

  Next, another embodiment of the liquid crystal display device of the present invention will be described. The configuration of this embodiment is the same as that of FIGS. 1 and 2, but the voltage supplied to the reset voltage setting wiring rsv is different from the above embodiment. FIG. 4 is a timing chart for explaining the operation of another embodiment of the liquid crystal display device of the present invention. In the figure, the same parts as those in FIG.

  In the liquid crystal display device of this embodiment, at the time t21 shown in FIG. 4, the pixel data (signal voltage) of the odd frame is written in the transfer capacitors Ct of all the pixels 14 in the pixel portion 13, and the vertical display is performed. After all of the shift register 11 and the horizontal shift register 12 are turned off, a high-level control voltage is applied to the reset voltage control wiring rst as shown in FIG. 4D for a short time immediately after time t21. The reset transistors Tr3 of all the pixels 14 in the pixel unit 13 are turned on. At this time, as shown in FIG. 4F, the gray voltage grl supplied to the reset voltage setting wiring rsv is written into the pixel capacitor Cp through the drain / source of the transistor Tr3 which is turned on and simultaneously applied to the pixel electrode PE. Applied.

  Here, as shown in FIG. 5, the voltage grl is equal to a gray signal voltage (hereinafter referred to as a low-side gray signal voltage), which is an intermediate gradation value of positive pixel data. On the other hand, at time t21, as shown in FIG. 4G, the common electrode voltage Vcom is switched to a low level (corresponding to Vcom + in FIG. 5). Therefore, after time t21, gray is displayed on the entire screen by applying the absolute driving voltage represented by | grl−Vcom + | to the liquid crystal layers LCM in all the pixels 14.

  Also, at time t23 shown in FIG. 4, even-frame pixel data (signal voltage) is written in the transfer capacitors Ct of all the pixels 14 in the pixel unit 13, and the vertical shift register 11 and the horizontal shift register 12 4 are all turned off, for a short time immediately after time t23, a high-level control voltage is applied to the reset voltage control wiring rst as shown in FIG. The reset transistor Tr3 of the pixel 14 is turned on. At this time, as shown in FIG. 4F, the gray voltage grh supplied to the reset voltage setting wiring rsv is written into the pixel capacitor Cp through the drain / source of the transistor Tr3 which is turned on, and at the same time to the pixel electrode PE. Applied.

  Here, as shown in FIG. 5, the voltage grh is equal to a gray signal voltage (hereinafter referred to as a high-side gray signal voltage) which is an intermediate gradation value of negative pixel data. On the other hand, at time t23, as shown in FIG. 4G, the common electrode voltage Vcom is switched to a high level (corresponding to Vcom− in FIG. 5). Therefore, after time t23, the absolute value of the drive voltage represented by | grh−Vcom + | is applied to the liquid crystal layers LCM in all the pixels 14 to display gray on the entire screen.

  Thus, in this embodiment, the pixel transistor Cp is turned on by turning on the pixel selection transistor Tr2 from time t21 (t23) when the reset transistor Tr3 is turned on and the gray signal voltage grl (grh) is written to the pixel capacitor Cp. The time up to the time t22 (t24) when the signal voltage starts to be transferred can be gray inserted. In this embodiment, since gray display is performed instead of the black display period of the above-described embodiment, the brightness of the screen can be improved by gray display brighter than black display. According to the present embodiment, it is possible to brighten the entire screen while ensuring the improvement effect of the moving image characteristics.

  The liquid crystal display device of this embodiment is effective when the entire screen is bright. That is, the liquid crystal display device according to the present embodiment detects whether the brightness of the screen displayed by the pixel unit 13 is brighter than a predetermined threshold based on the pixel data supplied to the plurality of video switches h1 to hj. Brightness detecting means is further provided. As this brightness detection means, for example, an integrated value obtained by integrating the signal voltage of the frame supplied to the signal line vid is compared with an integrated value of the signal voltage of another frame obtained in the same manner. There is a way.

  The present invention is not limited to the above embodiment. For example, the common electrode voltage Vcom may be switched for each field or may be switched for each vertical scanning period. The circuit configuration of the pixel 14 is not limited to the configuration shown in FIG. 2, and the transistors Tr1 to Tr3 may be P-channel MOS field effect transistors (however, the GND wiring is a VDD wiring and the wiring rst, tri, rsv Must be reversed from that in FIGS. 3 and 4). Further, when the three primary color signals are displayed in the frame order, the same operation as that of the above embodiment may be performed three times within one frame, and in this case, a single-plate liquid crystal display device can be configured.

DESCRIPTION OF SYMBOLS 10 Liquid crystal display device 11 Vertical shift register 12 Horizontal shift register 13 Pixel part 14 Pixel G1-Gk, G line scanning line D1-Dj, D column signal line
vid Pixel data signal line
tri Pixel selection signal wiring
rsv Reset voltage setting wiring
rst Reset voltage control wiring
h1 to hj Video switch Tr1 Transfer transistor Tr2 Pixel selection transistor Tr3 Reset transistor Ct Transfer capacitance Cp Pixel capacitance LC Liquid crystal display element PE Pixel electrode CE Common electrode LCM Liquid crystal layer Vcom Common electrode voltage

Claims (4)

A pixel portion in which pixels are arranged in each of a plurality of intersections where a plurality of column signal lines and a plurality of row scanning lines intersect;
A plurality of video switches provided respectively corresponding to the plurality of column signal lines;
Vertical direction drive means for outputting a row selection signal for sequentially selecting the plurality of row scanning lines one by one in units of one horizontal scanning period;
Horizontal driving means for sequentially turning on the plurality of video switches within one horizontal scanning period;
A reset voltage setting wiring, a reset voltage control wiring, and a pixel selection signal wiring commonly connected to all of the plurality of pixels in the pixel portion;
Each of the plurality of pixels in the pixel unit includes:
A liquid crystal display element having a structure in which a liquid crystal layer is sealed between a pixel electrode and a common electrode;
A wiring capacitor having one end connected to the pixel electrode;
A transfer capacity for holding pixel data;
Connected to a corresponding column signal line among the plurality of column signal lines, and connected to a corresponding video switch among the plurality of video switches, according to the row selection signal output from the vertical direction driving means. For transfer that causes the transfer capacitor to sample and hold the corresponding video switch that is turned on by the signal output from the horizontal driving means and the column signal line within the period controlled to be turned on. A transistor,
Immediately after the pixel data of the entire screen is held in the transfer capacitors in all the pixels in the pixel unit, the pixel is turned on by the reset voltage applied through the reset voltage control wiring, and the reset voltage setting A reset transistor for supplying a predetermined voltage supplied via the wiring to the wiring capacitance and holding the same, and applying it to the pixel electrode;
After a period during which the predetermined voltage is held in the wiring capacitance, the reset transistor is turned off, and the pixel data of the next screen is supplied to the plurality of column signal lines within the time period. Turned on by a pixel selection signal supplied via a pixel selection signal wiring, and collectively transfers the pixel data of the entire screen held in the transfer capacitors in all the pixels in the pixel unit to the wiring capacitors A pixel selecting transistor that is held and applied to the pixel electrode;
A liquid crystal display device comprising: The pixel data supplied to the plurality of video switches is positive pixel data that has a maximum level when the gradation value is large at a minimum level at the minimum gradation value and a maximum level at the maximum gradation value. When the minimum gradation value is reached, the gradation level becomes larger as the gradation value becomes larger, and the level becomes smaller. When the maximum gradation value is reached, the negative polarity pixel data that becomes the minimum level is alternately supplied every frame (or field). And
The common electrode voltage applied to the common electrode is the one frame so that when the positive pixel data and the negative pixel data have the same gradation value, the same driving voltage is applied to the liquid crystal layer. Each (or field) can be switched to high or low level,
The predetermined voltage is a voltage of the positive pixel data at the time of minimum gradation display of the liquid crystal display element during a period in which the positive pixel data is applied to the plurality of video switches. 2. The liquid crystal display device according to claim 1, wherein a period during which the negative pixel data is applied is a voltage of the negative pixel data at the time of minimum gradation display of the liquid crystal display element. Brightness detection means for detecting whether the brightness of the screen displayed by the pixel unit is brighter than a predetermined threshold based on the pixel data supplied to the video switches;
When the brightness detection means detects that the screen brightness is brighter than the predetermined threshold, the liquid crystal display displays the predetermined voltage and the positive pixel data is applied to the plurality of video switches. The voltage of the positive polarity pixel data at the time of halftone display of the element is used, and the negative polarity pixel data at the time of halftone display of the liquid crystal display element is applied during the period when the negative polarity pixel data is applied to the plurality of video switches. The liquid crystal display device according to claim 2, wherein A pixel portion in which pixels are arranged in each of a plurality of intersections where a plurality of column signal lines and a plurality of row scanning lines intersect;
A plurality of video switches provided respectively corresponding to the plurality of column signal lines;
Vertical direction drive means for outputting a row selection signal for sequentially selecting the plurality of row scanning lines one by one in units of one horizontal scanning period;
Horizontal driving means for sequentially turning on the plurality of video switches within one horizontal scanning period;
A reset voltage setting wiring, a reset voltage control wiring, and a pixel selection signal wiring commonly connected to all of the plurality of pixels in the pixel portion;
Each of the plurality of pixels in the pixel unit includes:
A liquid crystal display element having a structure in which a liquid crystal layer is sealed between a pixel electrode and a common electrode;
A wiring capacitor having one end connected to the pixel electrode;
A transfer capacity for holding pixel data;
The plurality of column signal lines are connected to a corresponding column signal line, and are connected to a corresponding video switch among the plurality of video switches, and are supplied through the corresponding video switch and the column signal line. A transfer transistor for sampling and holding pixel data in the transfer capacitor;
A reset transistor for supplying and holding a predetermined voltage to the wiring capacitor and applying it to the pixel electrode;
For a liquid crystal display device having a pixel selection transistor that transfers and holds the pixel data held in the transfer capacitor to the wiring capacitor and applies it to the pixel electrode.
The corresponding video switch and the column that are turned on by the signal output from the horizontal driving means within a period in which the transfer transistor is controlled to be turned on by the row selection signal output from the vertical driving means. A data holding step for sampling and holding the pixel data supplied through the signal line in the transfer capacitor;
Immediately after holding the pixel data of the entire screen in the transfer capacity in all the pixels in the pixel unit by the data holding step, the reset voltage is applied to all the pixels in the pixel unit via the reset voltage control wiring. Applying to the reset transistor in the pixel to turn it on, supplying the predetermined voltage from the reset voltage setting wiring to the wiring capacitor through the reset transistor that has been turned on, and applying it to the pixel electrode A reset step,
After a period in which the predetermined voltage is held in the wiring capacitance by the reset step, the reset transistor is turned off, and before the pixel data of the next screen is supplied to the plurality of column signal lines In addition, a pixel selection signal is supplied to the pixel selection transistor via the pixel selection signal wiring to turn on the pixel selection transistor, and is held in the transfer capacitors in all the pixels in the pixel portion. And a transfer step of transferring and holding the pixel data of the entire screen to the wiring capacitor and applying the data to the pixel electrode.

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