JP2008306562A - Operation amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an operation amplifier which improves power source voltage removal ratios while assuring phase compensation characteristics, and therefore can be realized with a small-scale circuit and low power consumption. <P>SOLUTION: The operation amplifier comprises: a differential amplifier circuit 1; an output amplifier circuit 2 connected in series to the poststage of the differential amplifier circuit 1; a phase compensation circuit 3 for performing phase compensation of input/output characteristics; and a current supply circuit 5 for supplying an alternating current to this phase compensation circuit 3. Impedance of the current supply circuit 5 is equal to impedance of the phase compensation circuit 3. The phase compensation circuit 3 has a capacitor Cc1 and a resistor Rc1 connected in series. The current supply circuit 5 has a capacitor Cc2 and a resistor Rc2 connected in series. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an operational amplifier, and more particularly to an operational amplifier that improves a power supply voltage rejection ratio of an output.

Ideally, an operational amplifier used in a stabilized power supply circuit or the like has a constant output voltage without fluctuation even when noise is applied to the power supply voltage. Therefore, a power supply rejection ratio (Power Supply Rejection) that represents the attenuation amount of the power supply voltage noise in the output voltage.
It is desired that Ratio: PSRR) is high. Since the noise of the power supply voltage may have a high frequency component, it is required that the power supply voltage rejection ratio of the operational amplifier is maintained up to a high frequency.

FIG. 6 is a circuit example of an operational amplifier having a two-stage connection using a phase compensation circuit configured by connecting a resistor Rc1 and a capacitor Cc1 that are conventionally known.
This operational amplifier includes a differential amplifier circuit 1, an output amplifier circuit 2, and a phase compensation circuit 3. The differential amplifier circuit 1 includes NMOS transistors M1 and M2 to which differential signals NIN and PIN are input, PMOS transistors M3 and M4 forming a current mirror (active load), an NMOS transistor M5 functioning as a current source, It has. The output amplifier circuit 2 includes a PMOS transistor M6 and an NMOS transistor M7. The output terminal of the differential amplifier circuit 1 is connected to the input terminal of the output amplifier circuit 2. The phase compensation circuit 3 includes a resistor Rc1 and a capacitor Cc1 connected in series. One end of the phase compensation circuit 3 is connected to the node N1 and the other end is connected to the output terminal 4 of the output amplifier circuit 2.

FIG. 7 is an example of a constant voltage output circuit using the operational amplifier of FIG. This circuit amplifies the input voltage Vin with an amplification factor determined by the ratio of the resistors R1 and R2, and extracts the amplified voltage as the output voltage Vout. Here, RL is a load resistance.
FIG. 8 is a constant voltage output circuit in which the operational amplifier of FIG. 6 is applied as the operational amplifier of the constant voltage output circuit of FIG. Next, the operation of the circuit when the power supply voltage VDD changes will be described.

  First, when the power supply voltage VDD increases, the gate-source voltage Vgs of the MOS transistor M6 increases and the current flowing through the MOS transistor M6 increases, so that the output voltage Vout and the feedback voltage Vfb also increase. When the feedback voltage Vfb rises, the differential amplifier circuit 1 charges the current I1 to the capacitor Cc1, the potential of the node N1 rises, and the gate-source voltage Vgs of the MOS transistor M6 decreases. As a result, the gate-source voltage Vgs of the MOS transistor M1 becomes substantially equal to the magnitude before the power supply voltage VDD rises, and the output voltage Vout is also kept substantially constant.

Conversely, when the power supply voltage VDD decreases (decreases) and the gate-source voltage Vgs of the MOS transistor M6 decreases, the feedback voltage Vfb decreases and the potential of the node N1 decreases. As a result, the gate-source voltage Vgs of the MOS transistor M6 increases, and control is performed to keep the output voltage Vout constant.
Here, the ratio between the amount of change in the power supply voltage VDD and the amount of change in the output voltage Vout in the steady state is the power supply voltage rejection ratio (PSRRdc) at DC.

Next, the power supply voltage rejection ratio (PSRRac) when the power supply voltage VDD changes in an alternating manner in the circuit of FIG. 8 will be described.
In this case, the feedback voltage Vfb fluctuates according to the fluctuation of the power supply voltage VDD, and the differential amplifier circuit 1 supplies the current I1 to the capacitor Cc1, so that the node N1 follows the power supply voltage VDD and the MOS transistor M6 The control works so as to maintain the gate-source voltage Vgs. Since the node I1 follows the power supply voltage VDD, the current I1 to be supplied to the capacitor Cc1 is proportional to the fluctuating frequency of the power supply voltage VDD. Therefore, the feedback voltage Vfb necessary for supplying the current I1, that is, the output The fluctuation of the voltage Vout is also proportional to the frequency. Therefore, the AC power supply voltage rejection ratio (PSRRac) is a characteristic that deteriorates as the frequency increases.

  The frequency characteristic of the power supply voltage rejection ratio of the output voltage Vout in the circuit of FIG. 8 is the DC power supply voltage rejection ratio PSRRdc at a low frequency because the current to be supplied to the capacitor Cc1 is small, and is supplied to the capacitor Cc1 at a high frequency. Since it is determined by the power current, it is determined by the power supply voltage rejection ratio PSRRac at AC. Therefore, the power supply voltage rejection ratio has frequency characteristics as shown in FIG.

  The characteristics of FIG. 9 can be obtained by solving the small signal equivalent circuit of the circuit of FIG. 8 shown in FIG. In FIG. 10, for simplification, there is no Rc1 = 0 Ω and RL, and only the output impedance of the output amplifier circuit 2 is affected by fluctuations in the power supply voltage VDD. Further, since the fluctuation of the output voltage OUT is sufficiently small with respect to the fluctuation of the node N1, an approximation is used in which the output terminal 4 to which the capacitor Cc1 is connected is regarded as AC ground (AC ground). gm1 and gm2 are transfer conductances of the differential amplifier circuit 1 and the output amplifier circuit 2, respectively, and Ro1 and Ro2 are output impedances of the differential amplifier circuit 1 and the output amplifier circuit 2, respectively.

In the small signal equivalent circuit of FIG. 10, the expression (1) is established at the output terminal 4 by Kirchhoff's current law, and the expression (2) is established at the node N1.
gm2 × (VDD−Vn1) = (1 / Ro2) × (VDD−Vout) − {1 / (R1 + R2)} × Vout (1)
Vn1 = {Ro1 / (Ro1 × Cc1 × s + 1)} × gm1 × {R1 / (R1 + R2)} × Vout (2)
By substituting equation (2) into equation (1) and using an approximation that gm is sufficiently large with respect to 1 / Ro, the power supply voltage rejection ratio becomes equation (3), which shows the frequency characteristics of FIG. I understand.
VDD / Vout≈ {R1 / (R1 + R2)} × {(Ro1 × gm1) / (Ro1 × Cc1 × s + 1)} (3)

Incidentally, as a conventional technique for improving the power supply voltage rejection ratio at a high frequency, a stabilized power supply circuit described in Patent Document 1 described below is known (see FIG. 11).
As shown in FIG. 11, the stabilized power supply circuit includes a reference voltage generation circuit 11, two differential amplifiers 12, 13, a power supply fluctuation detection unit 14, an output voltage detection unit 15, and a PMOS transistor M30. A load 17 is connected between the terminal 16 and the power supply voltage VSS. The PMOS transistor M30 has a gate connected to the output terminal of the differential amplifier 13, a source connected to the power supply voltage VDD, and a drain connected to the output terminal 16.

  In such a stabilized power supply circuit, the output voltage detector 15 divides the output voltage Vout by a resistor and outputs the divided voltage to the differential amplifier 12. The differential amplifier 12 amplifies and outputs an error between the differential voltage and the reference voltage from the reference voltage generator 11. The output of the differential amplifier 12 is supplied to the inverting input terminal of the differential amplifier 13. The power supply fluctuation detecting unit 14 detects a fluctuation voltage of the gate-source voltage (Vgs) of the PMOS transistor M30 due to noise mixing in the power supply voltage VDD. In the differential amplifier 2, the error signal amplified by the differential amplifier 1 and the signal detected by the power supply fluctuation detector 14 are added and output as a gate signal of the PMOS transistor M30.

FIG. 12 shows a specific circuit configuration of the stabilized power supply circuit shown in FIG.
As shown in FIG. 12, the power supply fluctuation detection unit 14 includes a common source amplifier including a PMOS transistor M31 and a resistor R13. In FIG. 12, a diode-connected NMOS transistor M32 constitutes the constant voltage power source DCV of FIG. The PMOS transistor M30 and the PMOS transistor M31 constitute a current mirror, and a current proportional to the current flowing through the PMOS transistor M30 also flows through the PMOS transistor 31. The output voltage detection unit 15 and voltage dividing resistors R11 and R12 are included.

  In the stabilized power supply circuit configured as described above, when the power supply voltage VDD rises and the gate-source voltage Vgs of the PMOS transistor M31 increases, the current of the PMOS transistor M31 increases. The output voltage of the common source amplifier (power fluctuation detector 14) increases. As a result, the input voltage at the non-inverting input terminal of the differential amplifier 13 increases, and the gate-source voltage Vgs of the PMOS transistor M20 connected to the output of the differential amplifier 13 also increases.

Conversely, when the power supply voltage VDD decreases and the gate-source voltage Vgs of the PMOS transistor M31 decreases, the current of the PMOS transistor M31 decreases and the output of the common source amplifier also decreases. Accordingly, the gate-source voltage Vgs of the PMOS transistor M30 also decreases.
As a result, in the above-described stabilized power supply circuit, control is performed to keep the gate-source voltage Vgs of the PMOS transistor M30 constant, and an attempt is made to improve the power supply voltage rejection ratio in the high frequency range.
JP 2004-362250 A

  In the conventional operational amplifier of FIG. 6, when the power supply voltage rejection ratio at a high frequency is required, it is necessary to increase the power supply voltage rejection ratio PSRRac at AC. This power supply voltage rejection ratio PSRRac can be increased by increasing the transfer conductance of the differential amplifier circuit or by decreasing the capacitor of the phase compensation circuit. However, the measure for improving the power supply voltage rejection ratio PSRRac is limited by ensuring the stability by widening the frequency band of the operational amplifier.

In addition, in the circuit configurations of FIGS. 11 and 12, the circuit scale is increased by requiring two differential amplifiers. Further, since the pole is formed by the presence of the differential amplifier 13 having a certain gain in the loop, the phase compensation characteristic may be deteriorated.
In view of the above, an object of the present invention is to improve the power supply voltage rejection ratio while ensuring the phase compensation characteristic, and the operational amplifier is small in scale and can be realized with a low current consumption. Is to provide.

In order to solve the above-described problems and achieve the object of the present invention, each invention has the following configuration.
The invention according to claim 1 includes a differential amplifier circuit, an output amplifier circuit connected in series at a subsequent stage of the differential amplifier circuit, a connection point between the differential amplifier and the output amplifier circuit, and the output amplifier circuit. An operational amplifier including a phase compensation unit connected between the output terminal and performing phase compensation of input / output characteristics, connected between the connection point and a power supply voltage terminal, and connected to the phase compensation unit Current supply means for supplying current is provided.

The invention according to claim 2 is the invention according to claim 1, wherein the impedance of the current supply means is equal to the impedance of the phase compensation means.
According to a third aspect of the present invention, in the first aspect of the present invention, the circuit constituting the current supply means is equivalent to the circuit constituting the phase compensation means.
The invention according to claim 4 is the invention according to claims 1 to 3, wherein the phase compensation means includes a capacitor and a resistance means connected in series, and the current supply means is connected in series. It has a capacitor and a resistance means.

The invention according to claim 5 is the invention according to claim 4, wherein the resistance means is composed of a MOS transistor or a MOS transistor and a resistor.
According to a sixth aspect of the present invention, in the invention according to the fourth or fifth aspect, the current supply unit supplies an alternating current to the phase compensation unit in addition to the capacitor and the resistor connected in series. MOS transistors for forming are formed.

  According to the present invention, it is possible to improve the power supply voltage rejection ratio at the high frequency as well as the low frequency while ensuring the phase compensation characteristics, and the circuit for that can be realized with a small scale and low current consumption. it can.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
As shown in FIG. 1, the first embodiment of the operational amplifier according to the present invention includes a differential amplifier circuit 1, an output amplifier circuit 2 connected in series at the subsequent stage of the differential amplifier circuit 1, and input / output characteristics. And a current supply circuit 5 for supplying an alternating current to the phase compensation circuit 3.
That is, in the first embodiment, the current supply circuit 5 is added to the operational amplifier shown in FIG. 6, and the same phase compensation characteristic as that of the operational amplifier shown in FIG. 6 is secured, and the power supply voltage rejection ratio is further improved. It is what I did. The current supply circuit 5 for improving this circuit has a small circuit scale and can suppress current consumption.

As described above, the first embodiment is basically based on the configuration of the operational amplifier shown in FIG. 6, and therefore, parts having the same configuration are denoted by the same reference numerals and description thereof is omitted as much as possible.
As shown in FIG. 1, the current supply circuit 5 includes a node (connection point) N1, which is a part of a connection portion to which the differential amplifier 1 and the output amplifier circuit 2 are connected, and terminals (power supply voltages VDD and VSS). And an alternating current is supplied to the phase compensation circuit 3 as will be described later. Specifically, it includes NMOS transistors M11 and M12, a PMOS transistor M13, a capacitor Cc2, and a resistor Rc2.

  The NMOS transistors M11 and M12 are cascode-connected to constitute a bias current source, and this bias current source is connected between the node N1 and the terminal of the power supply voltage VSS. The PMOS transistor M13 is connected between the node N1 and the terminal of the power supply voltage VDD, and has a function of preventing the bias current flowing through the NMOS transistors M11 and M12 from being supplied from the differential amplifier circuit 1. The resistor Rc2 and the capacitor Cc2 form a series circuit, which is connected between the source of the NMOS transistor M11 and the terminal of the power supply voltage VDD. The series circuit is an equivalent circuit to the series circuit of the resistor Rc1 and the capacitor Cc1 constituting the phase compensation circuit 3. In other words, both series circuits are circuits having the same impedance.

The gates of the MOS transistors M11, M12, and M13 are supplied with a current source in which the MOS transistors M11 and M12 are configured by cascode connection and an appropriate bias voltage that allows the MOS transistor M13 to be regarded as a current source.
According to such a configuration, since the impedance when the drain of the MOS transistor M11 and the drain of the MOS transistor M13 are viewed from the output of the differential amplifier circuit 1 is relatively high, the phase compensation of the first embodiment of FIG. The characteristics are almost equal to those of the conventional circuit of FIG.

Next, a circuit operation with respect to power supply voltage fluctuation when the operational amplifier according to the first embodiment having such a configuration is applied to the constant voltage output circuit shown in FIG. 7 will be described.
In the first embodiment, basically, the current I1 flowing in the capacitor Cc1 in order to keep the gate-source voltage Vgs of the PMOS transistor M6 constant by changing the voltage of the node N1 according to the change of the power supply voltage VDD. Is supplied from the terminal of the power supply voltage VDD by a current I2 flowing through the resistor Rc2 and the capacitor Cc2. As a result, in the first embodiment, the current Idiff output from the differential amplifier circuit 1 can be reduced to improve the power supply voltage rejection ratio.

When the voltage at the node N1 fluctuates in accordance with the fluctuation in the power supply voltage VDD, the voltage at the node N1 fluctuates equal to the power supply voltage VDD in terms of alternating current (AC), the output voltage Vout is constant, and the AC ground. Can be considered. For this reason, the current I1 is substantially equal to the current that flows when the resistor Rc1 and the capacitor Cc1 are connected between the power supply voltage VDD and the AC ground.
On the other hand, the source of the cascode-connected NMOS transistor M11 can be regarded as a constant AC ground when the impedance is low and the power supply voltage VDD fluctuates. Therefore, the current I2 is substantially equal to the current that flows when the resistor Rc2 and the capacitor Cc2 are connected between the power supply voltage VDD and the AC ground.

  Therefore, when the series connection of the resistor Rc1 and the capacitor Cc1 has an impedance equivalent to the series connection of the resistor Rc2 and the capacitor Cc2, the current I1 and the current I2 are substantially equal. The current I2 is divided into a path flowing into the source of the NMOS transistor M11 and a path flowing into the drain of the NMOS transistor M12. However, since the impedance of the source of the NMOS transistor M11 is sufficiently smaller than the impedance of the drain of the NMOS transistor M12, most of the current I2 flows to the source side of the NMOS transistor M11.

  Accordingly, since the node N1 varies according to the variation of the power supply voltage VDD, the current Idiff to be supplied to the capacitor Cc1 by the differential amplifier circuit 1 is an impedance mismatch between the current path of the current I1 and the current path of the current I2. Therefore, the change in the differential input voltage for supplying the current Idiff, that is, the change in the output voltage can be reduced. Therefore, as shown in FIG. 2, the power supply voltage rejection ratio is a graph in which PSRRac in FIG. 9 is shifted to the right, and PSRR at a high frequency can be improved.

(Second Embodiment)
As shown in FIG. 3, the second embodiment according to the operational amplifier of the present invention includes a differential amplifier circuit 1, an output amplifier circuit 2, a phase compensation circuit 3a, and a current supply circuit 5a.
That is, the second embodiment is based on the configuration of the first embodiment shown in FIG. 1, and the phase compensation circuit 3 in FIG. 1 is replaced with the phase compensation circuit 3a in FIG. 3, and the current supply circuit 5 in FIG. Instead of the current supply circuit 5a of FIG.
Thus, since 2nd Embodiment is based on the structure of 1st Embodiment shown in FIG. 1, the same code | symbol is attached | subjected about the part which the structure is common, and description is abbreviate | omitted.

  The phase compensation circuit 3a is configured by a series circuit in which a PMOS transistor M14, a resistor Rc1, and a capacitor Cc1 are connected in series. One end of the series circuit is connected to the node N1, and the other end is the output terminal 4 of the output amplifier circuit 2. It is connected to the. That is, in the phase compensation circuit 3a, the resistor Rc1 of the phase compensation circuit 3 of FIG.

The current supply circuit 5a is based on the configuration of the current supply circuit 5 of FIG. 1, and a PMOS transistor M15 is further connected in series to the series circuit composed of the resistor Rc2 and the capacitor Cc2 of FIG. 1 to form a new series circuit. The series circuit was connected between the source of the NMOS transistor M11 and the terminal of the power supply voltage VDD. That is, the current supply circuit 5a replaces the resistor Rc2 of the current supply circuit 5 of FIG. 1 with a series connection of the on-resistance of the PMOS transistor M15 and the resistor Rc2, and achieves the same function as the current supply circuit 5.
Here, the series circuit of the phase compensation circuit 3a and the series circuit of the current supply circuit 5a are equivalent, and the impedances of both the series circuits are equal.
According to 2nd Embodiment which consists of such a structure, the effect similar to 1st Embodiment is realizable.

(Third embodiment)
As shown in FIG. 4, the third embodiment according to the operational amplifier of the present invention includes a differential amplifier circuit 1, an output amplifier circuit 2, a phase compensation circuit 3, and a current supply circuit 5b.
That is, the second embodiment is based on the configuration of the first embodiment shown in FIG. 1, and the current supply circuit 5 in FIG. 1 is replaced with the current supply circuit 5b in FIG.
As described above, the third embodiment is based on the configuration of the first embodiment shown in FIG. 1, and therefore, parts having the same configuration are denoted by the same reference numerals and description thereof is omitted.
The current supply circuit 5b is based on the configuration of the current supply circuit 5 of FIG. 1, and an operational amplifier AMP1 is added. The output terminal of the operational amplifier AMP1 was connected to the gate of the MOS transistor M11, and the source of the MOS transistor M11 was connected to the inverting input terminal of the operational amplifier AMP1. An appropriate bias voltage is supplied to the normal input terminal of the operational amplifier AMP1.

  With such a configuration, the impedance of the source of the MOS transistor M11 viewed from the current path of the current I2 is 1 / G when the gain of the operational amplifier AMP1 is G, compared to the case of the first embodiment of FIG. Becomes smaller. Thereby, the source of the MOS transistor M11 approaches the ideal AC ground, the difference between the current I1 and the current I2 can be reduced, and the power supply voltage rejection ratio can be improved.

(Fourth embodiment)
As shown in FIG. 5, the fourth embodiment according to the operational amplifier of the present invention includes a differential amplifier circuit 1a, an output amplifier circuit 2, a phase compensation circuit 3, and a current supply circuit 5.
That is, the fourth embodiment is based on the configuration of the first embodiment shown in FIG. 1, and the differential amplifier circuit 1 in FIG. 1 is replaced with the differential amplifier circuit 1a in FIG.
As described above, the fourth embodiment is based on the configuration of the first embodiment shown in FIG. 1, and therefore, parts having the same configuration are denoted by the same reference numerals and description thereof is omitted.
In the differential amplifier circuit 1a, the differential amplifier circuit 1 of FIG. 1 is changed to a folded cascode type, and the NMOS differential input is changed to a PMOS differential input.
Specifically, the differential amplifier circuit 1a includes PMOS transistors M18 to M24 and NMOS transistors M25 to M28 as shown in FIG.

(Other)
When the configuration of the first embodiment of FIG. 1 is compared with the conventional circuit of FIG. 6, a current supply circuit 5 is added, and the only elements increased with this are a resistor Rc2, a capacitor Cc2, and MOS transistors M11, M12, and M13. It is. This increase in circuit scale is smaller than the increase in the differential amplifier 13 and the like in the prior art in FIG. Regarding the current consumption, only the bias current flowing from the power supply voltage VDD to the power supply voltage VSS through the MOS transistors M13, M11, and M12 has increased, and the current of the differential amplifier circuit 1 and the like need not be increased.
Further, as in the second embodiment shown in FIG. 3, it is possible to easily improve the PSRR of any operational amplifier in which phase compensation is performed by the resistance and capacitance including the ON resistance of the MOS transistor.

1 is a circuit diagram showing a configuration of a first embodiment of an operational amplifier according to the present invention. It is a figure showing the frequency characteristic of the power supply voltage removal ratio of the constant voltage output at the time of applying 1st Embodiment to the constant voltage output circuit of FIG. It is a circuit diagram which shows the structure of 2nd Embodiment of the operational amplifier of this invention. It is a circuit diagram which shows the structure of 3rd Embodiment of the operational amplifier of this invention. It is a circuit diagram which shows the structure of 4th Embodiment of the operational amplifier of this invention. It is a circuit diagram which shows the structure of the conventional operational amplifier. It is a circuit diagram which shows the structure of the conventional constant voltage output circuit using an operational amplifier. FIG. 8 is a circuit diagram illustrating a configuration of a constant voltage output circuit in which the operational amplifier of FIG. 6 is applied to the circuit of FIG. 7. It is a figure showing the frequency characteristic of the power supply voltage removal ratio of the constant voltage output in the circuit of FIG. It is a figure showing the small signal equivalent circuit of the circuit of FIG. It is a block diagram of the circuit which improves the power supply voltage rejection ratio in the high region using the prior art. 12 is a specific circuit example of FIG. 11.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 1a Differential amplifier circuit 2 Output amplifier circuit 3 Phase compensation circuit 4 Output terminal 5, 5a, 5b Current supply circuit

Claims (6)

A differential amplifier circuit; an output amplifier circuit connected in series at a subsequent stage of the differential amplifier circuit; and a connection point between the differential amplifier and the output amplifier circuit and an output terminal of the output amplifier circuit. An operational amplifier comprising phase compensation means for performing phase compensation of input / output characteristics,
An operational amplifier comprising current supply means connected between the connection point and a power supply voltage terminal for supplying an alternating current to the phase compensation means.   2. The operational amplifier according to claim 1, wherein the impedance of the current supply means is equal to the impedance of the phase compensation means.   3. The operational amplifier according to claim 1, wherein the circuit constituting the current supply means is equivalent to the circuit constituting the phase compensation means. The phase compensation means has a capacitor and a resistance means connected in series,
The operational amplifier according to claim 1, wherein the current supply unit includes a capacitor and a resistor unit connected in series.   5. The operational amplifier according to claim 4, wherein the resistance means includes a MOS transistor or a MOS transistor and a resistor.   5. The current supply unit includes a MOS transistor for forming a path for supplying an alternating current to the phase compensation unit in addition to the capacitor and resistor connected in series. 5. The operational amplifier according to 5.

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