JP2011239154A - Operational amplifier circuit - Google Patents

Abstract

An operational amplifier circuit that can cope with a low power supply voltage and a low current consumption and achieves a high gain and a wide band.
A first-stage amplifying unit including a differential pair M1 and M2 that receives an input signal differentially and has low resistance loads R1 and R2, and an output signal output from an output terminal connected to the output of the first-stage amplifying unit. The first stage amplifier includes a transistor M19, M20 having one of the output pairs of the differential pair M1, M2 input to the gate and the drain connected to the output terminal. Signal path, an input stage including transistors M5 and M6 for inputting the other output pair of the differential pair to a gate, and an output stage including transistors M17 and M18 having drains connected to the output terminals. And a second signal path. Further, the next-stage amplifier includes a bias circuit that sets a bias current flowing through the transistors M19 and M20 in the first signal path and the transistors M5 and M6 in the second signal path.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to an operational amplifier circuit.

  4 is shown in FIG. It is a figure explaining the structure of the operational amplifier circuit which applied 2 step | paragraph class A / AB amplifier of 3 (c). Note that FIG. 3 (c) discloses a configuration of a PMOS differential pair in which M1 and M2 are pMOS transistors, and M3 and M4 are nMOS transistors, but in FIG. 4, they are nMOS differential pairs. In FIG. 4, FIG. The reference numerals and the like of the transistors in 3 (c) are appropriately changed.

  Referring to FIG. 4, in this operational amplifier circuit, an nMOS transistor M15 whose source is connected to GND (ground) and receives a bias voltage Vcmfb1 at its gate, a commonly connected source is connected to the drain of nMOS transistor M15, and its gate is The MOS transistor pair M1 and M2 connected to the differential input terminals Vin + and Vin−, respectively, the source is connected to the power supply VDD, the gate is commonly connected to the bias terminal Vb, and the drain is the drain of the nMOS transistors M1 and M2. PMOS transistors M3 and M4 (load transistors) respectively connected to the first and second amplifiers (input differential stage).

  The second-stage amplifier has two signal paths. The first signal path is led to the output terminal Vout− (Vout +) through the nMOS transistor M11 (M12). That is, the drain of the nMOS transistor M2 is connected to the gate of the nMOS transistor M11 whose source is connected to GND, and the drain of the nMOS transistor M11 is connected to Vout−. The drain of the nMOS transistor M1 is connected to the gate of the nMOS transistor M12 whose source is connected to GND, and the drain of the nMOS transistor M12 is connected to Vout +.

  The second signal path is led to the output terminal Vout− (Vout +) through the nMOS transistor M5 (M6) and the current mirror circuit by the pMOS transistors M7 and M9 (M8 and M10). That is, the drain of the nMOS transistor M1 is connected to the gate of the nMOS transistor M5 whose source is connected to GND, and the drain of the nMOS transistor M5 is the pMOS transistor M7 that forms the input terminal of the first current mirror circuit (M7, M9). And the drain of the pMOS transistor M9, which forms the output terminal of the first current mirror circuit (M7, M9), is connected to Vout−. The drain of the nMOS transistor M2 is connected to the gate of the nMOS transistor M6 whose source is connected to GND, and the drain of the nMOS transistor M6 is the pMOS transistor M8 that forms the input terminal of the second current mirror circuit (M8, M10). The drain of the pMOS transistor M10 connected to the drain of the current mirror circuit (M8, M10) and connected to the drain of the current mirror circuit (M8, M10) is connected to Vout +. NMOS transistors M13 and M14 that receive a bias voltage Vcmfb2 at their gates are connected between Vout− and GND and between Vout + and GND, respectively.

  The gate bias voltage Vcmfb1 of the nMOS transistor M15 is supplied from the output of the first common-mode feedback circuit (not shown) to set the common-mode voltage of the gate electrodes of the nMOS transistors M5 and M6, and the gates of the nMOS transistors M13 and M14 The bias voltage Vcmfb2 is supplied from the output of a second common-mode feedback circuit (not shown) in order to set the common-mode output voltage of the operational amplifier circuit.

  A series circuit of a capacitor C1 and a resistor R1 connected between the drain of the nMOS transistor M2, which is an output of the input differential stage, and the output terminal Vout−, and a capacitor C2 connected between the drain of the nMOS transistor M1 and the output terminal Vout +. And a series circuit of the resistor R2 is a phase compensation circuit.

  In FIG. 4, when the signal voltage at the input terminal is Vin +> Vin−, the gate-source voltage of the nMOS transistor M1 is larger than the gate-source voltage of the nMOS transistor M2, and the drain current of the nMOS transistor M1 is nMOS. The drain current of the transistor M2 becomes larger and the drain voltage of the nMOS transistor M1 becomes lower than the drain voltage of the nMOS transistor M2. As a result, the gate-source voltage of the nMOS transistor M5 becomes smaller than the gate-source voltage of the nMOS transistor M6, the drain current of the nMOS transistor M5 becomes smaller than the drain current of the nMOS transistor M6, and the first The drain current (charging current) of the pMOS transistor M9, which is the output current of the current mirror circuit, is smaller than the drain current (charging current) of the pMOS transistor M10, which is the output current of the second current mirror circuit.

  Since the drain voltage of the nMOS transistor M2 is higher than the drain voltage of the nMOS transistor M1, the drain current (discharge current) of the nMOS transistor M11 is larger than the drain current (discharge current) of the nMOS transistor M12. For this reason, the voltage of Vout− decreases and the voltage of Vout + increases.

  On the other hand, when Vin + <Vin−, the voltage of Vout− increases and the voltage of Vout + decreases.

  As a simulation result, when a 0.8 μm CMOS process is performed and the power supply voltage VDD is 1.8 V, a DC gain of 68 dB and a unity gain frequency of 24 MHz are obtained.

For example, Patent Document 1 proposes a configuration shown in FIG. 5 as an operational amplifier circuit capable of obtaining a wide band characteristic and a high DC gain and capable of operating at a low power supply voltage. Referring to FIG. 5, the gate electrode is connected to one of the differential input terminals, the source electrode is commonly connected to the first current source transistor (M26), and the drain electrode is connected to the first and second load resistors (R1). , R4), and a first differential amplifier circuit configured by first and second Nch transistors (M1, M4) connected to each other,
A gate electrode is connected to one of the differential input terminals, a source electrode is commonly connected to the second current source transistor (M27), and a drain electrode is connected to the third and fourth load resistors (R2, R3), respectively. A second differential amplifier circuit constituted by connected third and fourth Nch transistors (M2, M3);
A fifth Nch transistor (M5) having a source electrode connected to a reference potential (GND) and a gate electrode connected to a drain electrode of the first Nch transistor (M1), and a source electrode being the fifth Nch transistor A first cascode amplifier circuit configured by a sixth Nch transistor (M7) connected to the drain electrode of (M5);
A seventh Nch transistor (M6) having a source electrode connected to a reference potential (GND) and a gate electrode connected to a drain electrode of the second Nch transistor (M4); and a source electrode connected to the seventh Nch transistor A second cascode amplifier circuit constituted by an eighth Nch transistor (M8) connected to the drain electrode of (M6);
A first Pch transistor (a source electrode connected to the power supply potential (VDD)), a gate electrode connected to the drain electrode of the sixth Nch transistor (M7), and a drain electrode connected to one of the differential output terminals ( A first output amplifier circuit configured by M11);
A second Pch transistor (the source electrode is connected to the power supply potential (VDD)), the gate electrode is connected to the drain electrode of the eighth Nch transistor (M8), and the drain electrode is connected to the other of the differential output terminals ( A second output amplifier circuit configured by M12);
A ninth Nch transistor having a source electrode connected to a reference potential (GND), a gate electrode connected to the drain electrode of the fourth Nch transistor (M3), and a drain electrode connected to one of the differential output terminals A third output amplifier circuit configured by (M13);
A tenth Nch transistor having a source electrode connected to a reference potential (GND), a gate electrode connected to the drain electrode of the third Nch transistor (M2), and a drain electrode connected to the other of the differential output terminals A fourth output amplifier circuit configured by (M14), and the operating voltage of the first and second differential amplifier circuits is such that the drain electrode is connected to the power supply potential (VDD) and the gate electrode is intermediate Supplied from each source electrode of the first and second non-doped Nch transistors (M19 and M20) connected to the potential.

Japanese Patent Laying-Open No. 2005-210477

"A 1.8-V Digital-Audio Sigma-Delta Modulator in 0.8-μm CMOS", IEEE J. Solid-State Circuits, Vol. 32, No. 6, pp.783-796, 1997

  The analysis of related technology is given below.

  The operational amplifier circuit shown in FIG. 4 has the following problems.

(1) The first problem is that it is difficult to increase the bandwidth.

で与えられる。ただし、
ｇｍ１はｎＭＯＳトランジスタＭ１の相互コンダクタンス、
Ｃ１は位相補償容量である。 As shown in FIG. 4, the first and second signal paths are provided, and the output stage performs a push-pull operation. However, its frequency characteristics are the same as a normal two-stage amplifier. For this reason, it is difficult to increase the bandwidth. That is, in the circuit of FIG.
The unity gain frequency (× 2π) is

Given in. However,
gm1 is the mutual conductance of the nMOS transistor M1,
C1 is a phase compensation capacitor.

で与えられる。ただし、
ｇｍ１１はｎＭＯＳトランジスタＭ１１の相互コンダクタンス、
ＣＬはＶｏｕｔ−に接続する負荷容量（不図示）である。なお、図４において、ｐＭＯＳトランジスタＭ９の相互コンダクタンスｇｍ９はｎＭＯＳトランジスタＭ１１の相互コンダクタンスｇｍ１１に等しいものとする。 The secondary pole (p2) is

Given in. However,
gm11 is the mutual conductance of the nMOS transistor M11,
CL is a load capacity (not shown) connected to Vout−. In FIG. 4, it is assumed that the mutual conductance gm9 of the pMOS transistor M9 is equal to the mutual conductance gm11 of the nMOS transistor M11.

  In order to increase the unity gain frequency, not only the mutual conductance gm1 of the nMOS transistor M1, but also the gm11 of the nMOS transistor M11 is increased, and the secondary pole p2 needs to be widened (for example, the secondary pole p2 is changed to GB). (Gain Bandwidth Product: gain bandwidth product = open loop gain × primary pole)).

で与えられる。ただし、
μはキャリア（電子）の移動度、Ｃ_ＯＸは単位面積当りのゲート絶縁膜容量、Ｗはゲート幅、Ｌはゲート長（チャネル長）、Ｖ_ＧＳはゲート・ソース間電圧、Ｖ_ｔｈは閾値電圧である。 For this reason, an increase in current or an increase in size (gate width W) of the transistors (M1, M2, M11, M12, M9, M10) and the like is accompanied. That is, assuming that the transistor operates in the saturation region, the drain-to-source current I _DS is

Given in. However,
μ is the carrier (electron) mobility, C _OX is the gate insulating film capacitance per unit area, W is the gate width, L is the gate length (channel length), V _GS is the gate-source voltage, and V _th is the threshold voltage. It is.

The mutual conductance gm is expressed as follows.

In order to increase the transconductance gm of the transistor, it is necessary to increase at least one of the current I _DS flowing through the transistor and the gate width W.

  Further, widening the band by using the elimination of the secondary pole by the zero point compensation resistor R1 is not practical when considering element variations such as resistance in the semiconductor integrated circuit, temperature fluctuation, etc. (almost impossible to realize). is there).

(2) The second problem is that it is difficult to achieve both low voltage operation and high gain. The minimum operating voltage of the circuit of FIG. 4 is 0.9 V (= the sum of the gate-source voltage VGS of the nMOS transistor M11 and the saturation voltage of the pMOS transistor M4 (eg, 0.65 V + 0.25 V = 0.9 V)) Low voltage operation is possible.

  However, it is difficult to increase the gain without sacrificing low-voltage operation, such as using a cascode configuration for the first stage amplification stage or output stage.

  Accordingly, an object of the present invention is to provide an operational amplifier circuit which can cope with a low power supply voltage and a low current consumption and achieves a high gain and a wide band.

According to the present invention, a first-stage amplifier including a differential pair that receives an input signal differentially and has a resistive load;
A next-stage amplifier connected to the output of the first-stage amplifier and outputting an output signal from an output terminal; and
With
The next-stage amplifier is
A first signal path having a one-stage configuration including a transistor having a source connected to a first power supply, one of the output pairs of the differential pair being input to a gate, and a drain connected to the output terminal;
An input stage including a transistor having a source connected to the first power supply and inputting the other output pair of the differential pair to a gate; a transistor having a source connected to the second power supply and a drain connected to the output terminal An output stage including:
A second signal path comprising an amplifying stage having an input connected at a first node to the drain of the transistor in the input stage, and an output connected to the gate of the transistor at the output stage and a second node;
In addition,
Provided is an operational amplifier circuit including a bias circuit that sets at least a bias current flowing in the transistor of the first signal path and the transistor of the input stage of the second signal path to a predetermined value in the next stage amplification unit. Is done.

According to the present invention, the first stage amplifier, the next stage amplifier, and the bias circuit,
The first stage amplifier is
A first current source having one end connected to the first power source;
First and second resistance elements;
A source is commonly connected to the other end of the first current source, a gate is connected to each of the first and second input terminals forming a differential input, and a drain is connected to one end of the first and second resistance elements. Are respectively connected to the first and second transistors of the first conductivity type;
A second conductivity type third and fourth transistor having a source connected to a second power source, a drain connected to the drain of each of the first and second transistors, and a gate connected to each other;
With
The next-stage amplifier is
Fifth and sixth transistors of first conductivity type, each having a source connected to the first power supply and a gate connected to the drains of the first and second transistors;
A second conductivity type seventh and eighth transistor having a source connected to the second power source and a drain connected to first and second output terminals for differential output;
A source connected to the second power source, and a ninth transistor and an eleventh transistor of the second conductivity type constituting the first current mirror circuit with the seventh transistor;
A source connected to the second power supply; a tenth and a twelfth transistors of a second conductivity type forming a second current mirror circuit with the eighth transistor;
A second conductivity type thirteenth transistor having a source connected to the drain of the ninth transistor;
Fifteenth and seventeenth transistors of the first conductivity type cascode-connected between the first power source and the drain of the thirteenth transistor;
A fourteenth transistor of the second conductivity type having a source connected to the drain of the tenth transistor;
16th and 18th transistors of the first conductivity type cascode-connected between the first power supply and the drain of the 14th transistor;
A first conductivity type nineteenth having a source connected to the first power supply, a drain connected to each of the first and second output terminals, and a gate connected to the drain of each of the second and first transistors. And a twentieth transistor;
With
The drains of the fifth, ninth, and twelfth transistors and the source of the thirteenth transistor are connected in common,
The drains of the sixth, tenth and eleventh transistors and the source of the fifteenth transistor are connected in common,
The drain of the thirteenth transistor is connected to the gate of the ninth transistor;
The drain of the fourteenth transistor is connected to the gate of the tenth transistor;
The bias circuit comprises:
A first conductivity type twenty-first transistor having a source connected to the first power source;
A third resistor having one end connected to the drain of the twenty-first transistor;
A second current source connected between the other end of the third resistor and the second power source;
With
A gate of the twenty-first transistor is connected to the other end of the third resistor, and is further connected to a gate of a first conductivity type transistor forming the first current source;
An operational amplifier circuit is provided in which the other ends of the first and second resistance elements of the first stage amplifier are commonly connected to the drain of the twenty-first transistor.

  According to the present invention, it is possible to cope with a low power supply voltage and a low current consumption, and to realize an operational amplifier circuit having a high gain and a wide bandwidth.

It is a figure which shows the circuit structure of Example 1 of this invention. It is a figure explaining this invention. It is a figure which shows the circuit structure of Example 2 of this invention. It is a figure which shows the circuit structure of the related technique 1. It is a figure which shows the circuit structure of the related technique 2.

The operational amplifier circuit according to the present invention, in one of its preferred embodiments, includes a first stage amplifying unit including a differential pair (M1, M2) having a low resistance load (R1, R2) receiving an input signal differentially, And a next-stage amplification unit that is connected to the output of the first-stage amplification unit and outputs an output signal from an output terminal.
The next stage amplifying unit includes a transistor M19 (source connected to a first power source (GND)), one of the output pairs of the differential pair (M1, M2) input to the gate, and a drain connected to the output terminal. A first signal path having a single-stage configuration including M20) and an input including a transistor M5 (M6) having a source connected to the first power supply (GND) and inputting the other of the output pair of the differential pair to the gate An output stage including a transistor M17 (M18) having a source connected to a second power supply and a drain connected to the output terminal; a drain of the transistor M5 (M6) in the input stage; and a first node N1 A second signal path having an intermediate stage with an input connected at (N2) and an output connected at the gate of the transistor M17 (M18) of the output stage and a second node N3 (N4). ing Further, in the next stage amplification section, at least a bias current flowing through the transistor 19 (M20) of the first signal path and the transistor M5 (M6) of the input stage of the second signal path is set to a predetermined value. And a bias circuit (transistor M24, resistor R3, current source Ib).

  In the present invention, the intermediate stage includes a grounded gate connected between the first node N1 (N2) and the second node N3 (N4) (the gate is grounded in an AC manner, that is, the gate is in an AC manner). A load circuit (active load circuit) including an active element connected between a transistor M13 (M14) connected to a voltage that does not change, the second node N3 (N4), and the first power supply (GND). I have.

  In the present invention, the active load circuit that forms an intermediate stage together with the common-gate transistor M13 (M14) includes a plurality of stages of transistors that are cascode-connected between the second node N3 (N4) and the first power supply (GND). The cascode circuit (M9, M11) ((M10, M12)) is provided.

  Alternatively, in the present invention, the active load circuit constituting the intermediate stage together with the common-gate transistor M13 (M14) is a gain / boost circuit connected between the second node N3 (N4) and the first power supply (GND). It is good also as a structure provided with. In the present invention, the gain / boost circuit inputs a resistance element R6 (R7) having one end connected to the first power supply (GND), a terminal voltage of the resistance element R6 (R7), and a predetermined reference voltage. A gain boost amplifier M25 (M26), a source connected to the other end of the resistor element R6 (R7), a drain connected to the second node N3 (N4), and a gain boost amplifier M25. A transistor M33 (M34) having a gate connected to the output of (M26). The gain boost amplifier M25 (M26) may include a circuit (transistor M31 (M32)) for level-shifting the terminal voltage of the resistor element R6 (R7).

  The operational amplifier circuit according to the present invention includes, in one of its preferable aspects, a first stage amplifying unit, a next stage amplifying unit, and a bias circuit, and the first stage amplifying unit is connected to a first power source (GND) at one end. Current source (M23), the first and second resistance elements (R1, R2), and the other end of the first current source (M23) are connected in common to the first and First conductivity type first and second terminals each having a gate connected to a second input terminal (Vin +, Vin−) and a drain connected to one end of each of the first and second resistance elements (R1, R2). The source is connected to the second transistor (M1, M2) and the second power supply (VDD), the drain is connected to the drain of each of the first and second transistors (M1, M2), and the gates are connected to each other. Second and third conductivity types And a transistor (M3, M4).

The next-stage amplifying unit has fifth and fifth first conductivity types in which a source is connected to the first power supply (GND) and a gate is connected to the drains of the first and second transistors (M1 and M2). 6 transistors (M5, M6) and the second power source (VDD) are connected to the source, and the first and second output terminals (Vout−, Vout +) forming the differential outputs are connected to the drains. A source is connected to the conductive type seventh and eighth transistors (M17, M18) and the second power supply (VDD), and the seventh transistor (M17) and the second current mirror circuit constituting the first current mirror circuit. Conductive ninth and eleventh transistors (M15, M7);
A source connected to the second power supply (VDD), and a tenth and twelfth transistors (M16, M8) of the second conductivity type constituting a second current mirror circuit with the eighth transistor (M18);
A thirteenth transistor (M13) of the second conductivity type having a source connected to the drain of the ninth transistor (M15);
Fifteenth and seventeenth transistors (M9, M11) of the first conductivity type cascode-connected between the first power supply (GND) and the drain of the thirteenth transistor (M13);
A fourteenth transistor (M14) of the second conductivity type having a source connected to the drain of the tenth transistor (M16);
Sixteenth and eighteenth transistors (M10, M12) of the first conductivity type cascode-connected between the drain of the first power supply (GND) and the fourteenth transistor (M14);
A source is connected to the first power supply (GND), drains are connected to the first and second output terminals (Vout−, Vout +), and drains of the second and first transistors (M2, M1). And 19th and 20th transistors (M19, M20) of the first conductivity type each having a gate connected thereto,
The drains of the fifth, ninth, and twelfth transistors (M5, M15, and M8) and the source of the thirteenth transistor (M13) are connected in common, and the sixth, tenth, and eleventh transistors (M6) , M7, M16) and the source of the fifteenth transistor (M14) are connected in common. The drain of the thirteenth transistor (M13) is connected to the gate of the ninth transistor (M15), and the drain of the fourteenth transistor (M14) is the gate of the tenth transistor (M16). It is connected to the.

  The bias circuit includes a first conductivity type 21st transistor (M24) having a source connected to the first power supply (GND) and a third end having one end connected to the drain of the 21st transistor (M24). A resistor (R3); and a second current source (Ib) connected between the other end of the third resistor (R3) and the second power supply (VDD). The gate of the twenty-first transistor (M24) is connected to the other end of the third resistor (R3), and is further connected to the gate of the first conductivity type transistor forming the first current source (M23). The other ends of the first and second resistance elements (R1, R2) of the first stage amplifier are commonly connected to the drain of the twenty-first transistor (M24). In the following, description will be made in accordance with examples.

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention. Referring to FIG. 1, in the operational amplifier circuit of this embodiment, the nMOS transistor M23 whose source is connected to GND, the commonly connected source is connected to the drain of the nMOS transistor M23, and the gates are connected to the terminals Vin + and Vin−. NMOS transistors M1, M2 connected and having drains connected to one ends of resistors R1, R2, respectively;
The pMOS transistors M3 and M4, whose source is connected to the power supply VDD, whose gate is connected to the bias terminal Vb1, and whose drains are connected to the drains of the nMOS transistors M1 and M2, respectively, constitute an initial stage amplification unit. The resistors (load resistors) R1 and R2 have values sufficiently lower than the output resistance values of the pMOS transistors M3 and M4. The other ends of the resistors R1 and R2 are connected in common and connected to the drain of an nMOS transistor M24 described later.

  The next stage amplifier has two signal paths. The first signal path is led to the output terminal Vout− (Vout +) through the nMOS transistor M19 (M20). That is, the drain of the nMOS transistor M2 is connected to the gate of the nMOS transistor M19 whose source is connected to GND, and the drain of the nMOS transistor M19 is connected to Vout−. The drain of the nMOS transistor M1 is connected to the gate of the nMOS transistor M20 whose source is connected to GND, and the drain of the nMOS transistor M20 is connected to Vout +.

  The second signal path is input to the cascode circuit by the pMOS transistor M8, the nMOS transistors M9, M11, and the pMOS transistors M13, M15 (M7, M10, M12, M14, M16) through the nMOS transistor M5 (M6), and finally The output terminal Vout− (Vout +) is led through the pMOS transistor M17 (M18). That is, the drain of the nMOS transistor M1 is connected to the gate of the nMOS transistor M5 whose source is connected to GND, and the drain of the nMOS transistor M5 is connected to the drains of the pMOS transistors M8 and M15 whose source is connected to the power supply VDD. . A pMOS transistor M13 and nMOS transistors M11 and M9 are connected between the connection point of the drains of the transistors M5, M8 and M15 and GND, the drain of the transistor M13 is connected to the gate of the transistor M15, and a bias voltage Vb2 is supplied to the gate. The bias voltages Vb3 and Vb4 are supplied to the gates of the nMOS transistors M11 and M9, respectively. Further, a pMOS transistor M17 having a source connected to the power supply VDD, a gate connected to the gate of the pMOS transistor M17, and a drain connected to Vout− is provided.

  The drain of the nMOS transistor M2 is connected to the gate of the nMOS transistor M6 whose source is connected to GND, and the drain of the nMOS transistor M6 is connected to the drains of the pMOS transistors M7 and M16 whose source is connected to the power supply VDD. A pMOS transistor M14 and nMOS transistors M12 and M10 are connected between the connection point of the drains of the transistors M6, M7 and M16 and GND, the drain of the transistor M14 is connected to the gate of the transistor M16, and the gate of the pMOS transistor M14 is biased. The voltage Vb2 is supplied, and bias voltages Vb3 and Vb4 are supplied to the gates of the nMOS transistors M12 and M10, respectively. Further, a pMOS transistor M18 having a source connected to the power supply VDD, a gate connected to the gate of the pMOS transistor M16, and a drain connected to Vout + is provided. An nMOS transistor M21 that receives a bias voltage Vcmfb at its gate is provided between Vout− and GND, and an nMOS transistor M22 that receives a bias voltage Vcmfb at its gate is provided between Vout + and GND.

A constant current source Ib, a resistor R3, and an nMOS transistor M24 are provided between the power supply and GND.
A connection node between one end of the resistor R3 and the drain of the transistor M24 is connected to a connection point between the resistors R1 and R2. The other end of the resistor R3 is connected to the gates of the nMOS transistors M24 and M23.

  The gate electrodes of the nMOS transistors M21 and M22 are connected to a common-mode feedback circuit (not shown) in order to set the common-mode output voltage of the operational amplifier circuit.

  The gate potentials of the nMOS transistors M5 (M6) and M19 (M20) are determined by the drain currents of the pMOS transistors M3 (M4) and M23 and the resistance value of R1 (R2), the nMOS transistors M24, the resistor R3, and the constant current source Ib. By appropriately setting various constants of the configured bias circuit, it matches the generated voltage VA of the bias circuit. As a result, the bias currents of the nMOS transistors M5, M6, M19, and M20 are fixed.

  The drains of the pMOS transistor M15 (M16) and the pMOS transistor M8 (M7) are connected to each other to detect the common-mode current.

  Further, the value of the common-mode current is determined by the local feedback in which the drain electrode of the pMOS transistor M13 (M14) is connected to the gate electrodes of M15 (M16) and M7 (M8), and the drains of M5 (M6) and M9 (M10). It corresponds to the sum of currents.

  Therefore, the bias current of M17 (M18) is fixed.

  A capacitor C1 connected between the drain and gate of the pMOS transistor M17 and a capacitor C2 connected between the drain and gate of the pMOS transistor M18 are phase compensation capacitors.

  Next, in this embodiment, a solution to the problem of the related art described above will be described.

<Broadband>
In the related art shown in FIG. 4, both the first and second signal paths from the input terminal to the output terminal have a two-stage amplification configuration.

  On the other hand, in the present embodiment, the gain of the first stage amplifier is kept low by using low resistance loads (R1, R2).

  Therefore, the first signal path can be regarded as one-stage amplification, and the second signal path can be regarded as two-stage amplification.

  According to the present embodiment, such a configuration eliminates the secondary pole generated at the output terminal as a comprehensive characteristic, and greatly improves the phase margin. As a result, it is possible to increase the bandwidth.

  Incidentally, the unity gain frequency (× 2π) is given by the following equation.

gm1 / gm19 / R1 / (C1 + CL)
However, gm1 and gm19 are transconductances of the transistors M1 and M19,
R1 is the resistance value of the resistor R1,
C1 is a capacitance value of the phase compensation capacitor C1,
CL is a capacity value of the load capacity.

<Both low voltage operation and high gain>
In this embodiment, the gain of the first stage amplifier is low and the phase rotation is small. For this reason, an amplification stage (intermediate stage) by a cascode circuit can be placed between the input stage and the output stage of the second signal path. Since this intermediate stage does not require a dynamic range, cascode circuits (M9, M11) and (M10, M12) that can increase the amplification factor can be used.

  The minimum operating voltage of the above circuit is 1.15V (= the sum of the gate-source voltage VGS of the pMOS transistor M17 and the saturation voltage of the nMOS transistors M9 and M11 (= 0.65V + 0.25V + 0.25V)).

  In order to obtain the effect of widening the band, it is essential to use a low resistance load in the first stage amplifier. In this embodiment, the bias currents of the input transistors M5 (M6) and M19 (M20) in the next stage are accurately set. Therefore, a dedicated load circuit (M24, R3, Ib) is provided to enable the use of a resistive load.

<Bias current setting mechanism>
Next, the bias current setting mechanism and the erasing of the secondary pole p2 in this embodiment will be supplemented.

In this embodiment, nMOS transistor M5 which forms the input stage of the next stage amplifying portion (element) (M6), the bias current of M19 (M20), stable, set to a constant multiple of the constant current source _{I b.}

In the circuit of FIG.
The drain current of the nMOS transistor M23 of the current source that supplies a constant current to the differential pair (M1, M2) is 2I ₁ ,
put and _{I 2} and the drain current of the pMOS transistor M3 (M4).
The values of the resistors R1 and R2 are R,
The resistance value of the resistor R3 is k times (= k × R) the resistance value R of R1.

  The ratio of the gate areas (gate width W) of the nMOS transistors M23 and M24 is m: 1.

If I ₂ > I ₁ , the current value from the common connection point of the resistors R1 and R2 toward the drain of the nMOS transistor M24,
2 × (I ₂ −I ₁ )
Flows. That is, two times the current value of the half of the difference current drain current 2I ₁ of the drain current _{I 2} and the nMOS transistor M23 of the pMOS transistor M3 (M4) is, from the common connection point of the resistors R1 and R2, the drain of the nMOS transistor M24 It flows toward.

The drain current flowing through the nMOS transistor M24 is the sum of the constant current value _Ib and the current value 2 × (I ₂ −I ₁ ) from the common connection point of the resistors R1 and R2 I _b + 2 × (I ₂ −I ₁ )
It becomes.

The nMOS transistors M23 and M24 form a current mirror circuit, and the ratio between the current value 2 × I ₁ flowing through the nMOS transistor M23 and the current value I _b + 2 × (I ₂ −I ₁ ) flowing through the nMOS transistor M24 is m: 1. Therefore, the following equation holds.

m × [I _b + 2 × (I ₂ −I ₁ )] = 2 × I ₁ (1)

The drain current (= 2 × I ₁ ) of the nMOS transistor M23 is given by the following equation (2) when 2 × I ₁ is obtained from the equation (1).

m × (I _b + 2 × I ₂ ) / (m + 1) (2)

  The drain current of the nMOS transistor M24 is 1 / m of the drain current of the nMOS transistor M23, and is given by the following equation (3).

(I _b + 2 × I ₂ ) / (m + 1) (3)

A condition is obtained in which the drain potential of the nMOS transistor M1 (M2) matches the gate-source voltage V _GS (= VA) of the nMOS transistor M24.

The potential at the common connection point of the load resistors R1 and R2 of the first stage amplifier is a voltage obtained by subtracting the voltage drop (= k × R × I _b ) of the resistor R3 from VA, and can be expressed by the following equation (4).

VA-k × R × I _b (4)

  Therefore, the drain potential of the nMOS transistor M1 (M2) is given by the following equation (5).

R × (I ₂ −I ₁ ) + VA−k × R × I _b (5)

The condition for the drain potential of the nMOS transistor M1 (M2) to coincide with VA is as follows:
R × (I ₂ −I ₁ ) + VA−k × R × I _b = VA
Therefore, it is given by the following equation (6).

R × (I ₂ −I ₁ ) = k × R × I _b (6)

The value of the drain current _{I 2} of the pMOS transistor M3 (M4), from equations (2) (6), to clear the _{I 1,} is given by the following equation (7).

I ₂ = [m / 2 + k × (m + 1)] I _b (7)

From the equations (3) and (7), the drain current of the nMOS transistor M24 is
(1 + 2 × k) × I _b (8)
It becomes.

To summarize the contents mentioned above, the drain current _{I 2} of the pMOS transistor M3 (M4), as shown in the above equation (7), is set to [m / 2 + k × ( m + 1)] times _{I b,} nMOS transistor M1 The drain potential of (M2) matches the gate-source voltage V _GS (= VA) of the nMOS transistor M24.

When the gate area (gate width W) of the nMOS transistor M5 (M6) or nMOS transistor M19 (M20) is n times the gate area (gate width W) of the nMOS transistor M24, the nMOS transistor M5 (M6) or nMOS transistor In M19 (M20), from (8), n × (1 + 2 × k) × I _b (9)
The drain current flows.

  From the equation (9), the bias current of the nMOS transistor M5 (M6) or the nMOS transistor M19 (M20) indicates that the gate area ratio (gate width ratio) n of the transistor, the nMOS transistor M24, and the resistances of the resistors R3 and R1. It is determined by a coefficient n × (1 + 2 × k) defined by the value ratio k. For this reason, extremely stable setting is possible. When a differential signal is input to Vin + and Vin−, the drain current changes around the bias current in the nMOS transistor M5 (M6) or the nMOS transistor M19 (M20).

  For the pMOS transistor M17 (M18), a stable bias setting is performed using the common-mode current detection circuit.

  When a differential signal is input to the input terminals Vin + and Vin−, the gate potential of the pMOS transistor M17 (M18) varies due to a change in the drain current of the nMOS transistor M5 (M6). Of course, the stability of the bias current of the pMOS transistor M17 (M18) is also required at this time.

  In this embodiment, in order to stabilize the bias current of the pMOS transistor M17, a common-mode current detection circuit configured by connecting the drains of the pMOS transistor M8 and the pMOS transistor M15 is provided. In order to stabilize the bias current of the pMOS transistor M18, a common-mode current detection circuit configured by connecting the drains of the pMOS transistor M7 and the pMOS transistor M16 is provided. The function of bias setting of these common-mode current detection circuits will be described below.

  When a differential signal is input to Vin + and Vin−, a first current mirror circuit (M17) composed of a pMOS transistor M15 having the same gate area as that of the pMOS transistor M7 according to a change in the drain current of the pMOS transistor M17. , M15, and M7), a mirror current that is the same as or proportional to the drain current of the pMOS transistor M17 flows through these transistors M7 and M15, and the same as the pMOS transistor M8 according to the change in the drain current of the pMOS transistor M18. Due to the second current mirror circuit (M18, M16, M8) composed of the pMOS transistor M16 having the gate area, a mirror current that is the same as or proportional to the drain current of the pMOS transistor M18 flows through these transistors M8, M16.

  In this embodiment, the drain of the pMOS transistor M8 and the drain of the pMOS transistor M15 are connected at the node N1, and the drain of the pMOS transistor M7 and the drain of the pMOS transistor M16 are connected at the node N2. In the current obtained by adding the drain currents of these transistors M8 and M15 (M7 and M16), the differential component is canceled out to become zero, and only the in-phase component remains.

That is, a mirror current (I _CM / 2 + ΔI) that is the same as or proportional to the drain current of the pMOS transistor M17 (M18) connected to the output terminal Vout− (Vout +) flows through the drain of the pMOS transistor M15 (M16). A mirror current (I _CM / 2-ΔI) that is the same as or proportional to the drain current of the pMOS transistor M18 (M17) connected to the output terminal Vout + (Vout−) flows to the drain of the transistor M8 (M7). The node N1 (the drains of the pMOS transistors M16 and M7, the source of the pMOS transistor M14, and the drain of the nMOS transistor M6) where the drains of M15 and M8, the source of the pMOS transistor M13, and the drain of the nMOS transistor M5 are connected in common. In the node N2 which is commonly connected to IN, these two mirror currents (I _CM / 2 + ΔI) and (I _CM / 2−ΔI) are summed, and as a result, the differential component (± ΔI) is canceled out. In the node N1 (N2), only the in-phase component current (I _CM ) remains.

The common-mode current (I _CM ) is supplied to the constant current source transistor M9 (M10) by a local feedback configuration in which the drain of the grounded pMOS transistor M13 (M14) is connected to the gate of the pMOS transistor M15 (M16). And the current value of the sum of the bias current of the nMOS transistor M5 (M6).

  Accordingly, the bias current of the pMOS transistors M17 and M15 constituting the first current mirror circuit with the pMOS transistors M7 and M15 is stably fixed by the gate area ratio (gate width W) of the transistors (M17, M15, M7). Similarly, the bias current of the pMOS transistors M18 and the pMOS transistors M18 constituting the second current mirror circuit (M18, M6, M8) is the gate area ratio (gate width W) of the transistors (M18, M16, M8). It is fixed stably by.

  Next, a condition (p2 = z1) in which the secondary pole p2 is erased will be described with reference to FIG. A condition for erasing the secondary pole p2 is given using a small signal equivalent circuit for differential signals.

In FIG.
gm1, gm5, gm17, and gm19 are respectively transconductances of the MOS transistors M1, M5, M17, and M19 in FIG.
CS is the sum of the gate capacitance of the pMOS transistor M17 and other capacitance connected in parallel.
CL is a load capacitance connected to the output terminal Vout−.
R1 and C1 are the resistors R1 and C1 in FIG.

  In FIG. 2, for the sake of simplicity, the output resistance of the nMOS transistor transistors M1, M5, M19, and M21, the pMOS transistor M17, and the influence of the cascode circuit formed by the common gate transistor M13 and the nMOS transistors M9 and M11 that are the loads. Is ignored.

If the calculation in the middle is omitted and s is a complex frequency, the transfer function of the small signal equivalent circuit of FIG.

  Therefore, when p2 = z, the secondary pole p2 is erased by the zero point z. The condition for satisfying this is given by the following equation from the above equations for p2 and z.

  The left side of the above formula is the ratio of mutual conductances gm19 and gm5, and the right side is the ratio of capacitances CL and Cc. This conditional expression can be stably realized with respect to element variations and temperature fluctuations in a semiconductor integrated circuit. At this time, the transfer function becomes first order as shown by the following equation, and the phase margin is greatly improved (ideally, at least 90 °).

である。 Therefore, the unity gain frequency when p2 = z holds is

It is.

  Hereinafter, the related art of FIG. 4 and this embodiment will be described in comparison with the bias current setting means for the first stage amplifier, the intermediate stage, and the input transistor.

<Configuration of first stage amplifier>
(Related technology)
The first stage load is an active load by a transistor, and because of the high gain, a low frequency pole is generated, so phase compensation is necessary.

(Example)
The first stage load has a low gain because of its low resistance, and the generated poles are in a very high frequency range, and phase compensation is not required in the first stage. The first signal path has a wide band, and the secondary pole generated in the second signal path can be erased stably with respect to element variations and the like. As a result, the total operational amplifier circuit has a very wide frequency characteristic.

<Intermediate stage>
(Related technology)
Neither the first nor the second signal path exists.

(Example)
A large gain is obtained by the cascode circuit having an amplification stage of the cascode circuit in the second signal path.

  Further, by replacing the cascode circuit with a gain / boost circuit, higher gain or low voltage operation becomes possible.

<Input transistor bias current setting means>
(Related technology)
The bias current of the input transistors (M5 (M6), M11 (M12)) at the next stage is fixed in a common-mode feedback loop constituted by the drain outputs of the nMOS transistors M15, M1, and M2.

(Example)
By connecting a connection point between the load resistors R1 and R2 to a bias circuit including a MOS transistor M24, a resistor element R3, and a constant current source Ib, the input transistors (M5 (M6) and M19 (M20)) of the next stage are connected. The bias current is fixed.

  According to the present embodiment, it is possible to use a low resistance load as the load of the first stage amplifier (broadband).

<Example 2>
Next, a second embodiment of the present invention will be described. FIG. 3 is a diagram showing a circuit configuration of the second embodiment of the present invention. Referring to FIG. 3, the operational amplifier circuit according to the present embodiment includes a cascode circuit formed by the nMOS transistors M9 and M11 (M10 and M12) according to the first embodiment, an nMOS transistor M25 capable of operating at a low voltage, a pMOS transistor M27, The gain / boost circuit is replaced by M29, nMOS transistors M31 and M33, and resistors R4 and R6 (M26, M28, M30, M32, M34, R5, and R7). By replacing the cascode circuit of FIG. 1 with a series circuit of one transistor and a resistor, further low voltage operation is possible.

  In FIG. 3, instead of the nMOS transistors M9 and M11 stacked vertically in two stages between the drain of the pMOS transistor M13 and GND, in FIG. 3, an nMOS transistor M33 (first gain) constituting the first gain / boost circuit is used. (The gate potential is controlled by a boost amplifier) and a resistor R6 series circuit. This first gain / boost circuit is a circuit that controls the on-resistance by controlling the gate voltage of the nMOS transistor M33 in accordance with the source voltage of the nMOS transistor M33. The connection point between the source of the nMOS transistor M33 and the resistor R6 Is connected to the other end of the resistor R4 whose one end is connected to GND, the source is connected to the gate of the nMOS transistor M31, and the drain is connected to the nMOS transistor. An nMOS transistor M25 (first gain boost amplifier) connected to the gate of the transistor M33 is provided. The drains of the nMOS transistors M31 and M25 are connected to the power supply VDD, and the pMOS transistor receives the bias voltage Vb1 at the gate. M29 It is connected to the drains of M27 (the constant current source transistor).

で与えられる。 The nMOS transistor M25 includes a terminal voltage of the resistor R4 (corresponding to a reference voltage input to the first gain boost amplifier) to which the constant current from the pMOS transistor M27 serving as a constant current source is supplied, and a resistance R6 An output voltage (drain voltage) corresponding to a difference voltage (that is, a gate-source voltage of the nMOS transistor M25) from the voltage obtained by level shifting the terminal voltage by the nMOS transistor M31 is applied to the gate of the nMOS transistor M33, and the output impedance is increased. It functions as a first gain boost amplifier having a resistance (therefore, the load resistance value between the node N3 and GND is high resistance). When the resistance value of the resistor R6 is r6, the gain (gain) of the gain boost amplifier is A, the transconductance of the transistor M33 is gm33, and the output resistance is ro33, the resistance R between the GND and the node N3 is, for example,

Given in.

  Further, instead of the two-stage vertically stacked nMOS transistors M10 and M12 in FIG. 1, between the drain of the pMOS transistor M14 and the GND, in FIG. 3, an nMOS transistor M34 (second output) constituting the second gain / boost circuit is shown. The gate potential is controlled by a gain boost amplifier), and a series circuit of a resistor R7. This second gain / boost circuit is a circuit that controls the on-resistance by controlling the gate voltage of the nMOS transistor M34 in accordance with the source voltage of the nMOS transistor M34, and the connection point between the source of the nMOS transistor M34 and the resistor R7. Is connected to the other end of the resistor R5 having one end connected to GND, the gate is connected to the gate of the nMOS transistor M32, and the drain is connected to the nMOS. The nMOS transistor M26 (second gain boost amplifier) connected to the gate of the transistor M34 is provided. The drains of the nMOS transistors M32 and M26 are connected to the power supply VDD, and the pMOS transistor receives the bias voltage Vb1 at the gate. M30 It is connected to the drains of M28 (the constant current source transistor).

  The nMOS transistor M26 has a terminal voltage of the resistor R5 (corresponding to the reference voltage input to the second gain / boost amplifier) to which the constant current from the pMOS transistor M28 forming the constant current source is supplied, and a terminal of the resistor R7. An output voltage (drain voltage) corresponding to a difference voltage (voltage between the gate and source of the nMOS transistor M26) from the voltage obtained by level shifting the voltage by the nMOS transistor M32 is applied to the gate of the nMOS transistor M34, and the output impedance is set to a high resistance ( Therefore, it functions as a second gain boost amplifier having a high load resistance value between the pMOS transistor M14 and GND.

  Note that the resistor R6 (R7) may be formed of an nMOS transistor M9 (M10) as in FIG.

  3 is 0.95V (= the sum of the gate-source voltage VGS of the pMOS transistor M17, the saturation voltage of the nMOS transistor M33, and the voltage drop of the resistor R6≈0.65V + 0.25V + 0. 05V).

  As a simulation result, a 0.25 μm CMOS@1.1V, a DC gain of 83 dB, a unity gain frequency of 2.2 GHz, a high gain and a wide band characteristic are obtained.

  In the embodiments shown in FIGS. 1 and 3, the polarity of the transistors may be changed, for example, the differential pairs M1 and M2 are composed of pMOS transistors, and M3 and M4 are composed of nMOS transistors. . According to this embodiment, it is possible to cope with low power supply voltage and low current consumption, high gain, and wide bandwidth, and an operational amplifier circuit that is suitable for mounting on a semiconductor integrated circuit is provided. According to the present invention, a semiconductor integrated circuit in which the operational amplifier circuit is mounted on a chip is provided.

  It should be noted that the disclosures of the above-mentioned patent documents and non-patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

C1, C2, C3 Capacitance Ib, Ibias Constant current source M1-M36 Transistors R1-R7 Resistors Vb, Vb1, Vb2, Vb3, Vb4, Vcmfb, Vcmfb1, Vcmfb2 Bias voltage Vin +, Vin− Input terminal Vout +, Vout− Output terminal

Claims (18)

A first-stage amplifier including a differential pair that receives a differential input signal and has a resistive load;
A next-stage amplifier connected to the output of the first-stage amplifier and outputting an output signal from an output terminal; and
With
The next-stage amplifier is
A first signal path having a one-stage configuration including a transistor having a source connected to a first power supply, a gate connected to one of the output pairs of the differential pair, and a drain connected to the output terminal;
An input stage including a transistor having a source connected to the first power supply and a gate connected to the other output pair of the differential pair, a source connected to the second power supply, and a drain connected to the output terminal An output stage including a transistor;
A second signal path comprising an intermediate stage having an input connected at a first node to the drain of the transistor in the input stage, and an output connected at the second node to the gate of the transistor in the output stage;
In addition,
An operational amplifier circuit comprising a bias circuit that sets at least a bias current flowing through the transistor of the first signal path and the transistor of the input stage of the second signal path in the next stage amplifier. In the second signal path,
The intermediate stage is
A gate-grounded transistor connected between the first node and the second node;
An active load circuit connected between the second node and the first power source;
The operational amplifier circuit according to claim 1, comprising:   The operational amplifier circuit according to claim 2, wherein the active load circuit includes a plurality of transistors that are cascode-connected between the first power supply and the second node.   The operational amplifier circuit according to claim 2, wherein the active load circuit includes a gain boost circuit. The gain boost circuit is
A gain / boost amplifier having a terminal voltage of a resistance element connected to the first power supply and a predetermined reference voltage as inputs;
The operational amplifier circuit according to claim 4, further comprising a transistor connected between the other end of the resistance element and the second node and having a gate connected to an output of the gain boost amplifier. In the second signal path,
6. The operational amplification according to claim 2, wherein a current of a differential component corresponding to a differential output is summed and canceled at the first node, and a current corresponding to an in-phase component remains. circuit. In the second signal path,
The operational amplifier circuit according to claim 1, further comprising a capacitor between a drain and a gate of the transistor in the output stage. The first stage amplifier is
A first current source having one end connected to the first power source;
First and second resistive elements forming the resistive load;
A source is commonly connected to the other end of the first current source, a gate is connected to each of the first and second input terminals forming a differential input, and a drain is connected to one end of the first and second resistance elements. Are respectively connected to the first and second transistors of the first conductivity type;
A second conductivity type third and fourth transistor having a source connected to a second power source, a drain connected to the drain of each of the first and second transistors, and a gate connected to each other;
With
In the next stage amplification unit,
The second signal path is:
Fifth and sixth transistors of first conductivity type, each having a source connected to the first power supply and a gate connected to the drains of the first and second transistors;
A second conductivity type seventh and eighth transistors having a source connected to the second power source and drains connected to first and second output terminals for differential output;
The fifth and sixth transistors form the input stage of the second signal path;
The seventh and eighth transistors form the output stage of the second signal path;
A source connected to the second power source, and a ninth transistor and an eleventh transistor of the second conductivity type constituting the first current mirror circuit with the seventh transistor;
A source connected to the second power supply; a tenth and a twelfth transistors of a second conductivity type forming a second current mirror circuit with the eighth transistor;
With
The intermediate stage is
A second conductivity type thirteenth transistor having a source connected to the drain of the ninth transistor;
Fifteenth and seventeenth transistors of the first conductivity type cascode-connected between the first power source and the drain of the thirteenth transistor;
A fourteenth transistor of the second conductivity type having a source connected to the drain of the tenth transistor;
Sixteenth and eighteenth transistors of the first conductivity type cascode-connected between the first power source and the drain of the fourteenth transistor;
With
The drains of the fifth, ninth, and twelfth transistors and the source of the thirteenth transistor are connected in common,
The drains of the sixth, tenth and eleventh transistors and the source of the fourteenth transistor are connected in common,
The drain of the thirteenth transistor is connected to the gate of the ninth transistor;
The drain of the fourteenth transistor is connected to the gate of the tenth transistor;
The sources of the thirteenth and fourteenth transistors form the first node corresponding to the inverting and non-inverting sides, respectively.
The drains of the thirteenth and fourteenth transistors constitute the second node corresponding to the inversion and non-inversion sides, respectively.
The first signal path is:
A first conductivity type nineteenth having a source connected to the first power supply, a drain connected to each of the first and second output terminals, and a gate connected to the drain of each of the second and first transistors. The operational amplifier circuit according to claim 1, further comprising: a twentieth transistor. The first stage amplifier is
A first current source having one end connected to the first power source;
First and second resistive elements forming the resistive load;
A source is commonly connected to the other end of the first current source, a gate is connected to each of the first and second input terminals forming a differential input, and a drain is connected to one end of the first and second resistance elements. Are respectively connected to the first and second transistors of the first conductivity type;
A second conductivity type third and fourth transistor having a source connected to a second power source, a drain connected to the drain of each of the first and second transistors, and a gate connected to each other;
With
In the next stage amplification unit,
The second signal path is:
Fifth and sixth transistors of first conductivity type, each having a source connected to the first power supply and a gate connected to the drains of the first and second transistors;
A second conductivity type seventh and eighth transistors having a source connected to the second power source and drains connected to first and second output terminals for differential output;
The fifth and sixth transistors form the input stage of the second signal path;
The seventh and eighth transistors form the output stage of the second signal path;
A source connected to the second power source, and a ninth transistor and an eleventh transistor of the second conductivity type constituting the first current mirror circuit with the seventh transistor;
A source connected to the second power supply; a tenth and a twelfth transistors of a second conductivity type forming a second current mirror circuit with the eighth transistor;
With
The intermediate stage is
A second conductivity type thirteenth transistor having a source connected to the drain of the ninth transistor;
A first gain-boost circuit connected between the first power supply and the drain of the thirteenth transistor;
A fourteenth transistor of the second conductivity type having a source connected to the drain of the tenth transistor;
A second gain-boost circuit connected between the first power supply and the drain of the fourteenth transistor;
With
The drains of the fifth, ninth, and twelfth transistors and the source of the thirteenth transistor are connected in common,
The drains of the sixth, tenth and eleventh transistors and the source of the fourteenth transistor are connected in common,
The drain of the thirteenth transistor is connected to the gate of the ninth transistor;
The drain of the fourteenth transistor is connected to the gate of the tenth transistor;
The sources of the thirteenth and fourteenth transistors form the first node corresponding to the inverting and non-inverting sides, respectively.
The drains of the thirteenth and fourteenth transistors constitute the second node corresponding to the inversion and non-inversion sides, respectively.
The first signal path is:
A first conductivity type nineteenth having a source connected to the first power supply, a drain connected to each of the first and second output terminals, and a gate connected to the drain of each of the second and first transistors. The operational amplifier circuit according to claim 1, further comprising: a twentieth transistor. The first gain / boost circuit comprises:
A fourth resistance element having one end connected to the first power source;
A first gain-boost amplifier that receives a voltage at the other end of the fourth resistance element and a predetermined reference voltage;
A source is connected to the other end of the fourth resistance element, a drain is connected to the drain of the thirteenth transistor, and a gate is connected to the output of the first gain boost amplifier. A twenty-second transistor;
With
The second gain boost circuit is
A fifth resistance element having one end connected to the first power source;
A second gain-boost amplifier that receives as input a voltage at the other end of the fifth resistance element and a predetermined reference voltage;
A source is connected to the other end of the fifth resistance element, a drain is connected to the drain of the fourteenth transistor, and a gate is connected to the output of the second gain boost amplifier. A 23rd transistor;
The operational amplifier circuit according to claim 9, comprising: The first gain / boost circuit comprises:
A fourth resistance element having one end connected to the first power source;
A first conductivity type 22nd transistor having a source connected to the other end of the fourth resistance element and a drain connected to the drain of the 13th transistor;
A sixth resistance element having one end connected to the first power source;
A 24th transistor of the first conductivity type having a source connected to the other end of the sixth resistance element and a drain connected to the gate of the 22nd transistor;
A source connected to the other end of the fourth resistance element, a gate connected to the gate of the 24th transistor, and a diode-connected 26th transistor of the first conductivity type;
With
The second gain boost circuit is
A fifth resistance element having one end connected to the first power source;
A first conductivity type 25th transistor having a source connected to the other end of the fifth resistance element and a drain connected to the drain of the 14th transistor;
A seventh resistance element having one end connected to the first power source;
A 26th transistor of the first conductivity type having a source connected to the other end of the seventh resistance element and a drain connected to the gate of the 25th transistor;
A source connected to the other end of the fifth resistor, a gate connected to the gate of the 26th transistor, and a diode-connected 27th transistor of the first conductivity type;
The operational amplifier circuit according to claim 9, comprising:   The drains of the 24th, 25th, 26th and 27th transistors are respectively connected to the drains of the 28th, 29th, 30th and 31st transistors of the second conductivity type. The operational amplifier circuit according to claim 11, wherein the thirty-first and thirty-first transistors have a source commonly connected to the second power supply and a gate commonly connected to the gates of the third and fourth transistors. The bias circuit comprises:
A first conductivity type twenty-first transistor having a source connected to the first power source;
A third resistance element having one end connected to the drain of the twenty-first transistor;
A second current source connected between the other end of the third resistance element and the second power source;
With
A gate of the twenty-first transistor is connected to the other end of the third resistance element, and further connected to a gate of a first conductivity type transistor forming the first current source;
13. The operational amplifier circuit according to claim 8, wherein the other ends of the first and second resistance elements of the first stage amplifier are commonly connected to a drain of the twenty-first transistor. A first stage amplifier, a next stage amplifier, and a bias circuit are provided.
The first stage amplifier is
A first current source having one end connected to the first power source;
First and second resistance elements;
A source is commonly connected to the other end of the first current source, a gate is connected to each of the first and second input terminals forming a differential input, and a drain is connected to one end of the first and second resistance elements. Are respectively connected to the first and second transistors of the first conductivity type;
A second conductivity type third and fourth transistor having a source connected to a second power source, a drain connected to the drain of each of the first and second transistors, and a gate connected to each other;
With
The next-stage amplifier is
Fifth and sixth transistors of first conductivity type, each having a source connected to the first power supply and a gate connected to the drains of the first and second transistors;
A second conductivity type seventh and eighth transistor having a source connected to the second power source and a drain connected to first and second output terminals for differential output;
A source connected to the second power source, and a ninth transistor and an eleventh transistor of the second conductivity type constituting the first current mirror circuit with the seventh transistor;
A source connected to the second power supply; a tenth and a twelfth transistors of a second conductivity type forming a second current mirror circuit with the eighth transistor;
A second conductivity type thirteenth transistor having a source connected to the drain of the ninth transistor;
Fifteenth and seventeenth transistors of the first conductivity type cascode-connected between the first power source and the drain of the thirteenth transistor;
A fourteenth transistor of the second conductivity type having a source connected to the drain of the tenth transistor;
16th and 18th transistors of the first conductivity type cascode-connected between the first power supply and the drain of the 14th transistor;
A first conductivity type nineteenth having a source connected to the first power supply, a drain connected to each of the first and second output terminals, and a gate connected to the drain of each of the second and first transistors. And a twentieth transistor;
With
The drains of the fifth, ninth, and twelfth transistors and the source of the thirteenth transistor are connected in common,
The drains of the sixth, tenth and eleventh transistors and the source of the fourteenth transistor are connected in common,
The drain of the thirteenth transistor is connected to the gate of the ninth transistor;
The drain of the fourteenth transistor is connected to the gate of the tenth transistor;
The bias circuit comprises:
A first conductivity type twenty-first transistor having a source connected to the first power source;
A third resistor having one end connected to the drain of the twenty-first transistor;
A second current source connected between the other end of the third resistor and the second power source;
With
A gate of the twenty-first transistor is connected to the other end of the third resistor, and is further connected to a gate of a first conductivity type transistor forming the first current source;
An operational amplifier circuit in which the other ends of the first and second resistance elements of the first stage amplifier are commonly connected to the drain of the twenty-first transistor. A first stage amplifier, a next stage amplifier, and a bias circuit are provided.
The first stage amplifier is
A first current source having one end connected to the first power source;
First and second resistance elements;
A source is commonly connected to the other end of the first current source, a gate is connected to each of the first and second input terminals forming a differential input, and a drain is connected to one end of the first and second resistance elements. Are respectively connected to the first and second transistors of the first conductivity type;
A second conductivity type third and fourth transistor having a source connected to a second power source, a drain connected to the drain of each of the first and second transistors, and a gate connected to each other;
With
The next-stage amplifier is
Fifth and sixth transistors of first conductivity type, each having a source connected to the first power supply and a gate connected to the drains of the first and second transistors;
A second conductivity type seventh and eighth transistor having a source connected to the second power source and a drain connected to first and second output terminals for differential output;
A source connected to the second power source, and a ninth transistor and an eleventh transistor of the second conductivity type constituting the first current mirror circuit with the seventh transistor;
A source connected to the second power supply; a tenth and a twelfth transistors of a second conductivity type forming a second current mirror circuit with the eighth transistor;
A second conductivity type thirteenth transistor having a source connected to the drain of the ninth transistor;
A first gain-boost circuit connected between the first power supply and the drain of the thirteenth transistor;
A fourteenth transistor of the second conductivity type having a source connected to the drain of the tenth transistor;
A second gain-boost circuit connected between the first power supply and the drain of the fourteenth transistor;
A first conductivity type nineteenth having a source connected to the first power supply, a drain connected to each of the first and second output terminals, and a gate connected to the drain of each of the second and first transistors. And a twentieth transistor;
With
The drains of the fifth, ninth, and twelfth transistors and the source of the thirteenth transistor are connected in common,
The drains of the sixth, tenth and eleventh transistors and the source of the fourteenth transistor are connected in common,
The drain of the thirteenth transistor is connected to the gate of the ninth transistor;
The drain of the fourteenth transistor is connected to the gate of the tenth transistor;
The bias circuit comprises:
A first conductivity type twenty-first transistor having a source connected to the first power source;
A third resistance element having one end connected to the drain of the twenty-first transistor;
A second current source connected between the other end of the third resistance element and the second power source;
With
A gate of the twenty-first transistor is connected to the other end of the third resistance element, and further connected to a gate of a first conductivity type transistor forming the first current source;
An operational amplifier circuit in which the other ends of the first and second resistance elements of the first stage amplifier are commonly connected to the drain of the twenty-first transistor. The first gain / boost circuit comprises:
A fourth resistance element having one end connected to the first power source;
A first conductivity type 22nd transistor having a source connected to the other end of the fourth resistance element and a drain connected to the drain of the 13th transistor;
A sixth resistance element having one end connected to the first power source;
A 24th transistor of the first conductivity type having a source connected to the other end of the sixth resistance element and a drain connected to the gate of the 22nd transistor;
A source connected to the other end of the fourth resistance element, a gate connected to the gate of the 24th transistor, and a diode-connected 26th transistor of the first conductivity type;
With
The second gain boost circuit is
A fifth resistance element having one end connected to the first power source;
A first conductivity type 25th transistor having a source connected to the other end of the fifth resistance element and a drain connected to the drain of the 14th transistor;
A seventh resistance element having one end connected to the first power source;
A 26th transistor of the first conductivity type having a source connected to the other end of the seventh resistance element and a drain connected to the gate of the 25th transistor;
A source connected to the other end of the fifth resistor, a gate connected to the gate of the 26th transistor, and a diode-connected 27th transistor of the first conductivity type;
With
The drains of the 24th, 25th, 26th and 27th transistors are respectively connected to the drains of the 28th, 29th, 30th and 31st transistors of the second conductivity type. The operational amplifier circuit according to claim 15, wherein the thirtieth and thirty-first transistors have a source commonly connected to the second power supply and a gate commonly connected to the gates of the third and fourth transistors. A first capacitor provided between the drain and gate of the seventh transistor;
The operational amplifier circuit according to claim 8, further comprising a second capacitor between a drain and a gate of the eighth transistor.   A semiconductor device comprising the operational amplifier circuit according to claim 1.

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