JP5936447B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, for example, a semiconductor integrated circuit suitable for phase compensation.

  An amplifier circuit and a power supply circuit such as a series regulator using the amplifier circuit need to ensure stability by compensating the phase. Related techniques are disclosed in Patent Literature 1, Patent Literature 2, Patent Literature 3 and Patent Literature 4.

  The voltage regulator disclosed in Patent Document 1 forms a main loop by a first amplifier, a second amplifier, a P-MOSFET and a phase compensation capacitor, and a third amplifier, a DC component cut capacitor, and the P- A sub-loop is formed by the MOSFET. As a result, this voltage regulator can individually optimize the design for compensation of high-frequency fluctuations in the output voltage and the design for compensation of low-frequency fluctuations. This makes it possible to carry out easily in a short time.

  The phase compensation circuit for an operational amplifier disclosed in Patent Document 2 includes a buffer amplifier that receives an output signal of an output stage of an operational amplifier having an input stage and an output stage, one end connected to the output of the buffer amplifier, and the other end of the output stage. And a capacitor connected to the input. This capacitor is a MOS capacitor having an n-type diffusion layer in the n-well as a bottom electrode and a gate electrode as a top electrode, and is configured to apply a positive bias voltage to the top surface voltage with respect to the bottom electrode. As a result, this phase compensation circuit can reduce the cost and shorten the time required for the process.

  In the error compensation phase compensation circuit disclosed in Patent Document 3, a capacitor and a resistor are connected in series to the output terminal of the error amplifier, and a current flowing through the capacitor is amplified and fed back by a transconductance amplifier connected to both ends of the resistor. Thus, the frequency of the main pole of the frequency characteristic of the error amplifier is lowered. Thereby, this phase compensation circuit makes it possible to reduce the capacitor area on the IC chip.

  The constant voltage source circuit disclosed in Patent Document 4 outputs an output control transistor that outputs a voltage corresponding to an input control signal, and a control signal that corresponds to the difference between the output voltage of the output control transistor and a reference voltage. And a control circuit for generating the constant voltage source circuit. In this constant voltage source circuit, the control circuit includes a capacitor that feeds back the output voltage, and an amplifying unit that superimposes a current corresponding to the difference between the voltage fed back through the capacitor and a predetermined voltage on the control signal. . Thus, the constant voltage source circuit supplies a stable voltage even when there is a load change.

JP 2005-202781 A JP-A-10-270956 JP 2011-151537 A JP 2005-84869 A

  However, Patent Document 1 does not disclose the downsizing of the phase compensation capacitor. Therefore, this related technique has a problem that the scale of the phase compensation capacitor cannot be reduced and the circuit scale increases.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a potential difference between an output transistor that generates an output voltage according to a control signal, a feedback signal having a voltage level according to the output voltage, and a reference voltage is amplified and output as the control signal. A first amplifying unit, a capacitor that generates a first current according to a change in the output voltage, amplifying the first current to generate a second current, and superimposing the second current on the control signal A current amplifying unit.

  According to the embodiment, it is possible to provide a semiconductor integrated circuit capable of reducing the scale of the phase compensation capacitor.

1 is a conceptual diagram of a semiconductor integrated circuit according to a first embodiment; 2 is a circuit diagram showing a configuration example of an amplifier circuit AMP11 according to the first embodiment; FIG. FIG. 3 is a circuit diagram showing a configuration example of a semiconductor integrated circuit according to a second embodiment; FIG. 6 is a diagram illustrating frequency characteristics of the semiconductor integrated circuit according to the second embodiment. FIG. 6 is a circuit diagram illustrating a configuration example of a semiconductor integrated circuit according to a third embodiment; FIG. 6 is a circuit diagram showing a configuration example of a semiconductor integrated circuit according to a fourth embodiment; FIG. 10 is a circuit diagram illustrating a configuration example of a semiconductor integrated circuit according to a fifth embodiment; FIG. 10 is a circuit diagram showing a configuration example of a semiconductor integrated circuit according to a sixth embodiment; FIG. 10 is a circuit diagram illustrating a configuration example of an amplifier circuit AMP51 according to a sixth embodiment; FIG. 10 is a circuit diagram showing a modification of the semiconductor integrated circuit according to the sixth embodiment; FIG. 10 is a circuit diagram illustrating a configuration example of a semiconductor integrated circuit according to a seventh embodiment; FIG. 10 is a circuit diagram illustrating a configuration example of a semiconductor integrated circuit according to an eighth embodiment; FIG. 10 is a circuit diagram illustrating a specific configuration example of a semiconductor integrated circuit according to an eighth embodiment; FIG. 10 is a circuit diagram illustrating a specific configuration example of a semiconductor integrated circuit according to an eighth embodiment; It is a circuit diagram which shows the structural example of the semiconductor integrated circuit concerning the concept before reaching embodiment. It is a circuit diagram which shows the structural example of the semiconductor integrated circuit concerning the concept before reaching embodiment. It is a circuit diagram which shows the structural example of the semiconductor integrated circuit concerning the concept before reaching embodiment.

<Preliminary examination by the inventors>
Prior to the description of the embodiment, the contents previously examined by the present inventors will be described.

  FIG. 15 is a circuit diagram showing a configuration of the semiconductor integrated circuit 100 according to the concept before reaching the embodiment. The semiconductor integrated circuit 100 is a so-called series regulator.

  A semiconductor integrated circuit 100 shown in FIG. 15 includes an output transistor MP101, an amplifier circuit AMP101, a phase compensation capacitor C101, and resistance elements R101 and R102. Here, a case where the output transistor MP101 is a P-channel MOS transistor will be described as an example.

  The output transistor MP101 generates an output voltage VOUT (voltage of the output terminal VOUT) corresponding to the control signal va ′ (voltage of the node va ′). The resistance elements R101 and R102 divide the output voltage VOUT and output a feedback signal vfeed. The amplifier circuit AMP101 amplifies the potential difference between the reference voltage vref and the feedback signal vfeed and outputs it as a control signal va ′.

  For example, when the output voltage VOUT rises from a desired voltage level, the voltage level of the feedback signal vfeed to the amplifier circuit AMP101 rises and becomes larger than the reference voltage vref. Therefore, the amplifier circuit AMP101 has the voltage level of the control signal va ′. To raise. As a result, the output voltage VOUT drops. On the other hand, when the output voltage VOUT decreases from the desired voltage level, the voltage level of the feedback signal vfeed to the amplifier circuit AMP101 decreases and becomes smaller than the reference voltage vref. Therefore, the amplifier circuit AMP101 has the voltage level of the control signal va ′. Descent. As a result, the output voltage VOUT rises. In this way, the output voltage VOUT is maintained at a desired voltage level.

  The phase compensation capacitor C101 is provided between the node va ′ and the output terminal VOUT, and performs phase compensation to prevent oscillation of the output voltage VOUT.

  Here, the current gain of the output transistor MP101 is defined as gm_MP101, and the drain resistance is defined as rds_MP101. Also, a parallel resistance of the drain resistance rds_MP101 of the output transistor MP101, the resistance elements R101 and R102, and the external additional resistance connected to the output terminal VOUT is defined as ro ′.

  In this case, the capacitance value of the capacitor C101 viewed from the node va ′ appears to be larger than the actual voltage gain (gm_MP101 × ro ′) times of the output transistor MP101 due to the Miller effect. As a result, even with a relatively small capacitor C101, a dominant pole (first pole) can be generated at the node va ′.

  Note that the phase compensation method for generating a dominant pole at the node va ′ inside the circuit as in the semiconductor integrated circuit 100 is a particularly effective method when a capacitor having a large capacitance value cannot be provided outside the output terminal VOUT. .

  For example, in a configuration in which a capacitor having a large capacitance value is provided outside the output terminal VOUT (that is, a configuration in which a dominant pole is generated in the output terminal VOUT), there is a problem that the circuit scale increases. The capacitor is generally provided as a separate component (external component) outside the chip. Therefore, this configuration has a problem that the cost increases. Furthermore, there is a problem that an external pin for connecting a capacitor must be additionally provided on the chip.

  On the other hand, such a problem does not occur in the semiconductor integrated circuits 100 and 200 configured without providing a capacitor having a large capacitance value outside the output terminal VOUT. In addition, there is an effect that safety is further improved by reducing the number of external pins.

  However, in the configuration of the semiconductor integrated circuit 100, a zero occurs in the right half plane in the complex plane by design. Therefore, there is a problem that the semiconductor integrated circuit 100 cannot stably prevent oscillation of the output voltage VOUT.

  In order to solve this problem, the semiconductor integrated circuit 200 shown in FIG. 16 was examined. FIG. 16 is a circuit diagram showing a configuration of a semiconductor integrated circuit 200 according to the concept before reaching the embodiment. The semiconductor integrated circuit 200 shown in FIG. 16 further includes a transistor MN102 that functions as a common-gate amplifier circuit between the capacitor and the node va ′, as compared with the semiconductor integrated circuit 100 shown in FIG.

  More specifically, the semiconductor integrated circuit 200 illustrated in FIG. 16 includes transistors MP102, MN101, and MN102 as compared with the semiconductor integrated circuit 100 illustrated in FIG. Here, a case where the transistor MP102 is a P-channel MOS transistor and the transistors MN101 and MN102 are N-channel MOS transistors will be described as an example.

  The transistor MP102 is provided between a power supply voltage terminal to which the power supply voltage VCC is supplied (hereinafter referred to as a power supply voltage terminal VCC) and the node va ′, and a bias voltage Vbp101 is supplied to the gate. The transistor MN102 is provided between the node va ′ and the node vb ′, and a bias voltage Vbn102 is supplied to the gate. The transistor MN101 is provided between the node vb ′ and a ground voltage terminal to which the ground voltage GND is supplied (hereinafter referred to as a ground voltage terminal GND), and a bias voltage Vbn101 is supplied to the gate. The transistors MP102 and MN101 each function as a constant current source for supplying a predetermined current. The capacitor C101 is provided between the node vb ′ and the output terminal VOUT. The other circuit configuration of the semiconductor integrated circuit 200 shown in FIG. 16 is the same as that of the semiconductor integrated circuit 100 shown in FIG.

  Thereby, the semiconductor integrated circuit 200 shown in FIG. 16 can prevent the zero point from being generated in the right half plane in the complex plane without impairing the advantage of the mirror effect. As a result, the semiconductor integrated circuit 200 can more stably prevent oscillation of the output voltage VOUT than the semiconductor integrated circuit 100 shown in FIG. In addition, the semiconductor integrated circuit 200 has an advantage such as a high power supply voltage rejection ratio (PSRP).

  However, in the semiconductor integrated circuit 200, the above-described mirror effect may be reduced depending on conditions such as the process, the power supply voltage VCC, the output voltage VOUT, and the temperature environment. Therefore, the semiconductor integrated circuit 200 needs to increase the scale of the capacitor C101 to some extent, assuming that the mirror effect is reduced. As a result, the semiconductor integrated circuit 200 has a problem that the circuit scale increases.

  Further, in the semiconductor integrated circuit 200, a large current needs to flow through the transistor MN102 functioning as a grounded gate amplifier circuit, which causes a problem that current consumption increases. This will be specifically described below.

  The semiconductor integrated circuit 200 does not attenuate the feedback signal that is fed back from the output terminal VOUT to the node va ′ through the capacitor C101 to a frequency that needs to be compensated by setting the pole generated at the node vb ′ to a high frequency. There is a need to.

  In order to generate a high-frequency pole at the node vb ′, it is necessary to make the time constant τ of the node vb ′ as small as possible. The time constant τ can be expressed as C ′ × 1 / gm ′, where C ′ is the capacitance value of the capacitor C101 and gm ′ is the transconductance of the transistor MN102. Here, since the capacitance value C ′ of the capacitor C101 is large as described above, 1 / gm ′ needs to be as small as possible in order to reduce the time constant τ. In order to reduce 1 / gm ′, it is necessary to pass a large current through the transistor MN102. For this reason, the semiconductor integrated circuit 200 has a problem that current consumption increases.

  Furthermore, the semiconductor integrated circuit 200 has a problem that the input conversion offset voltage of the amplifier circuit AMP101 becomes large. This will be specifically described below.

  The semiconductor integrated circuit 200 is usually designed such that substantially the same bias current flows through the transistors MP102 and MN101 functioning as constant current sources. FIG. 17 is a circuit diagram of the semiconductor integrated circuit 200 in which the configuration of the bias voltage generator is clearly shown. The bias voltage generation unit includes transistors MP103, MN103, and MN104. Here, a case where the transistor MP103 is a P-channel MOS transistor and the MN103 and MN104 are N-channel MOS transistors will be described as an example. As can be seen from FIG. 17, the semiconductor integrated circuit 200 is designed such that substantially the same current flows through the transistors MP102 and MN101.

  However, actually, the bias currents flowing through the transistors MP102 and MN101 may not be substantially the same due to device mismatch or process. In this case, the difference current between the bias current flowing through the transistor MP102 and the bias current flowing through the transistor MN101 flows into the output terminal of the amplifier circuit AMP101 via the node va ′. As this difference current increases, the input equivalent offset voltage of the amplifier circuit AMP101 increases.

  Here, in the semiconductor integrated circuit 200, since a large current flows through the transistors MP102 and MN101 as described above, the difference current becomes larger than when a small current flows through the transistors MP102 and MN101. Therefore, the semiconductor integrated circuit 200 has a problem that the input conversion offset voltage of the amplifier circuit AMP101 becomes large.

  Further, when the bias current flowing through the transistors MP102 and MN101 changes depending on conditions such as the process, the power supply voltage VCC, and the temperature, the input conversion offset voltage also changes accordingly. Therefore, the semiconductor integrated circuit 200 has a problem that it cannot generate the output voltage VOUT with high accuracy.

  The above-described problem is particularly noticeable when the difference voltage VCC-VOUT between the power supply voltage VCC and the output voltage VOUT is small (in the case of the Low-Dropout configuration). This will be specifically described below.

  First, when the difference voltage between the power supply voltage VCC and the output voltage VOUT is small, the mirror effect is small, and therefore the size of the capacitor C101 needs to be increased. Further, when the difference voltage between the power supply voltage VCC and the output voltage VOUT is small, the drain resistance rds_MP101 of the transistor MP101 is small, and accordingly, the voltage gain (rds_MP101 × ro ′) of the transistor MP101 is also small. When the voltage gain is reduced, the mirror effect is reduced, so that the scale of the capacitor C101 needs to be further increased. As a result, the circuit scale of the semiconductor integrated circuit 200 further increases. Along with this, the current consumption further increases, and the input conversion offset voltage further increases.

  In recent years, a series regulator employing a Low-Dropout configuration has been demanded for the purpose of improving power efficiency and expanding the range of the power supply voltage VCC. For this reason, there is a growing need to reduce the scale of the circuit for reducing the scale of the phase compensation capacitor.

  Hereinafter, embodiments will be described with reference to the drawings. Since the drawings are simple, the technical scope of the embodiments should not be narrowly interpreted based on the description of the drawings. Moreover, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including operation steps and the like) are not necessarily essential except when clearly indicated and clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

<Embodiment 1>
FIG. 1 is a conceptual diagram of a semiconductor integrated circuit 1 according to the first embodiment. In the semiconductor integrated circuit 1 according to the present embodiment, the feedback current generated by the phase compensation capacitor is amplified by the current amplifier and fed back to the gate of the output transistor. Thereby, in the semiconductor integrated circuit 1 according to the present embodiment, the scale of the phase compensation capacitor can be made smaller than before. As a result, the semiconductor integrated circuit 1 according to the present embodiment can suppress an increase in circuit scale. This will be specifically described below.

  The semiconductor integrated circuit 1 shown in FIG. 1 is a so-called series regulator, and includes an output transistor MP11, an amplifier circuit (first amplifier) AMP11, resistance elements R11 and R12, and a phase compensator 11. The phase compensation unit 11 includes a phase compensation capacitor C11, a current amplification unit 12, and an AC voltage source A11. In the present embodiment, a case where the output transistor MP11 is a P-channel MOS transistor will be described as an example.

  The output transistor MP11 is provided between a power supply voltage terminal to which the power supply voltage VCC is supplied (hereinafter referred to as a power supply voltage terminal VCC) and the output terminal VOUT. The resistance elements R11 and R12 are provided in series between the output terminal VOUT and a ground voltage terminal to which the ground voltage GND is supplied (hereinafter referred to as a ground voltage terminal GND). In the amplifier circuit AMP11, an inverting input terminal is connected to an input terminal to which a reference voltage vref is supplied (hereinafter referred to as an input terminal vref), a non-inverting input terminal is connected to a node between the resistance elements R11 and R12, and an output terminal Is connected to the gate of the output transistor MP11 via the node va. The phase compensation unit 11 is provided between the node va and the output terminal VOUT, and performs phase compensation to prevent oscillation of the output voltage VOUT.

  FIG. 2 is a diagram illustrating an example of a specific configuration of the amplifier circuit AMP11. The amplifier circuit AMP11 illustrated in FIG. 2 includes transistors MP1 to MP4 that are P channel MOS transistors and transistors MN1 to MN5 that are N channel MOS transistors.

  In the transistor MP1, the source is connected to the power supply voltage terminal VCC, and the drain and gate are connected to the drain of the transistor MN1. In the transistor MN1, the source is connected to the drain of the transistor MN5, and the gate is connected to the inverting input terminal (in−). In the transistor MP2, the source is connected to the power supply voltage terminal VCC, and the drain and gate are connected to the drain of the transistor MN2. In the transistor MN2, the source is connected to the drain of the transistor MN5, and the gate is connected to the non-inverting input terminal (in +). In the transistor MN5, the source is connected to the ground voltage terminal GND, and the bias voltage Vbn11 is supplied to the gate.

  In the transistor MP3, the source is connected to the power supply voltage terminal VCC, the drain is connected to the drain and gate of the transistor MN3, and the gate is connected to the gate of the transistor MP1. In the transistor MN3, the source is connected to the ground voltage terminal GND, and the gate is connected to the gate of the transistor MN4. In the transistor MP4, the source is connected to the power supply voltage terminal VCC, the drain is connected to the drain of the transistor MN4, and the gate is connected to the gate of the transistor MP2. In the transistor MN4, the source is connected to the ground voltage terminal GND.

  Returning to FIG. 1, the output transistor MP11 generates an output voltage VOUT (voltage of the output terminal VOUT) corresponding to the control signal va (voltage of the node va). The resistance elements R11 and R12 divide the output voltage VOUT and output a feedback signal vfeed. The amplifier circuit AMP11 amplifies the potential difference between the reference voltage vref and the feedback signal vfeed and outputs it as a control signal va.

  For example, when the output voltage VOUT rises from a desired voltage level, the voltage level of the feedback signal vfeed to the amplifier circuit AMP11 increases and becomes larger than the reference voltage vref, so that the amplifier circuit AMP11 sets the voltage level of the control signal va. Raise. As a result, the output voltage VOUT drops. On the other hand, when the output voltage VOUT decreases from the desired voltage level, the voltage level of the feedback signal vfeed to the amplifier circuit AMP11 decreases and becomes smaller than the reference voltage vref. Therefore, the amplifier circuit AMP11 reduces the voltage level of the control signal va. Lower. As a result, the output voltage VOUT rises. In this way, the output voltage VOUT is maintained at a desired voltage level.

  In the phase compensator 11, the AC voltage source A11 provides a fluctuation component of the output voltage VOUT to the capacitor C11. The capacitor C11 generates a feedback current (first current) iA corresponding to the fluctuation of the output voltage VOUT. The current amplifier 12 amplifies the feedback current iA generated by the capacitor C11 to generate a feedback current (second current) iB, and superimposes the feedback current iB on the control signal va. In other words, the current amplifying unit 12 amplifies the feedback current iA generated by the capacitor C11 to generate the feedback current iB, and feeds back the feedback current iB to the gate (node va) of the output transistor MP11.

  As described above, in the semiconductor integrated circuit 1 according to this embodiment, the feedback current generated by the phase compensation capacitor is amplified by the current amplifying unit and fed back to the gate (node va) of the output transistor. Thereby, in the semiconductor integrated circuit 1 according to the present embodiment, the scale of the phase compensation capacitor can be made smaller than before. As a result, the semiconductor integrated circuit 1 according to the present embodiment can suppress an increase in circuit scale.

  In the second and subsequent embodiments, specific configuration examples of the semiconductor integrated circuit 1 will be described.

<Embodiment 2>
FIG. 3 is a circuit diagram of a configuration example of the semiconductor integrated circuit 2 according to the second embodiment. A semiconductor integrated circuit 2 shown in FIG. 3 shows a specific configuration example of the semiconductor integrated circuit 1 shown in FIG.

  The semiconductor integrated circuit 2 shown in FIG. 3 includes, as the phase compensation unit 11, a transistor (first transistor) MP21, a transistor (second transistor) MP22, a transistor (first constant current transistor) MN21, and a transistor (second constant current transistor). Current transistor) MN22, transistor MN23, and capacitor C11. The transistors MP21, MP22, MN21, and MN22 constitute a current amplifying unit (corresponding to the current amplifying unit 12 in FIG. 1). The transistor MN23 constitutes an AC voltage source (corresponding to the AC voltage source A11 in FIG. 1). In the present embodiment, an example will be described in which the transistors MP21 and MP22 are P-channel MOS transistors and the transistors MN21 to MN23 are N-channel MOS transistors.

  In the transistor MP21, the source is connected to the power supply voltage terminal VCC, and the drain and gate are connected to the drain of the transistor MN23. In the transistor MP22, the source is connected to the power supply voltage terminal VCC, the drain is connected to the node va, and the gate is connected to the gate of the transistor MP21. That is, the current mirror circuit is configured by the transistors MP21 and MP22. Therefore, a current corresponding to the current id flowing through the transistor MP21 flows between the source and drain of the transistor MP22. In the following description, a case where a current that is n times the current id flowing through the transistor MP21 flows between the source and drain of the transistor MP22 will be described.

  In the transistor MN23, the source is connected to the node vb, and the gate is connected to the output terminal VOUT. The transistor MN23 functions as a source follower circuit that generates a source voltage (voltage at the node vb) corresponding to the gate voltage (output voltage VOUT).

  In the transistor MN21, the source is connected to the ground voltage terminal GND, the drain is connected to the node vb, and the bias voltage Vbn11 is supplied to the gate. Therefore, a predetermined bias current (first predetermined current) ib flows through the transistor MN21. That is, the transistor MN21 functions as a constant current source for supplying a predetermined bias current ib.

  In the transistor MN22, the source is connected to the ground voltage terminal GND, the drain is connected to the node va, and the bias voltage Vbn11 is supplied to the gate. Therefore, a predetermined bias current (second predetermined current) ia flows through the transistor MN22. That is, the transistor MN22 functions as a constant current source that supplies a predetermined bias current ia.

  One end of the capacitor C11 is connected to the node vb, and the other end of the capacitor C11 is connected to the ground voltage terminal GND. Since the other circuit configuration of the semiconductor integrated circuit 2 is the same as that of the semiconductor integrated circuit 1, the description thereof is omitted.

  Next, the operation of the semiconductor integrated circuit 2 will be described. Since the basic operation of the semiconductor integrated circuit 2 is the same as that of the semiconductor integrated circuit 1, the operation of the phase compensation unit will be mainly described below.

  First, a predetermined bias current ib flows through the transistor MN21 functioning as a constant current source. A current id flows through the transistor MP21.

  The transistor MN23 functioning as a source follower circuit generates a source voltage (voltage of the node vb) corresponding to the output voltage VOUT. Capacitor C11 generates a feedback current ic (corresponding to feedback current iA in FIG. 1) corresponding to a change in voltage at node vb. In other words, the capacitor C11 generates a feedback current ic according to the fluctuation of the output voltage VOUT.

  For example, when there is no change in the output voltage VOUT, the capacitor C11 does not generate the feedback current ic. In other words, when there is no change in the output voltage VOUT, the current value of the feedback current ic shows 0A. In this case, the feedback current id has the same current value as the bias current ib (id = ib).

  On the other hand, when the output voltage VOUT varies, the capacitor C11 generates a feedback current ic according to the variation of the output voltage VOUT (according to the variation of the voltage at the node vb). Here, the feedback current ic generated by the capacitor C11 hardly flows to the transistor MN21 having a high drain resistance, but flows to the transistor MP21. In this case, the current id indicates a current value obtained by adding the bias current ib and the feedback current ic (id = ib + ic).

  A current n times the current id flows through the transistor MP22. On the other hand, a predetermined bias current ia flows through the transistor MN22 functioning as a constant current source.

  For example, when there is no change in the output voltage VOUT, a current (n × ib) that is n times the bias current ib flows through the transistor MP22. Here, in the example of FIG. 3, the predetermined bias current ia flowing through the transistor MN22 is adjusted so as to indicate a current value n times the bias current ib. Therefore, when there is no change in the output voltage VOUT, no current flows through the gate of the output transistor MP11.

  On the other hand, when the output voltage VOUT fluctuates, a current (n × (ib + ic)) that is n times the current obtained by adding the bias current ib and the feedback current ic flows to the transistor MP22. Further, a current ia showing a current value n times the bias current ib flows through the transistor MN22. Therefore, when the output voltage VOUT fluctuates, a difference current (n * ic) between the current flowing through the transistor MP22 and the current flowing through the transistor MN22 flows through the gate of the output transistor MP11. This difference current corresponds to the feedback current iB in FIG. That is, a current obtained by amplifying the feedback current ic generated by the capacitor C11 by n times returns to the gate (node va) of the transistor MP11.

  As described above, the semiconductor integrated circuit 2 according to the present embodiment amplifies the feedback current ic generated by the phase compensation capacitor C11 by n times and feeds it back to the gate (node va) of the output transistor. Thereby, in the semiconductor integrated circuit 2 according to the present embodiment, the scale of the capacitor C11 for phase compensation can be made smaller than before. Considering simply, the semiconductor integrated circuit 2 according to the present embodiment has the capacitor C11 having a capacitance value reduced to 1 / n compared to the semiconductor integrated circuit 200 of FIG. (In actuality, it is necessary to consider the loss gain of the transistor MN23). As a result, the semiconductor integrated circuit 2 according to the present embodiment can suppress an increase in circuit scale.

  Here, in the semiconductor integrated circuit 2 according to the present embodiment, the capacitor C11 is 1 / n times that of the semiconductor integrated circuit 200 shown in FIG. 16, and therefore, equivalent ac characteristics are realized at the node vb. For this purpose, the current flowing through the transistor MN23 may be 1 / √n times.

  The capacitor C11 can be configured with a low withstand voltage capacitor having one end connected to the ground voltage terminal GND. Thereby, an increase in circuit scale is suppressed. On the other hand, in the semiconductor integrated circuits 100 and 200 shown in FIGS. 15 and 16, the capacitor C101 cannot be configured with a low withstand voltage capacity depending on use conditions.

  FIG. 4 is a diagram showing frequency characteristics of the semiconductor integrated circuit 2. 4 also shows the frequency characteristics of the semiconductor integrated circuit 200 shown in FIG. 16 for comparison. In the example of FIG. 4, it is assumed that the capacitors C11 and C101 of the semiconductor integrated circuits 2 and 200 have the same capacitance value. In the following, for the sake of simplicity, only the first pole (dominant pole) and the second pole will be described. However, in reality, there are more than the third pole near the same frequency as the second pole.

  First, the frequency of the first pole of the semiconductor integrated circuit 200 can be expressed as 1 / (2π × gm_MP101 × ro ′ × C ′ × rampout ′). Note that gm_MP101 indicates the current gain of the output transistor MP101. ro ′ represents the parallel resistance of the drain resistance of the output transistor MP101, the resistance elements R101 and R102, and the external additional resistance connected to the output terminal VOUT. C ′ represents the capacitance value of the capacitor C101. Rampout ′ indicates the impedance of the node va ′.

  On the other hand, the frequency of the first pole of the semiconductor integrated circuit 2 can be expressed as 1 / (n × 2π × gm_MP11 × ro × C × rampout). Note that gm_MP11 indicates the current gain of the output transistor MP11. ro represents the parallel resistance of the drain resistance rds_MP11 of the output transistor MP11, the resistance elements R11 and R12, and the external additional resistance connected to the output terminal VOUT. C indicates the capacitance value of the capacitor C11. “rampout” indicates the impedance of the node va.

  When gm_MP101 = gm_M11, ro ′ = ro, C ′ = C, and rampout ′ = rampout, in the semiconductor integrated circuit 2, the first pole has a low frequency of 1 / n times that of the semiconductor integrated circuit 200. You can see that it has moved to. As a result, the phase margin is improved from 0 ° to 45 °.

<Embodiment 3>
FIG. 5 is a circuit diagram of a configuration example of the semiconductor integrated circuit 3 according to the third embodiment. The semiconductor integrated circuit 3 shown in FIG. 5 further includes a transistor (third constant current transistor) MP31 as compared with the semiconductor integrated circuit 2 shown in FIG. This will be specifically described below.

  In the present embodiment, a case where the transistor MP31 is a P-channel MOS transistor will be described as an example. In the transistor MP31, the source is connected to the power supply voltage terminal VCC, the drain is connected to the drain of the transistor MN23, and the bias voltage Vbp11 is supplied to the gate. Therefore, a predetermined bias current (third predetermined current) ie flows through the transistor MP31. That is, the transistor MP31 functions as a constant current source that supplies a predetermined bias current ie. Since the other circuit configuration of the semiconductor integrated circuit 3 is the same as that of the semiconductor integrated circuit 2, the description thereof is omitted.

  Next, the operation of the semiconductor integrated circuit 3 will be described. Since the basic operation of the semiconductor integrated circuit 3 is the same as that of the semiconductor integrated circuit 1, the operation of the phase compensation unit will be mainly described below.

  First, predetermined bias currents ib and ie flow in the transistors MN21 and MP31 that function as constant current sources, respectively. A current id flows through the transistor MP21.

  The transistor MN23 functioning as a source follower circuit generates a source voltage (voltage of the node vb) corresponding to the output voltage VOUT. Capacitor C11 generates a feedback current ic corresponding to a change in voltage at node vb. In other words, the capacitor C11 generates a feedback current ic according to the fluctuation of the output voltage VOUT.

  For example, when there is no change in the output voltage VOUT, the capacitor C11 does not generate the feedback current ic. In other words, when there is no change in the output voltage VOUT, the current value of the feedback current ic shows 0A. In this case, the current id indicates a current value of a difference between the bias current ib and the bias current ie (id = ib−ie).

  On the other hand, when the output voltage VOUT varies, the capacitor C11 generates a feedback current ic according to the variation of the output voltage VOUT (according to the variation of the voltage at the node vb). Here, the feedback current ic generated by the capacitor C11 hardly flows to the transistors MN21 and MP31 having a high drain resistance but flows to the transistor MP21. In this case, the current id indicates a current value obtained by adding the feedback current ic to the current value (ib−ie) (id = ib + ic−ie).

  A current n times the current id flows through the transistor MP22. On the other hand, a predetermined bias current ia flows through the transistor MN22 functioning as a constant current source.

  For example, when there is no change in the output voltage VOUT, a current (n × (ib−ie)) that is n times the current (ib−ie) flows through the transistor MP22. Here, in the example of FIG. 5, the predetermined bias current ia flowing through the transistor MN22 is adjusted to show the same value as the current (n × (ib−ie)). Therefore, when there is no change in the output voltage VOUT, no current flows through the gate of the output transistor MP11.

  On the other hand, when the output voltage VOUT fluctuates, a current (n × (ib + ic−ie)) that is n times the current (ib + ic−ie) flows through the transistor MP22. In addition, a bias current ia having the same value as the current (n × (ib−ie)) flows through the transistor MN22. Therefore, when the output voltage VOUT fluctuates, a difference current (n * ic) between the current flowing through the transistor MP22 and the current flowing through the transistor MN22 flows through the gate of the output transistor MP11. That is, a current obtained by amplifying the feedback current ic generated by the capacitor C11 by n times returns to the gate (node va) of the transistor MP11.

  As described above, the semiconductor integrated circuit 3 according to the present embodiment can achieve the same effects as those of the second embodiment. Furthermore, the semiconductor integrated circuit 3 according to the present embodiment includes the transistor MP31 in parallel with the transistor MP21, so that the bias current ib component flowing through the transistor MP21 is relatively small. Thereby, the semiconductor integrated circuit 3 according to the present embodiment can reduce the bias current ia flowing through the transistors MP22 and MN22 without decreasing the amplified feedback current (n × ic). As a result, an increase in current consumption is suppressed. Along with this, an increase in the input conversion offset voltage of the amplifier circuit AMP11 is also suppressed.

  Here, by increasing the bias current ie flowing through the transistor MP31 to the same level as the bias current ib flowing through the transistor MN21 and reducing the bias current ib component flowing through the transistor MP21 as much as possible, the increase in current consumption is further suppressed. The Along with this, an increase in the input conversion offset voltage of the amplifier circuit AMP11 is further suppressed.

  In the semiconductor integrated circuit 3 according to the present embodiment, the capacitor C11 is 1 / n times that of the semiconductor integrated circuit 200 shown in FIG. 16, so that the equivalent ac characteristic is realized at the node vb. The current flowing through the transistor MN23 may be 1 / √n times. If the ratio of the bias currents ia and ib is 1: 1, the current consumption is suppressed to 2 / √n times the conventional value. For example, when n = 20, the current consumption is suppressed to about half of the conventional one. Accordingly, the input conversion offset voltage of the amplifier circuit AMP11 is also suppressed to 1 / √n times.

  Next, details of setting the bias currents ia, ib, and ie will be described using calculation formulas. Hereinafter, the ratio of the bias currents ia and ib is a: b. Further, a ratio of bias current components flowing through the transistors MP22, MP21, and MP31 is a: d: e. At this time, the following formulas (1), (2), and (3) hold.

ib = id + ie (1)
id: ia = d: a (2)
ia: ib = a: b (3)

  From the formula (2), the following formula (4) is established.

  id = (d / a) × ia (4)

  From the expression (3), the following expression (5) is established.

  ib = (b / a) × ia (5)

  When Expressions (4) and (5) are substituted into Expression (1), the following Expression (6) is obtained.

  (B / a) × ia = (d / a) × ia + ie (6)

  Here, since a: d = n: 1, the formula (6) is expressed as the following formula (7).

  (B / a) × ia = (1 / n) × ia + ie (7)

  Assuming that a: b = 1: 1, the expression (7) is expressed as the following expression (8).

  ia = (1 / n) × ia + ie (8)

  From the equation (8), in order to set the ratio of the bias currents ia and ib to 1: 1, it may be designed so as to satisfy ie = {(n−1) / n} × ia.

  Although the case where the ratio of the bias currents ia and ib is 1: 1 has been described as an example here, the present invention is not limited to this. The ratio of the bias currents ia and ib can be arbitrarily changed. By adjusting the ratio of the bias currents ia and ib and the current mirror ratio n, it is possible to improve the respective characteristics of the DC characteristic, the AC characteristic, and the TRAN characteristic.

<Embodiment 4>
FIG. 6 is a circuit diagram of a configuration example of the semiconductor integrated circuit 3a according to the fourth embodiment. In the semiconductor integrated circuit 3a shown in FIG. 6, the conductivity type (P type, N type) of each transistor is changed to a different conductivity type as compared with the semiconductor integrated circuit 3 shown in FIG. Further, the connection relationship between the power supply voltage terminal VCC and the ground voltage terminal GND is reversed. That is, in this embodiment, the VCC reference output voltage VOUT is generated instead of the GND reference.

  The semiconductor integrated circuit 3a shown in FIG. 6 includes an output transistor MN11a, an amplifier circuit AMP11a, resistance elements R11a and R12a, transistors MN21a, MN22a, MP21a, MP22a, MP23a, and MN31a, and a capacitor C11a.

  Here, the output transistor MN11a, the amplifier circuit AMP11a, the resistance elements R11a and R12a, the transistors MN21a, MN22a, MP21a, MP22a, MP23a, MN31a, and the capacitor C11a are respectively the output transistor MP11, the amplification circuit AMP11, and the resistance element in FIG. This corresponds to R11, R12, transistors MP21, MP22, MN21, MN22, MN23, MP31 and capacitor C11.

  The semiconductor integrated circuit 3a according to the present embodiment can achieve the same effects as the semiconductor integrated circuit 3 according to the third embodiment. The same applies to the other embodiments.

<Embodiment 5>
FIG. 7 is a circuit diagram of a configuration example of the semiconductor integrated circuit 4 according to the fifth embodiment. The semiconductor integrated circuit 4 shown in FIG. 7 further includes a resistance element R41 between the node vb and the capacitor C11, as compared with the semiconductor integrated circuit 3 shown in FIG. Since other circuit configurations and operations of the semiconductor integrated circuit 4 are the same as those of the semiconductor integrated circuit 3, the description thereof is omitted.

  The semiconductor integrated circuit 4 according to the present embodiment includes the resistance element R41, so that a zero point (a zero point that can return the advanced phase) can be generated on the left half plane in the complex plane. As a result, the semiconductor integrated circuit 4 according to the present embodiment can set the upper limit of the feedback current (n × ic) for phase compensation, so that the stability of the path of the feedback current for phase compensation is improved. The PSRR characteristics can be improved.

  In the present embodiment, the case where the resistance element R41 is added to the semiconductor integrated circuit 3 shown in FIG. 5 has been described, but the present invention is not limited to this. The resistor element R41 can be added as appropriate to the semiconductor integrated circuits according to the other embodiments.

<Embodiment 6>
FIG. 8 is a circuit diagram of a configuration example of the semiconductor integrated circuit 5 according to the sixth embodiment. The semiconductor integrated circuit 5 shown in FIG. 8 further includes a gain boost circuit GB51 as compared with the semiconductor integrated circuit 3 shown in FIG. This will be specifically described below.

  The gain boost circuit GB51 includes transistors MN51 and MN52 and an amplifier circuit (second amplifier unit) AMP51. In the present embodiment, a case where the transistors MN51 and MN52 are N-channel MOS transistors will be described as an example.

  In the transistor MN51, the drain is connected to the power supply voltage terminal VCC, the source is connected to the node vc, and the output voltage VOUT is supplied to the gate. In the transistor MN52, the drain is connected to the node vc, the source is connected to the ground voltage terminal GND, and the bias voltage Vbn11 is supplied to the gate. In the amplifier circuit AMP51, the inverting input terminal is connected to the node vb, the non-inverting input terminal is connected to the node vc, and the output terminal is connected to the gate of the transistor MN23.

  FIG. 9 is a diagram illustrating an example of a specific configuration of the amplifier circuit AMP51. The amplifier circuit AMP51 shown in FIG. 9 includes transistors MN6 to MN9 that are N channel MOS transistors and transistors MP5 to MP9 that are P channel MOS transistors.

  In the transistor MN6, the source is connected to the ground voltage terminal GND, and the drain and gate are connected to the drain of the transistor MP5. In the transistor MP5, the source is connected to the drain of the transistor MP9, and the gate is connected to the inverting input terminal (in−). In the transistor MN7, the source is connected to the ground voltage terminal GND, and the drain and gate are connected to the drain of the transistor MP6. In the transistor MP6, the source is connected to the drain of the transistor MP9, and the gate is connected to the non-inverting input terminal (in +). In the transistor MP9, the source is connected to the power supply voltage terminal VCC, and the bias voltage Vbp11 is supplied to the gate.

  In the transistor MN8, the source is connected to the ground voltage terminal GND, the drain is connected to the drain and gate of the transistor MP7, and the gate is connected to the gate of the transistor MN6. In the transistor MP7, the source is connected to the power supply voltage terminal VCC, and the gate is connected to the gate of the transistor MP8. In the transistor MN9, the source is connected to the ground voltage terminal GND, the drain is connected to the drain of the transistor MP8, and the gate is connected to the gate of the transistor MN7. In the transistor MP8, the source is connected to the power supply voltage terminal VCC.

  Returning to FIG. 8, the other circuit configuration of the semiconductor integrated circuit 5 is the same as that of the semiconductor integrated circuit 3 shown in FIG.

  The transistors MN51 and MN52 constitute a level shifter, shift the output voltage VOUT to a low voltage level, and output it from the node vc. The amplifier circuit AMP51 amplifies the potential difference between the voltage at the node vc and the voltage at the node vb and outputs the amplified difference to the gate of the transistor MN23. That is, the amplifier circuit AMP51 boosts the gain of the transistor MN23.

  As a result, the transconductance gm of the transistor MN23 increases, so that the impedance of the node vb decreases. Thereby, the current that needs to flow through the transistor MN23 is further reduced. That is, the bias currents ia and ib can be further reduced. As a result, an increase in current consumption is further suppressed, and accordingly, an increase in input conversion offset voltage of the amplifier circuit AMP11 is further suppressed.

  Further, since the semiconductor integrated circuit 5 according to the present embodiment can reduce the bias currents ia and ib as described above, the current mirror ratio n can be further increased without increasing the current consumption. Thereby, the semiconductor integrated circuit 5 according to the present embodiment can further reduce the scale of the capacitor C11.

  Note that the transistors MN51 and MN52 may not be provided if the output voltage VOUT does not need to be shifted to a low level (see FIG. 10).

  In the present embodiment, the case where the gain boost circuit GB51 is added to the semiconductor integrated circuit 5 shown in FIG. 5 has been described, but the present invention is not limited to this. The gain boost circuit GB51 can be added as appropriate to the semiconductor integrated circuits according to the other embodiments.

<Embodiment 7>
FIG. 11 is a circuit diagram of a configuration example of the semiconductor integrated circuit 6 according to the seventh embodiment. The semiconductor integrated circuit 6 shown in FIG. 11 further includes a transistor (fourth constant current transistor) MN61 and a transistor (fifth constant current transistor) MN62, as compared with the semiconductor integrated circuit 3 shown in FIG.

  In the present embodiment, a case where the transistors MN61 and MN62 are N-channel MOS transistors will be described as an example. The transistors MN61 and MN62 are cascode-connected to the transistors MN21 and MN22, respectively. More specifically, the transistor MN61 is provided between the node vb and the transistor MN21, and the bias voltage Vbn61 is supplied to the gate. The transistor MN62 is provided between the node va and the transistor MN22, and a bias voltage Vbn61 is supplied to the gate. Since the other circuit configuration of the semiconductor integrated circuit 6 is the same as that of the semiconductor integrated circuit 3, the description thereof is omitted.

  As a result, the drain resistances of the transistors MN21 and MN22 increase, so that fluctuations in the bias currents ia and ib due to changes in the process, power supply voltage VCC, temperature, and the like are suppressed. Thereby, the fluctuation of the error current flowing into the output terminal of the amplifier circuit AMP11 is reduced, so that the input conversion offset voltage of the amplifier circuit AMP11 is effectively suppressed.

  Although the case where the transistors MN61 and MN62 are added to the semiconductor integrated circuit 5 shown in FIG. 5 has been described in the present embodiment, the present invention is not limited to this. The transistors MN61 and MN62 can be added as appropriate to the semiconductor integrated circuits according to other embodiments.

<Eighth embodiment>
FIG. 12 is a circuit diagram of a configuration example of the semiconductor integrated circuit 7 according to the eighth embodiment. The semiconductor integrated circuit 7 shown in FIG. 12 includes the resistor element R41, the gain boost circuit GB51, and the transistors MN61 and MN62. Description of the specific configuration of the semiconductor integrated circuit 7 is omitted.

  In the present embodiment, the case where the semiconductor integrated circuit 7 includes the resistor element R41, the gain boost circuit GB51, and the transistors MN61 and MN62 has been described as an example. However, the present invention is not limited to this. The semiconductor integrated circuit 7 can be appropriately changed to a configuration including any one or two of the resistance element R41, the gain boost circuit GB51, and the transistors MN61 and MN62.

  FIG. 13 is a circuit diagram showing the semiconductor integrated circuit 7 in which the first configuration example of the bias voltage generation unit is clearly shown as a semiconductor integrated circuit 7a. The bias voltage generation unit includes a constant current source I71 and transistors MN71 to MN73, MP71, MP72. FIG. 14 shows a semiconductor integrated circuit 7b in which a second configuration example of the bias voltage generator is added to the semiconductor integrated circuit 7. The bias voltage generation unit includes a constant current source I71 and transistors MN71, MN73, and MP72. It is assumed that the transistors MN71 to MN73 are N channel MOS transistors and the transistors MP71 and MP72 are P channel MOS transistors.

  As described above, in the semiconductor integrated circuit according to the above-described embodiment, the feedback current generated by the phase compensation capacitor is amplified by the current amplification unit and fed back to the gate (node va) of the output transistor. As a result, the semiconductor integrated circuit according to the above embodiment can reduce the scale of the phase compensation capacitor as compared with the conventional case. As a result, the semiconductor integrated circuit according to the above embodiment can suppress an increase in circuit scale.

  Furthermore, the semiconductor integrated circuit according to the above embodiment includes the transistor MP31 in parallel with the transistor MP21, so that the bias current ib component flowing through the transistor MP21 is relatively small. Accordingly, the semiconductor integrated circuit according to the above embodiment can reduce the bias current ia flowing through the transistors MP22 and MN22 without reducing the amplified feedback current. As a result, an increase in current consumption is suppressed. Along with this, an increase in the input conversion offset voltage of the amplifier circuit AMP11 is also suppressed.

  The semiconductor integrated circuit according to the above-described embodiment is particularly effective when adopting a low-dropout configuration that has recently been highly demanded.

(Comparison with conventional technology)
The configuration disclosed in Patent Document 2 does not have a configuration (for example, a current mirror circuit) that amplifies the phase compensation feedback current. Therefore, in this configuration, there is a problem that the scale of the phase compensation capacitor is increased. On the other hand, such a problem does not occur in the semiconductor integrated circuit according to the above embodiment.

  The configuration disclosed in Patent Document 3 does not perform phase compensation using the mirror effect. On the other hand, the semiconductor integrated circuit according to the above embodiment has a configuration that performs phase compensation using the mirror effect and amplifies the phase compensation feedback current. Further, the feedback destination of the phase compensation feedback current differs between the configuration disclosed in Patent Document 3 and the configuration of the semiconductor integrated circuit according to the above embodiment. In short, the circuit configuration is completely different between the configuration disclosed in Patent Document 3 and the configuration of the semiconductor integrated circuit according to the above embodiment.

  In the configuration disclosed in Patent Document 4, the phase compensation feedback current is supplied to the output side of the current mirror circuit. That is, in this current mirror circuit, the phase compensation feedback current is not amplified. On the other hand, in the semiconductor integrated circuit according to the above embodiment, the phase compensation feedback current is amplified by the current mirror circuit. Therefore, the semiconductor integrated circuit according to the above embodiment can further reduce the scale of the phase compensation capacitor.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  In the above embodiment, the case where the semiconductor integrated circuits 1 to 7, 1a, 3a, 5a, 7a, and 7b are series regulators has been described as an example. However, the present invention is not limited to this. The semiconductor integrated circuits 1 to 7, 1a, 3a, 5a, 7a, and 7b may be amplifier circuits.

  In the above embodiment, the case where the semiconductor integrated circuits 1 to 7, 1a, 3a, 5a, 7a, and 7b include the resistance elements R11 and R12 has been described as an example, but the present invention is not limited to this. If it is not necessary to divide the output voltage VOUT, the semiconductor integrated circuits 1 to 7, 1a, 3a, 5a, 7a, and 7b can be appropriately changed to a configuration that does not include the resistance elements R11 and R12.

1 to 7, 1a, 3a, 5a, 7a, 7b Semiconductor integrated circuit 11 Phase compensation unit 12 Current amplification unit A11 AC voltage source AMP11, AMP11a, AMP51 Amplification circuit C11, C11a Phase compensation capacitor GB51, GB51a Gain boost circuit I71 constant Current sources MN1 to MN9 N channel MOS transistors MN21 to MN23, MN51, MN52 N channel MOS transistors MN61, MN62, MN71 to MN73 N channel MOS transistors MN11a, MN21a, MN22a, MN31a N channel MOS transistors MP1 to MP9 P channel MOS transistors MP11 , MP21, MP22 P-channel MOS transistors MP21a, MP22a, MP23a P-channel MOS transistors MP31, M 71, MP72 P-channel MOS transistor R11, R11a, R12, R12a, R41 resistive element va, vb, vc node

Claims (8)

An output transistor that generates an output voltage according to the control signal;
A first amplifier that amplifies a potential difference between a feedback signal having a voltage level corresponding to the output voltage and a reference voltage and outputs the amplified signal as the control signal;
A capacitor that generates a first current in accordance with a change in the output voltage;
A current amplifying unit that amplifies the first current to generate a second current and superimposes the second current on the control signal ;
The current amplifier is
A first transistor;
A second transistor that is current-mirror connected to the first transistor and that flows a current corresponding to a current that flows through the first transistor;
A first constant current transistor connected in series to the first transistor and through which a first predetermined current flows;
A second constant current transistor connected in series to the second transistor and through which a second predetermined current flows,
A source follower circuit provided between the first transistor and the first constant current transistor;
A second amplifying unit that amplifies a potential difference between a voltage corresponding to the output voltage and a source voltage of the source follower circuit, and supplies the amplified voltage difference to a gate of the source follower circuit;
The capacitor generates the first current according to a change in a source voltage of the source follower circuit,
The first current generated by the capacitor is supplied to a node between the first transistor and the first constant current transistor;
The current amplifying unit generates a difference current between the current flowing through the second transistor and the second predetermined current flowing through the second constant current transistor as the second current;
Semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1, further comprising a resistive element between the capacitor and the node. A fourth constant current transistor that is cascode-connected to the first constant current transistor and through which the first predetermined current flows;
The second is cascode connected to the constant current transistor, the semiconductor integrated circuit according to claim 1 and a fifth constant-current transistor second predetermined current flows, further comprising a. An output transistor that generates an output voltage according to the control signal;
A first amplifier that amplifies a potential difference between a feedback signal having a voltage level corresponding to the output voltage and a reference voltage and outputs the amplified signal as the control signal;
A capacitor that generates a first current in accordance with a change in the output voltage;
A current amplifying unit that amplifies the first current to generate a second current and superimposes the second current on the control signal ;
The current amplifier is
A first transistor;
A second transistor that is current-mirror connected to the first transistor and that flows a current corresponding to a current that flows through the first transistor;
A first constant current transistor connected in series to the first transistor and through which a first predetermined current flows;
A second constant current transistor connected in series to the second transistor and through which a second predetermined current flows;
A third constant current transistor connected in parallel to the first transistor and through which a third predetermined current flows,
The first current generated by the capacitor is supplied to a node between the first transistor, the third constant current transistor, and the first constant current transistor;
The current amplifying unit generates a difference current between the current flowing through the second transistor and the second predetermined current flowing through the second constant current transistor as the second current;
Semiconductor integrated circuit. A source follower circuit provided between the first transistor, the third constant current transistor, and the first constant current transistor, wherein the output voltage is applied to a gate;
5. The semiconductor integrated circuit according to claim 4 , wherein the capacitor generates the first current according to a change in a source voltage of the source follower circuit. The semiconductor integrated circuit according to claim 5 , further comprising a resistance element between the capacitor and the node. 6. The semiconductor integrated circuit according to claim 5 , further comprising a second amplifying unit that amplifies a potential difference between a voltage corresponding to the output voltage and a source voltage of the source follower circuit and supplies the amplified voltage difference to a gate of the source follower circuit. circuit. A fourth constant current transistor that is cascode-connected to the first constant current transistor and through which the first predetermined current flows;
The semiconductor integrated circuit according to claim 5 , further comprising: a fifth constant current transistor that is cascode-connected to the second constant current transistor and through which the second predetermined current flows.

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