JP2008300587A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the heat-radiating property of a formed semiconductor device by the formation of an aperture penetrating between the main/back sides of a tab in the outer periphery of the tab. <P>SOLUTION: In a resin sealed type semiconductor device 1, a tab 3a to mount a semiconductor chip 2 is formed in the shape of a frame. This tab 3a of the shape of the frame has integrally an inner periphery portion in which the semiconductor chip 2 planarly overlaps and an outer periphery portion located in the perimeter of the semiconductor chip 2. The width of the outer periphery portion of the tab 3a is wider than the width of the inner periphery portion of the tab 3a. Moreover, in the outer periphery portion of the tab 3a, apertures S1, S2 penetrating between the main/back sides of the tab 3a are formed. Thereby, the heat-radiating property of the semiconductor device 1 can be improved. Since the apertures S1, S2 are formed, the reflow crack resistance of the semiconductor device 1 can be raised. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and particularly relates to a technique effective when applied to a heat dissipation technique of a semiconductor device using a lead frame.

  For example, semiconductor devices used in automobile electronic devices are required to have higher mounting reliability than semiconductor devices used in general electronic devices from the viewpoint of being able to withstand high-temperature conditions and vibrations. . The package configuration of a semiconductor device includes a so-called BGA (Ball Grid Array) type semiconductor device in which a plurality of bump electrodes (external terminals) are arranged on the back surface. In the case of this type of semiconductor device, the bump electrode is on the back surface. Since it is arranged, it is difficult to confirm the bonding state of the bump electrode after mounting the semiconductor device, and there is anxiety in securing high mounting reliability.

  On the other hand, in the case of a QFP (Quad Flat Package) type or QFN (Quad Flat Non leaded Package) type semiconductor device, the external terminals are formed along the outer periphery of the semiconductor device. The terminal bonding state can be confirmed well. For this reason, QFP type and QFN type semiconductor devices are excellent in securing high mounting reliability and are suitable for use in automobiles. Further, in the case of a QFP type or QFN type semiconductor device, since a lead frame is used instead of a wiring board used in a BGA type semiconductor device, there is an advantage that the manufacturing cost can be reduced.

  A semiconductor device using such a lead frame is described in, for example, Japanese Patent Application Laid-Open No. 2007-73763 (Patent Document 1), and the planar dimensions of the tab (chip mounting portion) of the lead frame are mounted thereon. A so-called large tab configuration that is slightly larger than the planar dimension of the semiconductor chip is disclosed.

  However, if the tab dimension of the tab is larger than the plane dimension of the semiconductor chip, it is caused by heat treatment during mounting of the semiconductor device due to voids existing at the interface between the tab and the resin sealing body or moisture accumulated therein. Cracks are likely to occur in the resin sealing body. For this reason, for example, in Japanese Patent Laid-Open No. 10-326859 (Patent Document 2), the planar dimension of the tab of the lead frame is made larger than the planar dimension of the semiconductor chip mounted thereon, for reasons of improving the crack resistance. A so-called small tab configuration is disclosed.

However, when the planar dimension of the tab is smaller than that of the semiconductor chip, heat dissipation such as heat generated in the semiconductor chip becomes lower than that of the large tab configuration. Therefore, from the viewpoint of improving both crack resistance and heat dissipation, for example, Japanese Patent Application Laid-Open No. 2007-53195 (Patent Document 3) discloses a so-called frame in which the planar shape of a tab of a lead frame is formed in a frame shape. A tab configuration is disclosed.
JP 2007-73763 A Japanese Patent Laid-Open No. 10-326859 JP 2007-53195 A

  By the way, for example, in semiconductor devices used for automobile navigation devices and audio devices, the number of operation processes increases and the operation speed increases as the number of functions increases, and the semiconductor chip itself generates heat during operation. It becomes easy.

  In the case of the above-described frame tab of Patent Document 3, the heat dissipation is improved as compared with the small tab of Patent Document 2, but the heat dissipation is not sufficiently obtained as compared with the large tab of Patent Document 1.

  It is known that heat generated in a semiconductor chip is dissipated through a tab or the like, and is also dissipated outside through a lead through a conductive member connected to the semiconductor chip. As the number of external terminals increases with functionalization, the tip of the lead (tip on the tab side) cannot be sufficiently close to the semiconductor chip, and the lead is separated from the semiconductor chip, improving heat dissipation. Is difficult.

  The objective of this invention is providing the technique which can improve the heat dissipation of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the plurality of inventions disclosed in the present application, an outline of an embodiment will be briefly described as follows.

  That is, in this embodiment, in the frame-shaped chip mounting portion on which the semiconductor chip is mounted, the width of the outer peripheral portion located around the semiconductor chip is larger than the width of the inner peripheral portion where the semiconductor chips overlap in a plane. Widely, an opening that penetrates the upper and lower surfaces is formed in the outer peripheral portion.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, in the frame-shaped chip mounting portion on which the semiconductor chip is mounted, the width of the outer peripheral portion located around the semiconductor chip is wider than the width of the inner peripheral portion where the semiconductor chip overlaps in plan view, Since the opening part which penetrates the upper and lower surfaces is formed, the heat dissipation of the semiconductor device can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
1 is a plan view of the semiconductor device according to the first embodiment, and FIG. 2 is a cross-sectional view taken along line X1-X1 in FIG. In FIG. 1, for the sake of explanation, the inside of the semiconductor device is shown through.

  A semiconductor device 1 according to the first embodiment is an electronic component used in, for example, an audio device or a navigation device mounted on an automobile, and includes a semiconductor chip 2, a tab (chip mounting portion) 3a, and a tab suspension lead 3b. , A plurality of leads 3 c, a fixing tape 4, a bonding wire (hereinafter simply referred to as a wire) 5, and a sealing body 6.

  The semiconductor chip 2 is formed using, for example, a semiconductor material such as silicon (Si) single crystal as a substrate, and has a main surface (first main surface) and a back surface (first surface) located on opposite sides along the thickness direction. 2 main surfaces).

  An integrated circuit such as a serial sound interface (SSI) circuit and a CDROM (Compact Disc Read Only Memory) decoder circuit is formed on the main surface of the semiconductor chip 2.

  A plurality of bonding pads (hereinafter simply referred to as pads) are arranged along the outer periphery of the semiconductor chip 2 near the outer periphery of the main surface of the semiconductor chip 2 (not shown). The plurality of pads (electrodes) are electrically connected to the integrated circuit.

  The tab (die pad, chip mounting portion) 3a, the plurality of tab suspension leads (suspension leads) 3b, and the plurality of leads 3c are formed from a part of the same lead frame, and are opposite to each other along the thickness direction. And a back surface (second main surface). The material of the tab 3a, the plurality of tab suspension leads 3b, and the plurality of leads 3c is formed using a metal material such as copper (Cu) as a base material. However, this material is not limited to copper, and can be variously changed. Needless to say, the material may be formed of an iron-based metal material such as 42 alloy. In this case, a metal material such as copper is most effective.

  The tab 3a has a so-called frame tab configuration in which a planar shape is formed in a frame shape having a quadrangular shape. The semiconductor chip 2 is mounted on the main surface of the tab 3a in a state where the back surface is bonded to a part of the main surface of the tab 3a with an adhesive. The tab 3a is formed to be lower than the main surface of the lead 3c. In other words, the main surface of the tab 3a is formed so as to be located on the back side of the main surface of the lead 3c. That is, the tab 3a and the lead 3c are formed so as to be separated from each other in the thickness direction. The configuration of the tab 3a will be described in detail later.

  The plurality of tab suspension leads 3b are members that support the tab 3a on the lead frame. The tab suspension leads 3b are formed in a state of extending radially from the four corners of the tab 3a along the direction of the outer periphery of the semiconductor device 1. The tab 3a and the plurality of tab suspension leads 3b are integrally formed. Reference numeral 3b1 denotes a bent portion formed on the tab suspension lead 3b in order to lower the tab 3a below the main surface of the lead. In the first embodiment, the bent portion 3b1 is formed at a position closer to the tab 3a than the inner end (tip, tip portion on the tab 3a side) of the lead (inner lead portion) 3c. This will also be described in detail later.

  The plurality of leads 3 c are members for drawing out the electrodes (the pads) of the integrated circuit of the semiconductor chip 2 to the outside of the sealing body 6. The plurality of leads 3 c are formed in a state of extending radially from the center of the tab 3 a toward the outer periphery of the semiconductor device 1. Each lead 3c is arranged side by side between the tab suspension leads 3b adjacent to each other while being insulated and separated from each other along the outer peripheral direction of the tab 3a.

  The inner end of each lead 3c (the tip on the tab 3a side, the tip of the inner lead portion) is disposed at a position slightly away from the tab 3a. The tips of the plurality of leads 3c corresponding to the respective sides of the tab 3a are formed in a plane V shape. That is, the inner end of each lead 3c is separated from the tab 3a as it approaches the center of the side of the tab 3a. This is to prevent the wire 5 connected to the lead 3c arranged on the tab suspension lead 3b side from coming into contact with the inner lead 3c or the wire 5 connected thereto. Another reason is to make the lengths of the plurality of wires 5 electrically connecting the plurality of bonding pads of the semiconductor chip 2 and the plurality of leads 3c uniform. Note that the inner end of each lead 3c and the portion to which the wire 5 is connected (wire connecting portion) is subjected to, for example, nickel (Ni) base gold (Au) plating.

  In addition, the outer end opposite to the inner end of the lead 3 c protrudes from the four side surfaces of the sealing body 6. The lead 3c portion (outer lead portion) protruding from the side surface of the sealing body 6 is formed in a gull wing shape, for example. That is, the semiconductor device 1 according to the first embodiment has, for example, a QFP (Quad Flat Package) configuration.

  The fixing tape (lead fixing tape) 4 is a member for fixing the tip portions of the plurality of leads 3c so as not to flutter during the wire bonding process. The fixing tape 4 is formed of an insulating material such as polyimide resin, for example, and is formed on the main surface of the plurality of leads 3c in a state of being formed in a planar frame shape so as to mechanically connect the plurality of leads 3c to each other. Is pasted. The frame width (short direction dimension) of the fixed tape 4 is, for example, 1.0 mm to 1.5 mm. Here, when the width of the fixing tape 4 is narrower than 1.0 mm, the strength of the fixing tape 4 itself is reduced, and it is difficult to suppress the fluttering of the plurality of leads 3c. Further, since the fixing tape 4 is made of, for example, polyimide resin, the adhesiveness with the resin constituting the sealing body is lower than the adhesiveness between the resin and the lead frame. Therefore, when the width of the fixing tape is thicker than 1.5 mm, a problem that the resin sealing body peels off at the interface with the fixing tape 4 easily occurs, and the reliability of the semiconductor device is lowered.

  The wire 5 is a member that electrically connects the pad of the semiconductor chip 2 and the plurality of leads 3c. The wire 5 is made of a metal such as gold (Au). The plurality of pads of the semiconductor chip 2 are electrically connected to the plurality of leads 3c through the plurality of wires 5, and are further drawn out of the sealing body 6 through the plurality of leads 3c.

  The sealing body 6 is made of, for example, an insulating material such as an epoxy resin, and the appearance thereof is formed in a flat plate-like thin plate shape, for example. The semiconductor chip 2, the tab 3 a, the plurality of tab suspension leads 3 b, a part of the plurality of leads 3 c, the fixing tape 4 and the plurality of wires 5 are sealed with a sealing body 6.

  Next, the tab 3a and its periphery will be described in detail. 3 and 5 are enlarged plan views of main parts of the semiconductor device 1 of FIG. 1, FIG. 4 is a cross-sectional view taken along line X1-X1 in FIG. 3, FIG. 6 is a cross-sectional view taken along line X1-X1 in FIG. It is an enlarged plan view of the tab 3a. Note that FIG. 3 shows a state in which the wire 5 is removed for easy viewing of the drawing. Further, FIG. 5 shows a state in which the semiconductor chip 2 and the sealing body 6 are removed for easy viewing of the drawing. 5 and 7 indicate the outer periphery of the semiconductor chip 2.

  In the center of the main surface of the frame-shaped tab 3a, the semiconductor chip 2 is bonded with an adhesive 10 (see FIG. 4) using, for example, silver (Ag) paste (conductive paste) in order to improve the heat dissipation of the semiconductor chip 2. Is mounted (joined). In some cases, Duff (Die Attach Film: hereinafter abbreviated as DAF) is used as the adhesive. However, since the DAF has a structure having adhesive layers on the front and back of a tape base material made of an insulator, it is difficult to efficiently transfer heat generated during operation of the semiconductor chip 2 to the tab as compared with the silver paste. Further, since the DAF is attached to the entire back surface of the semiconductor chip 2, the DAF on the back surface of the semiconductor chip 2 and the resin of the sealing body 6 are in direct contact within the frame of the tab 3a, and the sealing of the contact portion is performed. The adhesion (adhesion) of the body 6 is reduced. As a result, the reflow crack resistance of the semiconductor device 1 is reduced. That is, cracks may occur in the sealing body 6 starting from a portion where the resin adhesion of the sealing body 6 is low due to heat when the semiconductor device 1 is mounted on the wiring board.

  On the other hand, when a silver paste is used as the adhesive material 10 as in the first embodiment, it is possible to improve the dissipation of heat generated during the operation of the semiconductor chip 2 as compared with the case where DAF is used. Moreover, since the back surface of the semiconductor chip 2 is in direct contact with the resin constituting the sealing body 6 in the frame of the tab 3a by using a silver paste material as the adhesive material 10, the adhesive property of the sealing body 6 in the contacted portion thereof. (Adhesion) can be improved. For this reason, it is possible to reduce the occurrence of cracks in the sealing body 6 when the semiconductor device 1 is mounted. That is, the reflow crack resistance of the semiconductor device 1 can be improved.

  Here, in the first embodiment, for convenience, the portion of the frame-like tab 3a where the semiconductor chip 2 overlaps in a plane is referred to as an inner peripheral portion 3a1, and the periphery thereof is referred to as an outer peripheral portion 3a2. That is, in the first embodiment, the tab 3a integrally includes an inner peripheral portion 3a1 where the semiconductor chip 2 overlaps in plan and an outer peripheral portion 3a2 positioned around the semiconductor chip 2 (FIG. 5, FIG. (See FIG. 7).

  When the first direction is a direction from the inner periphery to the outer periphery of the tab 3a (or the semiconductor chip 2) and perpendicular to the side of the tab 3a, the dimension of the outer peripheral portion 3a2 in the first direction. L1 (see FIG. 7) is formed wider than the dimension L2 in the first direction of the inner peripheral portion 3a1. That is, the frame width (dimension L3 = dimension L1 + dimension L2) of the tab 3a is formed wider than the frame width of the frame tab shown in Patent Document 3 described above, for example. The frame width (dimension L3) of the tab 3a is formed wider than the frame width (dimension in the short direction) of the fixed tape 4, for example. The frame width of the tab 3a is equal to or longer than the dimension from the outer periphery of the tab 3a to the inner end of the lead 3c.

  Since the area of the metal portion can be increased by widening the frame width of the tab 3a in this way, the heat dissipation of the semiconductor device 1 (the heat dissipation generated during the operation of the semiconductor chip 2) is improved. Can be made.

  Further, since the distance between the tab 3a and the plurality of leads 3c on the outer periphery of the tab 3a can be shortened by widening the frame width of the tab 3a, the thermal resistance between the tab 3a and the lead 3c can be lowered. . For this reason, since the heat generated during the operation of the semiconductor chip 2 can be dissipated through the leads 3c, the heat dissipation of the semiconductor device 1 can be improved.

  However, if the frame width of the tab 3a is simply increased, the sealing body 6 may be cracked by heat when the semiconductor device 1 is mounted on the wiring board. That is, there is a problem that the reflow crack resistance is lowered. Therefore, in the first embodiment, openings (slits, holes) S (S1, S2) penetrating between the main back surfaces of the tab 3a are formed in the outer peripheral portion 3a2 of the tab 3a. Thereby, a part of the sealing body 6 formed in the opening S can serve as an anchor to improve the reflow crack resistance, so that the occurrence of cracks in the sealing body 6 can be suppressed or prevented. Therefore, the reflow crack resistance of the semiconductor device 1 can be improved.

  In this Embodiment 1, the opening part S is not formed in the inner peripheral part 3a1 of the tab 3a. This is because the conductive paste is used as the adhesive 10 for bonding the semiconductor chip 2 to the tab 3a as described above, so that even if the opening S is formed in the inner peripheral portion 3a1 of the tab 3a, the opening S is conductive. This is because the anchoring effect of the sealing body 6 cannot be obtained sufficiently because it is buried with the paste.

  A plurality of openings S are arranged along the first direction. Here, a case where the openings S are arranged in two rows is illustrated. The first row (inner circumferential side) is the opening S1 (S), and the second row (outer circumferential side) is the opening S2 (S). The openings S may be arranged in one row or three or more rows. However, if the number of the openings S is too large, the planar size of the tab 3a increases and the planar size of the semiconductor device 1 increases. Two rows are preferred. The frame width (L3) of the tab 3a is, for example, 2.3 mm when the opening S is one row, and is, for example, 2.6 mm when the opening S is two rows.

  Here, when the direction along one side of the frame-shaped tab 3a (or the semiconductor chip 2) is the second direction (direction intersecting the first direction), a plurality of openings arranged along the first direction. The part S is divided into a plurality of openings S along the second direction for each column. The openings S (S1, S2) in each row are formed in a planar strip shape that is longer in the second direction than in the first direction.

  A dimension (short dimension) L4 in the first direction of the opening S1 in the first row is, for example, 0.15 to 0.3 mm. Moreover, the dimension (short direction dimension) L5 of the 1st direction of the opening part S2 of the 2nd row is 0.15-0.3 mm, for example. The reason for this dimension value is that if the dimensions L4 and L5 are too large, the area of the metal portion of the tab 3a is reduced and the heat dissipation is reduced. This is because the resin of the body 6 cannot be sufficiently filled and the anchor effect cannot be obtained. In the first embodiment, the dimension (short dimension) L5 in the first direction of the opening S2 in the second row is larger than the dimension (short dimension) L4 in the first direction of the opening S1 in the first row. It is getting smaller. This is to ensure the mechanical strength of the tab 3a in addition to the above reason.

  The opening S1 in the first row is arranged at the center in the first direction of the tab 3a. That is, the dimension L6 in the first direction from the inner periphery of the tab 3a to the opening S1 in the first row is equal to the dimension L7 in the first direction from the outer periphery of the tab 3a to the opening S1 in the first row. This is to ensure the uniformity of the mechanical strength of the tab 3a. The dimensions L6 and L7 are, for example, 1 mm.

  On the other hand, the opening S2 in the second row is arranged at the center of the dimension L7 in the first direction. That is, the dimension L8 in the first direction from the opening S1 to the opening S2 in the second row is equal to the dimension L9 in the first direction from the outer periphery of the tab 3a to the opening S2 in the second row. This is also to ensure the uniformity of the mechanical strength of the tab 3a.

  A separation portion is disposed between the adjacent openings in the second direction of the plurality of openings S1 and S2 in each row. This separation part forms a connection part that connects the tabs 3a located on both sides in the first direction with the openings S1 and S2 interposed therebetween.

  Separating portions (connecting portions) between the adjacent openings in the second direction of the plurality of openings S1 in the first row are arranged at positions corresponding to the centers and corners of the sides of the tab 3a or the semiconductor chip 2. On the other hand, a separation portion (connection portion) between adjacent openings in the second direction of the plurality of openings S2 in the second row is arranged at a position corresponding to the tab 3a or the corner of the semiconductor chip 2 and a part of the opening S1. ing. That is, the openings S1 and S2 arranged adjacent to each other along the first direction are arranged so that their arrangement positions are shifted from each other in the second direction. Thereby, since the position of the connection part of the 1st row and the 2nd row shifts, the mechanical strength of tab 3a can be improved. As a result, it is possible to suppress or prevent the tab 3a from being deformed, for example, when the tab 3a is bent.

  In the first embodiment, as described above, the bent portion 3b1 of the tab suspension lead 3b is formed at a position closer to the tab 3a than the inner end of the lead 3c. This will be described with reference to FIGS.

  FIG. 8 is an enlarged plan view of the main part of the lead frame 3 of the semiconductor device and the bonding stage 15 on which the semiconductor device lead frame 3 examined by the present inventor prior to the configuration of the first embodiment, and FIG. 9 is Z1-Z1 in FIG. A cross-sectional view of the line is shown.

  The lead frame 3 is placed on the bonding stage 15 of the wire bonding apparatus. Since the tab 3a is lowered in the thickness direction as compared with the lead 3c as described above, the frame mounting surface of the bonding stage 15 is accommodated so that the entire tab 3a and a part of each of the plurality of tab suspension leads 3b are accommodated. Is formed with a groove 15a. The groove 15a is formed with a slightly larger planar dimension than the tab 3a and the tab suspension lead 3b so that the entire tab 3a and a part of the tab suspension lead 3b can be accommodated.

  Here, in the lead frame 3 of FIG. 8, the bent portion 3b1 of the tab suspension lead 3b is formed at a position farther from the tab 3a than the inner end (tip portion) of the lead (inner lead portion) 3c. This is based on the assumption that a pyramid collet (planar dimension is larger than the planar dimension of the semiconductor chip 2) is used as means for holding the semiconductor chip 2 when the semiconductor chip 2 is mounted on the tab 3a. . The pyramid collet is used in consideration of the fact that various semiconductor chips 2 having different planar dimensions may be mounted on the tab 3a.

  However, when the pyramid collet is used, if the position of the bent portion 3b1 of the tab suspension lead 3b is closer to the tab 3a than the inner end of the lead 3c, the outer periphery of the pyramid collet hits the tab suspension lead 3b. Therefore, in this case, the bent portion 3b1 of the tab suspension lead 3b is formed at a position farther from the tab 3a than the inner end of the lead 3c, so that the outer periphery of the pyramid collet does not contact the tab suspension lead 3b. .

  By the way, when the bent portion 3b1 of the tab suspension lead 3b is formed at a position farther from the tab 3a than the inner end of the lead 3c as described above, the groove 15a for accommodating a part of the tab suspension lead 3b is also formed on the lead 3c. It is formed so as to extend to a position farther from the tab 3a than the inner end. In this case, the lead 3c adjacent to the tab suspension lead 3b must be separated from the outer periphery of the groove 15a by a length L10. This needs to be performed in a state where the lead 3c is fixed on the heated bonding stage 15 as a measure against defective wire connection. However, if the length L10 between the lead 3c and the groove 15a is short, the lead frame 3 is attached to the bonding stage. This is because it is difficult to securely fix the back surface of the lead 3c to the bonding stage 15 if a positional deviation occurs when the electrode is disposed on the bonding stage 15. Therefore, since the lead 3c is formed away from the tab suspension lead 3b in consideration of the length L10, the interval (pitch) between the plurality of leads 3c is also narrowed, and the respective tips of the plurality of leads 3c are reduced. It is difficult to bring the portion close to the semiconductor chip 2. As a result, it becomes difficult to dissipate the heat of the semiconductor chip 2 through the plurality of leads 3c.

  Next, FIG. 10 is an enlarged plan view of a main part of the lead frame 3 and the bonding stage 15 on which the lead frame 3 of the semiconductor device 1 according to the first embodiment is mounted, and FIG. 11 is a sectional view taken along the line Z1-Z1 in FIG. ing.

  In the first embodiment, the bent portion 3b1 of the tab suspension lead 3b is formed at a position closer to the tab 3a than the inner end of the lead 3c. For this reason, the groove 15a is not interposed between the tab suspension lead 3b and the lead 3c adjacent thereto. In this case, the lead 3c adjacent to the tab suspension lead 3b may be disposed so as to be separated from the outer periphery of the tab suspension lead 3b by a length L10 from the outer periphery of the tab suspension lead 3b. It can be brought close to the lead 3b. For this reason, the inner ends of the plurality of leads 3c can be brought closer to the tab 3a. That is, the distance between the tab 3a (semiconductor chip 2) and the lead 3c can be shortened.

  As a result, the thermal resistance between the tab 3a and the lead 3c can be lowered, so that the heat generated during the operation of the semiconductor chip 2 can be dissipated through the lead 3c. Therefore, the heat dissipation of the semiconductor device 1 can be improved.

  Moreover, since the distance between the semiconductor chip 2 and the lead 3c can be shortened, the length of the wire 5 can be shortened. In other words, the distance between the tab 3a and the tip of the lead (inner lead portion) 3c can be reduced. Thereby, the problem that several wires 5 mutually contact can be suppressed. Here, the following may be considered as a cause of the problem that the wires 5 contact each other. When the sealing bodies 6 are formed above and below the lead frame 3 as in the QFP type semiconductor device, there is a resin that flows in the thickness direction of the lead frame 3. Such a resin is particularly likely to occur in a place where no obstacle exists, and is described in the first embodiment, for example, a space between the tab 3a and the lead 3c. For this reason, when the resin flows in the thickness direction of the lead frame 3 in this space, the plurality of wires 5 disposed in a position overlapping the space in a plane are swept away. Thereby, the problem that adjacent wires 5 come into contact with each other easily occurs. However, in the first embodiment, the tab 3a is formed to have a relatively large width, and the bent portion 3b1 formed on the tab suspension lead 3b is positioned closer to the tab 3a than the tip of the lead (inner lead portion) 3c. Since it forms, it becomes possible to make each front-end | tip part of the some lead | read | reed 3c approach the tab 3a more, and the space between the tab 3a and the some lead | read | reed 3c can be made relatively small. Therefore, a short circuit failure of the wire 5 can be suppressed.

  Next, an example of a method for manufacturing the semiconductor device 1 according to the first embodiment will be described with reference to FIGS.

  First, a lead frame 3 as shown in FIGS. 12 to 14 is prepared. 12 is an enlarged plan view of a main part of the lead frame 3, FIG. 13 is an enlarged plan view of a unit region of the lead frame 3 in FIG. 12, and FIG. 14 is a sectional view taken along line X1-X1 in FIG.

  The lead frame 3 is formed of, for example, a flat strip-shaped metal thin plate, and has a main surface (first main surface) and a back surface (second main surface) located on opposite sides along the thickness direction. Yes. The lead frame 3 is made of a metal such as copper or 42 alloy, for example, and a plurality of unit regions are arranged along the longitudinal direction thereof.

  The unit area of the lead frame 3 is an area having components necessary for manufacturing one semiconductor device 1, and the frame-like tab 3a, the tab suspension lead 3b, and the plurality of leads 3c are already in the horizontal frame. The pattern is formed in a state of being integrally connected to the portion 3d and the vertical frame portion 3e. The tab 3a is lowered in the thickness direction of the tab 3a as described above, and the openings S1 and S2 are formed in the outer peripheral portion 3a2. Furthermore, the fixing tape 4 is affixed on the main surface of the plurality of leads 3c in each unit region.

  Subsequently, a conductive paste material such as silver paste is applied to the inner peripheral portion 3a1 of the main surface of the tab 3a of each unit region of the lead frame 3. 15 is an enlarged plan view of a unit region of the lead frame 3 after applying the paste material, and FIG. 16 is a cross-sectional view taken along line X1-X1 of FIG. The paste material 10a is applied in the form of dots along the inner periphery of the tab 3a on the inner peripheral portion 3a1 of the main surface of the tab 3a. When applying the paste material 10a, for example, a paste nozzle 18 is used.

  Subsequently, the process proceeds to a die bonding process. First, the lead frame 3 is placed on the bonding stage of the die bonding apparatus. Subsequently, as shown in FIGS. 17 and 18, a vacuum suction pad (die suction jig) 20 is applied to the main surface of the semiconductor chip 2 to hold the semiconductor chip 2 by vacuum suction, and the tab 3 a of the lead frame 3 is held. Transfer directly above. 17 is an enlarged plan view of a unit region of the lead frame 3 during die bonding, and FIG. 18 is a cross-sectional view taken along line X1-X1 of FIG. The chip suction surface of the vacuum suction pad 20 (the surface facing the main surface of the semiconductor chip 2) is smaller than the main surface of the semiconductor chip 2, and the outer periphery thereof protrudes from the outer periphery of the semiconductor chip 2 when the semiconductor chip 2 is sucked. There is no end.

  Subsequently, after the relative planar positions of the semiconductor chip 2 held on the vacuum suction pad 20 and the tab 3a are aligned, the semiconductor chip 2 is moved to the tab 3a side, and the back surface of the semiconductor chip 2 is moved to the tab 3a. Lightly press against the inner peripheral portion 3a1 of the main surface. Thus, as shown in FIGS. 19 and 20, the back surface of the semiconductor chip 2 and the main surface of the tab 3a are joined by the adhesive 10, and the semiconductor chip 2 is mounted on the main surface of the tab 3a. 19 is an enlarged plan view of a unit region of the lead frame 3 during die bonding, and FIG. 20 is a cross-sectional view taken along line X1-X1 of FIG. Such a die bonding process is performed for each unit region of the lead frame 3.

  Next, the process proceeds to a wire bonding process. 21 is a plan view of a part (unit region) of the bonding stage 15 of the wire bonding apparatus, and FIG. 22 is a cross-sectional view taken along line X1-X1 of FIG. On the frame mounting surface of the bonding stage 15, a groove 15 a that can accommodate the entire tab 3 a and a part of the tab suspension lead 3 b is formed. A plurality of grooves 15 a are formed on the frame mounting surface of the bonding stage 15 corresponding to the unit area of the lead frame 3.

  Subsequently, as shown in FIGS. 23 and 24, the lead frame 3 is placed on the frame mounting surface of the heated bonding stage 15. FIG. 23 is an enlarged plan view of a main part of a unit region of the lead frame 3 placed on the bonding stage 15 of the wire bonding apparatus, and FIG. 24 is a sectional view taken along line X1-X1 in FIG. The lead frame 3 is placed on the frame mounting surface of the bonding stage 15 in a state where the entire tab 3a of each unit region and a part of the tab suspension lead 3b are stored in the groove 15a of each unit region of the bonding stage 15. It is put on.

  Subsequently, as shown in FIGS. 25 and 26, the lead 3 c exposed from the bonding window of the lead tip pressing jig 21 in a state where the plurality of leads 3 c of the lead frame 3 are pressed by the lead tip pressing jig 21. Are connected to the pads of the semiconductor chip 2 by wires 5. 25 is an enlarged plan view of a main part of a unit region of the lead frame 3 placed on the bonding stage 15 after the wire bonding process, and FIG. 26 is a cross-sectional view taken along line X1-X1 of FIG.

  By the way, in a general wire bonding process, wire bonding is performed in a state where the lead 3c portion outside the fixing tape 4 is pressed by the lead tip pressing jig 21. However, as the functionality of the semiconductor device 1 increases, the total number of leads 3c increases and the leads 3c become thinner, so that the leads 3c are likely to float in the thickness direction during the wire bonding process. In order to connect the wire 5 while suppressing such fluttering of the lead 3c, it is preferable to fix the position near the lead 3c with the lead tip pressing jig 21 as much as possible, but for connecting the wire 5 In order to prevent interference with a capillary (not shown), it is difficult to fix the position closer to the tip of the lead 3 c than the fixing tape 4 with the lead tip pressing jig 21.

  Therefore, in the first embodiment, in order to fix the position closer to the tip of the lead 3c with the lead tip pressing jig 21, the lead tip is placed at a position that overlaps the fixing tape 4 as shown in FIG. Wire bonding is performed in a state in which the plurality of leads 3 c are pressed by the holding jig 21. Thereby, since the inner end of the lead 3c can be firmly pressed by the lead tip pressing jig 21, it is possible to suppress or prevent the lead 3c from floating during the wire bonding process. For this reason, the reliability of wire bonding can be improved.

  Subsequently, as shown in FIGS. 27 and 28, the sealing body 6 is formed by a transfer molding method. 27 is an enlarged plan view of a main part of a unit region of the lead frame 3 after the molding process, and FIG. 28 is a cross-sectional view taken along line X1-X1 of FIG. In the molding process, the sealing bodies 6 of the plurality of unit regions of the lead frame 3 are molded together.

  In the first embodiment, since the area of the tab 3a is increased, deformation of the wire 5 during the molding process can be suppressed or prevented, so that contact failure between the wires 5 due to deformation of the wire 5 is reduced or prevented. can do. This will be described with reference to FIGS. 29 and 30. FIG.

  FIG. 29 is a cross-sectional view of the mold 25 during the molding process in the case of the general tab 3a, and FIG. 30 is a cross-sectional view of the mold 25 during the molding process according to the first embodiment.

  The mold 25 has a lower mold 25a and an upper mold 25b. The lead frame 3 is held in a state sandwiched between the lower mold 25a and the upper mold 25b. The semiconductor chip 2, the tab 3a, a part of the lead 3c and the wire 5 mounted on the lead frame 3 are accommodated in a cavity 25c formed on the opposing surface of the lower die 25a and the upper die 25b. Arrows A and B indicate the flow of the mold resin.

  In the general case, as shown in FIG. 29, the tab 3a is small, the mold resin flow A from the upper mold 25b side to the lower mold 25a side, and the mold resin flow B from the lower mold 25a side to the upper mold 25b side. Therefore, the wire 5 may be deformed by the flow A and B of the mold resin.

  On the other hand, in the case of the first embodiment, as shown in FIG. 30, the tab 3a is large and the outer peripheral portion 3a2 blocks the flow A and B of the mold resin, so that the flow of the mold resin is suppressed. For this reason, the deformation | transformation of the wire 5 resulting from the flow A and B of mold resin can be suppressed or prevented.

  Subsequently, after the individual sealing bodies 6 are taken out from the lead frame 3 by cutting a part of the lead frame 3, the leads 3c protruding from the four side surfaces of the sealing body 6 are formed in a gull wing shape to form a semiconductor device. 1 is manufactured.

(Embodiment 2)
In the second embodiment, the outer peripheral shape of the frame-shaped tab is different from that of the first embodiment. The rest is the same as in the first embodiment.

  31 is an enlarged plan view of a main part of the semiconductor device 1 according to the second embodiment, and FIG. 32 is a cross-sectional view taken along line X2-X2 in FIG. FIG. 31 shows the inside of the sealing body 6 in a transparent manner for easy viewing of the drawing, and shows a state in which the wires are removed.

  In the second embodiment, the outer peripheral shape of the frame-like tab 3a is formed in, for example, a substantially octagonal shape. That is, on the outer periphery of the tab 3 a, the portions corresponding to the four sides of the semiconductor chip 2 are shaped so as to gradually approach the tip of the lead 3 c toward the center of the side of the semiconductor chip 2. Thereby, a part of the tab 3a corresponding to the center of each of the four sides of the semiconductor chip 4 can be brought close to the inner end of the lead 3c, so that the heat dissipation of the semiconductor device 1 can be improved.

  In addition, the shape of the inner periphery (center opening) of the frame-like tab 3a may be made substantially octagonal so as to match the outer shape so that the dimensions of the tab 3a in the first direction are equal. Thereby, since the dimension of the 1st direction of the tab 3a becomes substantially equal in a perimeter, the uniformity of the mechanical strength of the tab 3a is securable.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above description, the case where the invention made mainly by the present inventor is applied to a semiconductor device used in an electronic device of an automobile, which is a field of use as a background, has been described. However, the present invention is not limited thereto and can be applied in various ways. For example, the present invention can be applied to a semiconductor device used in an information processing device such as a personal computer, a mobile communication device such as a mobile phone, and a multimedia device such as a digital camera.

  The present invention can be applied to the semiconductor device manufacturing industry.

1 is a plan view of a semiconductor device according to an embodiment (Embodiment 1) of the present invention; It is sectional drawing of the X1-X1 line | wire of FIG. FIG. 2 is an enlarged plan view of a main part of the semiconductor device of FIG. 1. It is sectional drawing of the X1-X1 line | wire of FIG. FIG. 2 is an enlarged plan view of a main part of the semiconductor device of FIG. 1. It is sectional drawing of the X1-X1 line | wire of FIG. FIG. 2 is an enlarged plan view of a tab of the semiconductor device of FIG. 1. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an enlarged plan view of a main part of a lead frame of a semiconductor device examined by the present inventor prior to an embodiment of the present invention and a bonding stage on which this is mounted. It is sectional drawing of the Z1-Z1 line | wire of FIG. 1 is an enlarged plan view of a main part of a lead frame of a semiconductor device according to an embodiment of the present invention and a bonding stage on which the lead frame is mounted. It is sectional drawing of the Z1-Z1 line | wire of FIG. FIG. 2 is an enlarged plan view of a main part of a lead frame during a manufacturing process of the semiconductor device of FIG. FIG. 13 is an enlarged plan view of a unit region of the lead frame in FIG. 12. It is sectional drawing of the X1-X1 line | wire of FIG. FIG. 14 is an enlarged plan view of a unit region after applying a paste material for a lead frame in the manufacturing process of the semiconductor device subsequent to FIG. 13; It is sectional drawing of the X1-X1 line | wire of FIG. FIG. 16 is an enlarged plan view of a unit region during die bonding of the lead frame during the manufacturing process of the semiconductor device following FIG. 15; It is sectional drawing of the X1-X1 line | wire of FIG. FIG. 18 is an enlarged plan view of a unit region during die bonding of the lead frame during the manufacturing process of the semiconductor device following FIG. 17; It is sectional drawing of the X1-X1 line | wire of FIG. It is a partial top view of the bonding stage of a wire bonding apparatus. It is sectional drawing of the X1-X1 line | wire of FIG. FIG. 20 is an enlarged plan view of a main part of a unit region of the lead frame placed on the bonding stage of the wire bonding apparatus in the semiconductor device manufacturing process following FIG. 19; It is sectional drawing of the X1-X1 line | wire of FIG. FIG. 24 is an essential part enlarged plan view of a unit region of a lead frame placed on a bonding stage after a wire bonding process which is a semiconductor device manufacturing process subsequent to FIG. 23; It is sectional drawing of the X1-X1 line | wire of FIG. FIG. 26 is an essential part enlarged plan view of a unit region of the lead frame after a molding process that is a manufacturing process of the semiconductor device following FIG. 25; It is sectional drawing of the X1-X1 line | wire of FIG. It is sectional drawing of the mold die at the time of a mold process in the case of a general tab. It is sectional drawing in the mold die at the time of the molding process which is a manufacturing process of the semiconductor device of FIG. It is a principal part enlarged plan view of the semiconductor device of other embodiment (Embodiment 2) of this invention. It is sectional drawing of the X2-X2 line | wire of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor chip 3 Lead frame 3a Tab (chip mounting part)
3a1 Inner peripheral part 3a2 Outer peripheral part 3b Tab suspension lead 3b1 Bending part 3c Lead 4 Fixing tape 5 Bonding wire 6 Sealing body 10 Adhesive 10a Paste material 15 Bonding stage 15a Groove 18 Paste nozzle 20 Vacuum suction pad (Suction collet)
21 Lead tip holding jig 25 Mold die 25a Lower die 25b Upper die 25c Cavity S1 Opening S2 Opening

Claims (15)

(A) a frame-shaped chip mounting portion having a first main surface and a second main surface located on opposite sides along the thickness direction;
(B) a semiconductor chip mounted on the chip mounting portion;
(C) a plurality of leads arranged around the chip mounting portion;
(D) bonding wires for electrically connecting the plurality of electrodes of the semiconductor chip to the plurality of leads;
(E) a resin sealing body for sealing the semiconductor chip;
The chip mounting portion is
An inner periphery where the semiconductor chips overlap in a plane;
And integrally having an outer peripheral portion located around the semiconductor chip,
When the direction from the inner periphery to the outer periphery of the chip mounting portion is the first direction,
The dimension of the outer peripheral part in the first direction is wider than the dimension of the inner peripheral part in the first direction,
The semiconductor device according to claim 1, wherein an opening that penetrates between the first and second main surfaces is formed in the outer peripheral portion.   2. The semiconductor device according to claim 1, wherein a dimension of the chip mounting portion in the first direction is wider than a width of a fixing tape provided so as to fix the plurality of leads.   The semiconductor device according to claim 1, wherein a plurality of the openings are arranged along the first direction. The semiconductor device according to claim 3.
When the direction along the outer periphery of the chip mounting portion is the second direction,
The plurality of openings arranged along the first direction of the outer peripheral portion are formed to be divided into a plurality of openings along the second direction for each row,
Openings arranged adjacent to each other along the first direction of the outer peripheral portion are arranged so that their arrangement positions are shifted from each other in the second direction. The semiconductor device according to claim 1,
When the direction along the outer periphery of the chip mounting portion is the second direction,
The opening is divided into a plurality of openings along the second direction,
The separation part arranged between the plurality of openings arranged along the second direction is a connection that connects parts of the chip mounting parts located on both sides of the first direction with the opening interposed therebetween. A semiconductor device characterized in that a part is formed.   6. The semiconductor device according to claim 5, wherein the connecting portion is formed at a position corresponding to a center of a side of the semiconductor chip.   2. The semiconductor device according to claim 1, wherein the semiconductor chip is mounted on the chip mounting portion using a conductive paste material. The semiconductor device according to claim 1,
The chip mounting portion is supported by a plurality of suspension leads formed integrally with the chip mounting portion,
Each of the plurality of suspension leads is bent in a direction intersecting the first main surface and the second main surface of the chip mounting portion,
The bent portion of each of the plurality of suspension leads is formed at a position closer to the semiconductor chip than the tip on the chip mounting portion side of the plurality of leads.   9. The semiconductor device according to claim 8, wherein each of the plurality of suspension leads is bent from a first main surface to a second main surface of the chip mounting portion.   2. The semiconductor device according to claim 1, wherein the semiconductor chip has functions of a serial sound interface and a CDROM decoder. (A) preparing a lead frame having a first main surface and a second main surface located on opposite sides along the thickness direction;
(B) mounting a semiconductor chip using a suction collet on the frame-shaped chip mounting portion of the lead frame;
(C) After mounting the lead frame on a bonding stage of a bonding apparatus, the plurality of electrodes of the semiconductor chip mounted on the chip mounting portion are electrically connected to the plurality of leads of the lead frame by bonding wires. Process,
(D) sealing the semiconductor chip with a resin sealing body,
The lead frame in the step (a) is
The chip mounting portion;
The plurality of leads disposed around the chip mounting portion;
A plurality of suspension leads formed integrally with the chip mounting portion and supporting the chip mounting portion;
The chip mounting portion is
An inner periphery where the semiconductor chips overlap in a plane;
And integrally having an outer peripheral portion located around the semiconductor chip,
When the direction from the inner periphery to the outer periphery of the chip mounting portion is the first direction,
The dimension of the outer peripheral part in the first direction is wider than the dimension of the inner peripheral part in the first direction,
In the outer peripheral portion, an opening penetrating between the first and second main surfaces is formed,
The plurality of suspension leads are bent in a direction intersecting the first main surface and the second main surface of the lead frame,
Each bent portion of the plurality of suspension leads is formed at a position closer to the semiconductor chip than the tip of the plurality of leads on the chip mounting portion side,
A groove is formed on the frame mounting surface of the bonding stage of the bonding apparatus,
In the step (c),
A plurality of electrodes of a semiconductor chip mounted on the chip mounting portion, after the lead frame is mounted on the bonding stage so that the chip mounting portion of the lead frame fits in the groove of the bonding stage; A method of manufacturing a semiconductor device, wherein a plurality of leads of a lead frame are electrically connected by bonding wires.   12. The method of manufacturing a semiconductor device according to claim 11, wherein in the step (b), a planar size of the suction surface of the suction collet is smaller than a planar size of the semiconductor chip.   12. The method of manufacturing a semiconductor device according to claim 11, wherein a frame mounting surface of the bonding stage has a groove provided at a position corresponding to a part of each of the plurality of suspension leads and the chip mounting portion. The bonding wire is connected in a state where a part of the suspension lead and the chip mounting portion are disposed in the groove.   14. The method of manufacturing a semiconductor device according to claim 13, wherein the bonding wire is connected in a state in which a fixing tape attached to the lead frame is pressed by a jig.   12. The method of manufacturing a semiconductor device according to claim 11, wherein each of the plurality of suspension leads is bent from a first main surface to a second main surface of the chip mounting portion. Production method.

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