JP2008270310A - Group III nitride compound semiconductor vertical transistor and manufacturing method thereof - Google Patents

Abstract

A novel group III nitride compound semiconductor vertical transistor is provided.
An Al / Ti / Pt / Au multiple metal layer 32, an AuSn solder layer 33, an Au / Ni / Al / Ti multiple metal layer 15, an n ⁺ contact layer (n ⁺ -GaN) on an n-type Si substrate 31. ) 14 and a drift portion (n-GaN) 13 are formed. The drift portion 13 has a current confinement portion 13bn having a thickness of about 0.5 μm, and an AlN layer 21 and a p layer (p-GaN) 22 are formed on the left and right sides thereof. The uppermost portion of the drift portion 13 (current confinement portion 13bn) and the uppermost portion of the p layer (p-GaN) 22 are in the same plane. A channel layer (n-GaN) 12 and an electron donating layer (AlGaN) 11 are formed on them. The HEMT 100 can be obtained by epitaxially growing a sapphire substrate, attaching a silicon substrate, and removing the sapphire substrate by a laser lift-off method.
[Selection] FIG. A

Description

The present invention relates to a novel vertical transistor mainly composed of a group III nitride compound semiconductor and a method for manufacturing the same. The present invention particularly relates to a group III nitride compound semiconductor vertical transistor that functions as a high electron mobility transistor (HEMT) using a two-dimensional electron gas. In this specification, the group III nitride compound semiconductor means a binary, ternary, or quaternary semiconductor represented by Al _x Ga _y In _1-xy N, and conductivity type control, etc. Therefore, it is assumed that the elements added with any element are included, and further, the partial composition of the group III element is replaced with B and Tl, and the partial composition of the group V element is replaced with P, As, Sb, and Bi. Including those that have been made. Further, the vertical type of the vertical transistor means a transistor in which current flows in the normal direction of the substrate main surface.

Various group III nitride compound semiconductor devices have been studied as devices operating at high temperatures and high breakdown voltage. For example, a field effect transistor (FET) using a group III nitride compound semiconductor has been reported which has a source electrode, a gate electrode, and a drain electrode in the lateral direction, that is, aligned with the element surface. The same applies to the group III nitride compound semiconductor transistor that acts as a high electron mobility transistor (HEMT).
JP 2004-260140 A JP 2005-159207 A

  The inventors of the present invention have studied a group III nitride compound semiconductor vertical transistor having a novel configuration that acts as a HEMT. It is also conceivable to form a vertical transistor by, for example, laminating a drain portion, a current constriction portion (and an insulating region for limiting the region), a channel layer, and an electron donating layer in this order from the lower layer by epitaxial growth. However, in this order, it is difficult to form a flat interface between the channel layer and the electron donating layer above the current confinement portion, and it is difficult to form a HEMT with good device characteristics using a two-dimensional electron gas. .

  Further, in order to form the drain electrode, it is necessary to expose the drain portion or to form the HEMT on a conductive substrate. When the HEMT is formed on an insulating substrate such as sapphire and the drain portion is exposed, the effective area acting as an element is substantially smaller than the occupied area of the element. Further, as a conductive substrate capable of epitaxially growing a group III nitride compound semiconductor with good crystallinity at present, GaN free-standing substrates, SiC substrates, etc. are very expensive, and it is difficult to increase the area of the substrate. There is.

  The present invention has been made in order to solve the above-mentioned problems, and has been completed with the idea of a completely new group III nitride compound semiconductor vertical transistor and a manufacturing method thereof.

The invention according to claim 1 is a novel vertical transistor conceived by the present inventors.
The structure is a vertical transistor using a group III nitride compound semiconductor, and includes a conductive support substrate and a layer made of a material different from that of the group III nitride compound semiconductor provided on the support substrate. A conductive layer having at least one layer, a drift portion made of a group III nitride compound semiconductor formed directly on the conductive layer or via a group III nitride compound semiconductor layer, and provided on the drift portion; It has a channel layer and an electron donating layer respectively formed from two types of group III nitride compound semiconductors having different compositions, and the drift portion is an insulating region or a group III nitride compound semiconductor region having a lower carrier concentration Alternatively, a group III nitride compound semiconductor region having a different conductivity type has a current confinement portion laterally limited, and an insulator is interposed on the surface of the electron donating layer above the current confinement portion of the drift portion, or A group III nitride compound having a gate electrode by Schottky connection, a source electrode capable of supplying current to the channel layer in the lateral direction of the gate electrode, and a drain electrode on the back surface of the support substrate It is a semiconductor vertical transistor.

  Here, the layer made of a material different from the Group III nitride compound semiconductor is, for example, a single metal layer or alloy layer, a metal multilayer, or a layer made of another conductive material, and is made of Group III nitride. What is not a physical compound semiconductor shall be said. The source electrode capable of supplying current to the channel layer may be provided, for example, in direct contact with the channel layer, or provided that current can be supplied to the channel layer even when the channel layer is interposed. Be good. The same applies to the following.

  The invention according to claim 2 allows or prevents diffusion of the two-dimensional electron gas in the lateral direction above the current confinement portion of the drift portion in the vicinity of the interface between the channel layer and the electron donating layer by the gate electrode, It is a high electron mobility transistor (HEMT) that allows or blocks the transfer of carriers from the source electrode to the drain electrode. In the invention according to claim 3, the current confinement portion of the drift portion is laterally limited by a group III nitride compound semiconductor region having a different conductivity type, and the potential of the source electrode is different from that of the conductivity type. It is also applied to the group III nitride compound semiconductor region.

The invention according to claim 4 is a method for manufacturing the novel vertical transistor of the first to third aspects, which is conceived by the present inventors.
That is, on the epitaxial growth substrate, at least a sacrificial layer, a first layer made of a group III nitride compound semiconductor containing at least aluminum, a second layer made of a group III nitride compound semiconductor and constituting a channel layer, After epitaxially forming a third layer made of a group III nitride compound semiconductor to which an acceptor impurity is added, the third layer is partially etched to partially expose the second layer. After epitaxially growing a fourth layer made of a group III nitride compound semiconductor on the layer 2 and forming a drift portion, the group III nitride compound semiconductor layer or a conductive layer directly or further on the drift portion And connecting the conductive layer side of the conductive support substrate having the conductive layer formed on the surface to remove at least the epitaxial growth substrate and the sacrificial layer to expose the first layer. A gate electrode is formed on the exposed first layer above the current confinement portion of the drift portion by Schottky connection or via an insulating layer, and current is supplied to the second layer in the lateral direction of the gate electrode. A method for producing a group III nitride compound semiconductor vertical transistor, characterized in that a possible source electrode is formed by ohmic connection.
The invention according to claim 5 is characterized in that the source electrode is formed so as to be in contact with the group III nitride compound semiconductor region to which the acceptor impurity is added.

The vertical transistor according to claims 1 to 3 has a novel configuration, and the novel vertical transistor can be easily manufactured by the manufacturing method according to claim 4 or 5.
According to the manufacturing method, the electron donor layer and the channel layer are formed in this order on the epitaxial growth substrate through the group III nitride compound semiconductor layer serving as a sacrificial layer, and in this order, the flatness of the electron donor layer and the channel layer. In particular, their interfaces can be formed extremely flat. Thereby, for example, a two-dimensional electron gas can be efficiently formed on the channel layer side of the interface. After forming the electron donor layer and the channel layer with a flat interface, the process for forming the current confinement part and the drift part can be designed arbitrarily, and the drift part is increased to a layer thickness of 10 μm or more to increase the current. It is also easy to make a power transistor that can withstand.
Further, since the back surface of the conductive support substrate can be used as the drain electrode, the entire area in the horizontal direction of the element can be effectively used as a transistor.

  By sandwiching the current confinement portion of the drift portion between layers of different conductivity types and applying a source potential to the layers of different conductivity types, an aperture structure that allows current to flow in the vertical direction can be formed. For example, if the drift portion (current constriction portion) is n-type, the current confinement portion is sandwiched between two p-type regions. Then, the source potential is applied to the two p-type regions, so that the depletion layer can completely close the current confinement portion. Thereby, the high pressure | voltage resistant characteristic at the time of OFF can be provided.

  When removing the epitaxial growth substrate from the epitaxial film, a technique called a laser lift-off method can be used. This is not absorbed by the epitaxial growth substrate. For example, a laser having a wavelength that is absorbed by GaN is irradiated to the interface between the GaN layer and the epitaxial growth substrate in focus, and a very thin part of the GaN layer on the epitaxial growth substrate interface side ( Melt 0.1 μm or less in thickness). By scanning the laser so that the melted portion is the entire surface of the epitaxial growth substrate, the epitaxial growth substrate can be easily removed from the epitaxial film. Prior to laser lift-off, a support substrate is attached on the opposite side of the epitaxial film from the epitaxial growth substrate. The support substrate is preferably a conductive support substrate so that it can eventually become a substrate of an element. As the conductive support substrate, for example, an n-type silicon substrate is preferably used at low cost.

  In order to form the current confinement portion, for example, when a hole or void is provided in the p-type layer to expose the channel layer, dry etching using an insulating film such as a photoresist or silicon oxide as a mask is preferably used.

  FIG. 1A is a cross-sectional view showing a configuration of a group III nitride compound semiconductor vertical transistor (HEMT) 100 according to a first specific example of the present invention. FIG. FIG. The structure of group A nitride semiconductor compound vertical transistor (HEMT) 100 of A is as follows.

A multi-metal layer 32 in which an aluminum (Al) layer / titanium (Ti) layer / platinum (Pt) layer / gold (Au) layer is laminated in this order on an n-type Si substrate 31, and gold tin (AuSn) thereon. A multiple metal layer 15 is formed on which a solder layer 33 is laminated in order of gold (Au) layer / nickel (Ni) layer / aluminum (Al) layer / titanium (Ti) layer. As shown later, the internal configuration of the multiple metal layer 15 is described in the order of stacking on the n ⁺ contact layer (n ⁺ -GaN) 14, so that FIG. In A, the indication of the multiple metal layer 15 was Ti / Al / Ni / Au.

An n ⁺ contact layer (n ⁺ -GaN) 14 made of GaN doped with silicon (Si) having a film thickness of 0.1 μm and an electron concentration of 1 × 10 ¹⁸ / cm ³ is formed on the multiple metal layer 15. A drift portion (n-GaN) 13 made of GaN doped with silicon (Si) having a film thickness of 20 μm and a carrier concentration of 2 × 10 ¹⁶ / cm ³ is formed thereon. The drift portion 13 has a current confinement portion 13bn having a thickness of about 0.5 μm, and an AlN layer 21 having a thickness of 0.01 μm and a thickness on the AlN layer 21 on the left and right of the current confinement portion 13bn in FIG. A p-layer (p-GaN) 22 made of GaN doped with magnesium (Mg) having a hole concentration of 2 × 10 ¹⁸ / cm ^{3 and} a thickness of 0.5 μm is formed. The uppermost portion of the drift portion 13 (current confinement portion 13bn) and the uppermost portion of the p layer (p-GaN) 22 are in the same plane.

On the drift portion 13 (current confinement portion 13bn) and the p layer (p-GaN) 22, it is made of GaN doped with silicon (Si) having a film thickness of 0.1 μm and an electron concentration of 1 × 10 ¹⁶ / cm ^3. A channel layer (n-GaN) 12 is formed on the channel layer (n-GaN) 12 with an electron-donating layer (AlGaN) 11 made of AlGaN with no impurity added to a thickness of 0.03 μm and a SiO layer with a thickness of 0.05 μm. _An insulating film 10 made of ₂ is formed.

In addition, FIG. As shown in A, the polycrystal is formed on the insulating film 10 made of SiO ₂ so as to include the horizontal occupation region of the current confinement portion 13bn and to extend to the upper side of the p layer (p-GaN) 22 extending to the left and right. A gate electrode 41G made of silicon (Poly-Si) is formed. Two source electrodes 40S are formed on the left and right sides as viewed from the gate electrode 41G with an interval in the horizontal direction. The source electrode 40S is formed to be in contact with the channel layer (n-GaN) 12 exposed by partially removing the insulating film 10 made of SiO ₂ and the electron donating layer (AlGaN) 11. A drain electrode 42D is formed on the back surface of the n-type Si substrate 31. The structure of the source electrode 40S is laminated in the order of titanium (Ti) layer / aluminum layer (Al) / nickel (Ni) layer / gold (Au) layer from the lower side (side in contact with the channel layer (n-GaN) 12). The drain electrode 40D has a structure in which the aluminum layer (Al) / titanium (Ti) layer / platinum (Pt) layer / gold (Au) layer is laminated in this order from the upper side (side in contact with the n-type Si substrate 31). It has been done.

Each component of the group III nitride compound semiconductor vertical transistor (HEMT) 100 in FIG. 1 corresponds to the description of the invention according to claim 1 as follows.
The n-type silicon substrate 31 hits the conductive support substrate.
The laminated structure of the multiple metal layer 32, the solder layer 33, and the multiple metal layer 15 corresponds to a conductive layer having at least one layer made of a material different from that of the group III nitride compound semiconductor.
The p-GaN layer 22 which forms the current confinement portion 13bn by limiting the drift portion 13 to the region corresponds to a group III nitride compound semiconductor region having a different conductivity type.
Correspondence between the drift portion, the channel layer, the electricity supply layer, and each electrode is clear.

  Next, FIG. FIG. 1 shows a method for manufacturing a group III nitride compound semiconductor vertical transistor (HEMT) 100 of A. B to FIG. A process diagram of H is shown. The correspondence with the description of claim 4 will be described individually.

First, FIG. The wafer 100s1 having the configuration B is formed as follows. A sapphire substrate (epitaxial growth substrate) 1 having a C-plane as a main surface is prepared, a buffer layer made of aluminum nitride (AlN) is formed by a known method, and a sacrificial layer made of gallium nitride without addition of impurities is formed thereon. (I-GaN) 2 is epitaxially grown by 4 μm. Thereafter, on the sacrificial layer (i-GaN) 2, an electron donating layer (AlGaN, first layer) 11 made of AlGaN with no impurity added and having a thickness of 0.03 μm, a thickness of 0.1 μm, and silicon added Channel layer (n-GaN, second layer) 12 made of GaN having an electron concentration of 1 × 10 ¹⁶ / cm ^3, a p-layer (p-GaN, p-GaN, second layer) having a thickness of 0.5 μm and added with magnesium. A third layer 22 to which an acceptor impurity is added and an AlN layer 21 having a thickness of 0.01 μm are epitaxially grown in this order. Thereafter, the p-layer (p-GaN, third layer) 22 is activated by heating in a nitrogen atmosphere so that the hole concentration becomes 2 × 10 ¹⁸ / cm ³ . In addition, FIG. In B, the description of the buffer layer made of AlN formed between the sapphire substrate (Sapph) 1 and the sacrificial layer (i-GaN) 2 is omitted.

  Next, in order to form the current confinement part 13bn of the drift part 13 made of n-type GaN, the central part of the AlN layer 21 and the p layer (p-GaN, third layer) 22 is etched to form the gap H. Form. At this time, the AlN layer 21 may be etched by wet etching with an alkaline aqueous solution, and then the p layer (p-GaN) 22 may be etched by dry etching. Thus, the channel layer (n-GaN, second layer) 12 is exposed at the bottom of the gap H (FIG. 1.C).

Next, when gallium nitride (GaN) doped with silicon is epitaxially grown, in the gap H, from the surface of the channel layer (n-GaN, second layer) 12 at the bottom and from the surface of the AlN layer 21. Also, epitaxial growth occurs, the gap H is filled, and flat epitaxial growth occurs as a whole wafer. Thus, a drift portion (n-GaN, fourth layer) 13 made of GaN having a carrier concentration of 2 × 10 ¹⁶ / cm ^{3 and} a thickness of 20 μm from the surface of the channel layer (n-GaN, second layer) 12 is formed. To do. At this time, the gap H is filled as a current confinement portion 13bn made of GaN having a carrier concentration of 2 × 10 ¹⁶ / cm ³ (FIG. 1.D).

Thereafter, an n ⁺ contact layer (n ⁺ -GaN) 14 made of GaN doped with silicon having a film thickness of 0.1 μm and an electron concentration of 1 × 10 ¹⁸ / cm ³ is formed by epitaxial growth, and a multiple metal layer 15 is deposited. To form. The multiple metal layer 15 is formed in the order of a titanium (Ti) layer, an aluminum (Al) layer, a nickel (Ni) layer, and a gold (Au) layer from the side close to the n ⁺ contact layer (n ⁺ -GaN) 14. . In this way, a wafer 100s2 is obtained (FIG. 1.E).

  Next, an n-type silicon substrate (n-Si, conductive support substrate) 31 having the same shape as the wafer 100s2 (sapphire substrate (Sapph) 1) is prepared, and an aluminum (Al) layer and titanium (Ti) are sequentially formed on the surface. The multiple metal layer 32 is formed by forming a layer, a platinum (Pt) layer, and a gold (Au) layer. Thereafter, using the gold tin solder (AuSn) 33, the side (conductive layer side) of the n-type silicon substrate (n-Si) 31 on which the multiple metal layer 32 is formed and the multiple metal layer 15 side of the wafer 100s2 are connected. The wafer 100ss is obtained by bonding (FIG. 1.F). Joining may be performed by heating at 350 ° C. for 5 minutes.

  Thereafter, a very small part (thickness of 0.1 μm or less) of the interface of the sacrificial layer (i-GaN) 2 on the sapphire substrate (Sapph) 1 side of the wafer 100 ss is melted by a well-known laser lift-off method. The sapphire substrate (Sapph) 1 is removed (FIG. 1.G). Thereafter, if the sacrificial layer (i-GaN) 2 is removed by dry etching, a wafer 100s with an electron donor layer (AlGaN, first layer) 11 made of AlGaN having no impurities added exposed is obtained (FIG. 1). H).

  Thereafter, the insulating film 10 and the gate electrode 41G are formed on the surface of the electron donating layer (AlGaN, first layer) 11 made of AlGaN to which no impurities are added so as to cover the horizontal occupying surface of the current confinement portion 13bn. In addition, in order to form the source electrode 40S at a distance from the gate electrode 41G, the insulating film 10 and a part of the electron donating layer (AlGaN, first layer) 11 made of AlGaN to which no impurities are added are removed by etching. The channel layer (n-GaN, second layer) 12 made of GaN is exposed. The configuration of the source electrode 40S is as described above. A drain electrode 42D is formed on the back surface of the n-type silicon substrate (n-Si, conductive support substrate) 31. The configuration of the drain electrode 42D is also as described above.

  FIG. In the group III nitride compound semiconductor vertical transistor (HEMT) 100 of A, a two-dimensional electron gas (2-DEG) is present in the vicinity of the interface between the channel layer (n-GaN) 12 and the electron donating layer (AlGaN) 11. It is formed. This is illustrated in FIG. A with thick broken lines. That is, when a voltage is applied between the source 40S / drain 42D and a voltage equal to or higher than the threshold voltage is applied to the gate electrode 41G, a two-dimensional electron gas (2-DEG) is formed from the source 40S to above the current confinement portion 13bn. Electrons are conducted through the constriction portion 13bn, that is, through the drift portion 13 to the drain electrode 42D. On the other hand, when a voltage equal to or lower than the threshold voltage is applied to the gate electrode 41G, the two-dimensional electron gas (2-DEG) does not reach the current confinement portion 13bn from the source 40S, passes through the current confinement portion 13bn (drift portion 13), and drains. Electrons cannot conduct to the electrode 42D.

FIG. 2 is a cross-sectional view showing the configuration of a group III nitride compound semiconductor vertical transistor (HEMT) 200 according to a second specific example of the present invention.
The group III nitride compound semiconductor vertical transistor (HEMT) 200 in FIG. 2 has a p-layer (p-GaN) 22 as thick as 10 μm (the current confinement portion 13bn is also 10 μm in thickness). The layer 21 is not formed, the p layer (p-GaN) 22 is in contact with the n ⁺ contact layer (n ⁺ -GaN) 14, and the potential of the source electrode 40S2 is also applied to the p layer (p-GaN) 22 Basically, each electrode is different from that of the multiple metal layer 152, the metal layer 322, and the solder 332 except that the constituent metals are different. The structure is the same as that of the group III nitride compound semiconductor vertical transistor (HEMT) 100 of A, and the manufacturing method is also substantially the same.

  The configuration in which the current confining portion 13bn of the n drain of the group III nitride compound semiconductor vertical transistor (HEMT) 200 in FIG. 2 is sandwiched between two p layers 22 is a minimum unit super junction structure. That is, the source potential is applied to the two p layers 22, and the depletion layer extends at the interface between the current confinement portion 13 bn and the two p layers 22, and the depletion layer is formed until the current confinement portion 13 bn is closed. Is possible. Thereby, a high breakdown voltage vertical transistor can be obtained.

  In order to form the super junction structure, deep trench etching is required. At this time, if dry etching is combined with wet etching using TMAH, it is easy to make the trench sidewall vertical.

[Modification]
In the above embodiment, the structure of the electron donating layer made of AlGaN to which no impurities are added and the channel layer made of n-GaN is shown, but the present invention is not limited to this. When a two-dimensional electron gas is generated by a group III nitride compound semiconductor, strain between two group III nitride compound semiconductor layers having different compositions is important, and the respective conductivity types are not necessarily important. That is, the electron donating layer and the channel layer may be formed of different compositions, and a two-dimensional electron gas may be generated at the interface. In this case, the donor impurity may be added to any layer, or the donor impurity may not be added to any layer.

  In the first embodiment, FIG. Although a group III nitride compound semiconductor vertical transistor (HEMT) 100 having a configuration in which an AlN layer 21 is provided on the lower surface of a p layer (p-GaN) 22 as shown in A, the AlN layer is represented by a p layer (p− It is good also as a structure provided in the upper and lower sides of (GaN) 22, respectively. According to this configuration, it is possible to form the hole H with high accuracy in the depth direction, that is, the vertical wall surface. This is shown in FIG. A to FIG. A description will be given using C.

FIG. A is shown in FIG. Similar to B, a sapphire substrate (epitaxial growth substrate) 1 having a C-plane as a main surface, a sacrificial layer (i-GaN) 2 made of gallium nitride without addition of impurities, and an electron donation layer (AlGaN made of AlGaN without addition of impurities) 11) After forming a channel layer (n-GaN) 12 made of GaN having an electron concentration of 1 × 10 ¹⁶ / cm ³ doped with silicon, an AlN layer 23 having a thickness of 0.01 μm, a thickness of 0.5 μm, A p-layer (p-GaN) 22 made of GaN doped with magnesium and an AlN layer 21 having a thickness of 0.01 μm are epitaxially grown in this order. Thereafter, the p layer (p-GaN) 22 is activated as in the first embodiment.
Next, in order to form the current confinement portion 13bn of the drift portion 13 made of n-type GaN, the AlN layer 21 is etched by wet etching with an alkaline aqueous solution, and then the p layer (p-GaN) 22 is etched by dry etching. At this time, the AlN layer 23 located under the p layer (p-GaN) 22 serves as a stopper layer for dry etching (FIG. 3.B).
Thereafter, if the AlN layer 23 is etched by wet etching with an alkaline aqueous solution, only the AlN layer 23 can be etched, and the channel layer (n-GaN) 12 is not etched (FIG. 3.C).
Thus, by providing the AlN layer 23, it is possible to form the holes H with high accuracy in the depth direction.

  In the above embodiment, the gate electrode 40G is provided on the electron donating layer made of high resistance AlGaN via the insulating layer made of silicon oxide. However, for example, a direct gate electrode may be formed to form a Schottky gate. .

  Although the HEMT using the two-dimensional electron gas is shown in the above embodiment, a non-HEMT FET is also included in the present invention.

Sectional drawing which shows the structure of the group III nitride compound semiconductor vertical transistor (HEMT) 100 which concerns on the specific 1st Example of this application. Sectional drawing in 1 process of the manufacturing method of group III nitride type compound semiconductor vertical transistor (HEMT) 100. Sectional drawing in 1 process of the manufacturing method of group III nitride type compound semiconductor vertical transistor (HEMT) 100. Sectional drawing in 1 process of the manufacturing method of group III nitride type compound semiconductor vertical transistor (HEMT) 100. Sectional drawing in 1 process of the manufacturing method of group III nitride type compound semiconductor vertical transistor (HEMT) 100. Sectional drawing in 1 process of the manufacturing method of group III nitride type compound semiconductor vertical transistor (HEMT) 100. Sectional drawing in 1 process of the manufacturing method of group III nitride type compound semiconductor vertical transistor (HEMT) 100. Sectional drawing in 1 process of the manufacturing method of group III nitride type compound semiconductor vertical transistor (HEMT) 100. Sectional drawing which shows the structure of the group III nitride type compound semiconductor vertical transistor (HEMT) 200 which concerns on the specific 2nd Example of this application. Sectional drawing in 1 process of the manufacturing method of a modification. Sectional drawing in 1 process of the manufacturing method of a modification. Sectional drawing in 1 process of the manufacturing method of a modification.

Explanation of symbols

100, 200: Group III nitride compound semiconductor vertical transistor (HEMT)
1: Sapphire substrate (epitaxial growth substrate)
2: Sacrificial layer made of GaN (i-GaN)
11: Electron donating layer (first layer) made of AlGaN
12: channel layer (second layer) made of n-GaN
13: Drift portion (fourth layer) made of n-GaN
13nb: Current constriction part of drift part 13 14: Contact layer made of n-GaN 15, 152, 32: Multiple metal layer 21: AlN layer 22: p-GaN layer (third layer)
31: n-type silicon substrate (conductive support substrate)
322: Metal layer 33, 332: Solder layer 40S, 40S2: Source electrode 41G: Gate electrode 42D, 42D2: Drain electrode

Claims (5)

A vertical transistor using a group III nitride compound semiconductor,
A conductive support substrate;
A conductive layer provided on the support substrate and having at least one layer made of a material different from the group III nitride compound semiconductor;
A drift portion made of a group III nitride compound semiconductor formed directly on the conductive layer or via a group III nitride compound semiconductor layer;
A channel layer and an electron donating layer provided on the drift portion, each formed from two group III nitride compound semiconductors having different compositions;
The drift portion has a current confinement portion laterally limited by an insulating region, a group III nitride compound semiconductor region having a lower carrier concentration, or a group III nitride compound semiconductor region having a different conductivity type. ,
On the surface of the electron donating layer above the current confinement portion of the drift portion, a gate electrode via an insulator or by Schottky connection,
A source electrode capable of supplying current to the channel layer in a lateral direction of the gate electrode;
A group III nitride compound semiconductor vertical transistor comprising a drain electrode on the back surface of the support substrate. By allowing or preventing the diffusion of the two-dimensional electron gas in the lateral direction above the current confinement part of the drift part in the vicinity of the interface between the channel layer and the electron donating layer by the gate electrode, 2. The group III nitride compound semiconductor vertical transistor according to claim 1, wherein the group III nitride compound semiconductor vertical transistor is a high electron mobility transistor that allows or blocks transmission of carriers to the drain electrode. The current confinement part of the drift part is region-limited in the lateral direction by a group III nitride compound semiconductor region having a different conductivity type,
3. The group III nitride compound semiconductor vertical transistor according to claim 2, wherein the potential of the source electrode is also applied to a group III nitride compound semiconductor region having a different conductivity type. On the epitaxial growth substrate,
At least with a sacrificial layer,
A first layer comprising a group III nitride compound semiconductor containing at least aluminum;
A second layer comprising a group III nitride compound semiconductor and constituting a channel layer;
After epitaxially forming a third layer made of a group III nitride compound semiconductor to which an acceptor impurity is added,
Partially etching the third layer to partially expose the second layer;
After epitaxially growing a fourth layer made of a group III nitride compound semiconductor and forming a drift portion on the exposed second layer,
Connect the conductive layer side of the conductive support substrate formed with a conductive layer on the surface directly or through another group III nitride compound semiconductor layer or conductive layer to the drift portion,
Removing at least the epitaxial growth substrate and the sacrificial layer to expose the first layer;
Forming a gate electrode by Schottky connection or via an insulating layer above the current confinement portion of the drift portion of the exposed first layer;
A method of manufacturing a group III nitride compound semiconductor vertical transistor, comprising forming a source electrode capable of supplying current to the second layer by ohmic connection in a lateral direction of the gate electrode. 5. The group III nitride compound semiconductor vertical transistor according to claim 4, wherein the source electrode is formed so as to be in contact with the group III nitride compound semiconductor region to which the acceptor impurity is added. Production method.

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