[go: up one dir, main page]

JP2007529815A - 信号送信装置及び信号送信のための方法 - Google Patents

信号送信装置及び信号送信のための方法 Download PDF

Info

Publication number
JP2007529815A
JP2007529815A JP2007503488A JP2007503488A JP2007529815A JP 2007529815 A JP2007529815 A JP 2007529815A JP 2007503488 A JP2007503488 A JP 2007503488A JP 2007503488 A JP2007503488 A JP 2007503488A JP 2007529815 A JP2007529815 A JP 2007529815A
Authority
JP
Japan
Prior art keywords
pci express
endpoint device
communication link
tag field
express endpoint
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2007503488A
Other languages
English (en)
Japanese (ja)
Inventor
デイヴィッド アール エヴォイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips NV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips NV, Koninklijke Philips Electronics NV filed Critical Koninklijke Philips NV
Publication of JP2007529815A publication Critical patent/JP2007529815A/ja
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Near-Field Transmission Systems (AREA)
JP2007503488A 2004-03-19 2005-03-19 信号送信装置及び信号送信のための方法 Withdrawn JP2007529815A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US55450404P 2004-03-19 2004-03-19
PCT/IB2005/051031 WO2005091156A2 (en) 2004-03-19 2005-03-19 Signaling arrangement and approach therefor

Publications (1)

Publication Number Publication Date
JP2007529815A true JP2007529815A (ja) 2007-10-25

Family

ID=34962013

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007503488A Withdrawn JP2007529815A (ja) 2004-03-19 2005-03-19 信号送信装置及び信号送信のための方法

Country Status (5)

Country Link
EP (1) EP1728170A2 (zh)
JP (1) JP2007529815A (zh)
KR (1) KR20060130664A (zh)
CN (1) CN1934558A (zh)
WO (1) WO2005091156A2 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009217407A (ja) * 2008-03-07 2009-09-24 Nec Corp データ通信システムのデットロック回避方法及びそのシステム並びにその制御プログラム
JP2012529094A (ja) * 2009-06-02 2012-11-15 インターナショナル・ビジネス・マシーンズ・コーポレーション ペリフェラル・コンポーネント・インターコネクト(pci)エクスプレス・ネットワークにおける損失されたポステッド・ライト・パケットおよび順序の狂ったポステッド・ライト・パケットの検出
WO2015155997A1 (ja) * 2014-04-11 2015-10-15 日本電気株式会社 設定装置、制御装置、設定方法及びネットワークスイッチ

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5057548B2 (ja) * 2006-05-02 2012-10-24 株式会社リコー 画像データ転送装置及び画像データ転送方法
US8139575B2 (en) * 2007-06-29 2012-03-20 International Business Machines Corporation Device, system and method of modification of PCI express packet digest
US7702827B2 (en) 2007-06-29 2010-04-20 International Business Machines Corporation System and method for a credit based flow device that utilizes PCI express packets having modified headers wherein ID fields includes non-ID data
EP3771889A1 (de) 2019-07-31 2021-02-03 Siemens Aktiengesellschaft Messvorrichtung

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5751723A (en) * 1996-07-01 1998-05-12 Motorola, Inc. Method and system for overhead bandwidth recovery in a packetized network
US7120722B2 (en) * 2002-05-14 2006-10-10 Intel Corporation Using information provided through tag space

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009217407A (ja) * 2008-03-07 2009-09-24 Nec Corp データ通信システムのデットロック回避方法及びそのシステム並びにその制御プログラム
JP2012529094A (ja) * 2009-06-02 2012-11-15 インターナショナル・ビジネス・マシーンズ・コーポレーション ペリフェラル・コンポーネント・インターコネクト(pci)エクスプレス・ネットワークにおける損失されたポステッド・ライト・パケットおよび順序の狂ったポステッド・ライト・パケットの検出
WO2015155997A1 (ja) * 2014-04-11 2015-10-15 日本電気株式会社 設定装置、制御装置、設定方法及びネットワークスイッチ

Also Published As

Publication number Publication date
EP1728170A2 (en) 2006-12-06
WO2005091156A3 (en) 2006-03-02
CN1934558A (zh) 2007-03-21
WO2005091156A2 (en) 2005-09-29
KR20060130664A (ko) 2006-12-19

Similar Documents

Publication Publication Date Title
US7340548B2 (en) On-chip bus
US8443126B2 (en) Hot plug process in a distributed interconnect bus
CN103490852B (zh) 用于处理与点到点数据链路有关的数据的方法和装置
JP6517243B2 (ja) リンクレイヤ/物理レイヤ(phy)シリアルインターフェース
US8291146B2 (en) System and method for accessing resources of a PCI express compliant device
US6434633B1 (en) Method and apparatus for facilitating AC-link communications between a controller and a slow peripheral of a codec
JP2000082035A (ja) 様々な周波数動作をサポ―トする複数の周辺構成要素相互接続バスをサポ―トする方法およびシステム
WO2003058470A1 (en) Communicating message request transaction types between agents in a computer system using multiple message groups
TW202026895A (zh) 聚集帶內中斷
US11921652B2 (en) Method, apparatus and system for device transparent grouping of devices on a bus
US11797468B2 (en) Peripheral component interconnect express device and computing system including the same
US5978869A (en) Enhanced dual speed bus computer system
JP2007529815A (ja) 信号送信装置及び信号送信のための方法
CN111737183A (zh) 一种服务器及一种i2c总线的通信故障处理方法和系统
US8533377B2 (en) System and method for allocating transaction ID in a system with a plurality of processing modules
US7577877B2 (en) Mechanisms to prevent undesirable bus behavior
JP4630288B2 (ja) 受信したシリアル転送アライメントシーケンスのレートの検証
US8135923B2 (en) Method for protocol enhancement of PCI express using a continue bit
US9025614B2 (en) Unified system networking with PCIE-CEE tunneling
KR100333585B1 (ko) 데이터 처리 시스템 및 이 데이터 처리 시스템에서 주변 장치간의 충돌 제거 방법
US6901472B2 (en) Data-processing unit with a circuit arrangement for connecting a first communications bus with a second communications bus
WO2003060733A1 (en) Bus architecture and communication protocol

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20080603