Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
  • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
  • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation

Definitions

• the present invention relates generally to passing information and, more particularly, to the passing of information involving the use of a tag (or similar) field for communicating information.
• Many different types of electronic communications are carried out for a variety of purposes and with a variety of different types of devices and systems.
• One type of electronic communications system involves those communications associated with BUS- type communications between two or more different components.
• computers typically include a central processing unit (CPU) that communicates with peripheral devices via a bus. Instructions and other information is passed between the CPU and the peripheral devices on a communications BUS or other link.
• PCI Peripheral Component Interconnect
• PCI is an interconnection system between a microprocessor and attached devices in which expansion slots are spaced closely for high speed operation.
• a computer can support new PCI cards while continuing to support Industry Standard Architecture (ISA), expansion cards, which is an older standard.
• ISA Industry Standard Architecture
• PCI is designed to be independent of microprocessor design and to be synchronized with the clock speed ofthe microprocessor.
• PCI uses active paths (on a multi-drop bus) to transmit both address and data signals, sending the address on one clock cycle and data on the next.
• the PCI bus can be populated with adapters requiring fast accesses to each other and/or system memory and that can be accessed by a host processor at speeds approaching that of the processor's full native bus speed.
• PCI-type architecture is widely implemented, and is now installed on most desktop computers.
• PCI Express architecture exhibits similarities to PCI architecture with certain changes.
• PCI Express architecture employs a switch that replaces the multi-drop bus ofthe PCI architecture with a switch that provides fan-out for an input-output (I/O) bus. The fan- out capability ofthe switch facilitates a series of connections for add-in, high-performance I/O.
• the switch is a logical element that may be implemented within a component that also contains a host bridge.
• a PCI switch can logically be thought of, e.g., as a collection of PCI-to-PCI bridges in which one bridge is the upstream bridge that is connected to a private local bus via its downstream side to the upstream sides of a group of additional PCI-to-PCI bridges.
• information such as that indicating synchronization events is desirably signaled to devices, such as PCI Express endpoint devices, communicatively coupled to one another.
• this signaling involves the use of interrupts requiring multiple packets, vendor unique message processing or other processing that tends to slow the processing of communications.
• interrupts generally involve periodic breaks in communication on the bus, thus interrupting streaming data such as write data. These breaks tend to increase the communication overhead of synchronization events (e.g., by increasing latency and tying up communication bandwidth).
• PCI Express communications approaches include PCI Express communications approaches.
• Various aspects ofthe present invention involve communication approaches for a variety of computer circuits, such as those including communication BUS-type structures (e.g., PCI-type structures) and others.
• the present invention is exemplified in a number of implementations and applications, some of which are summarized below.
• information is included in a tag field of data posted to a communications link, such as posted request data.
• This posted data is communicated between devices coupled to the link and can be used to. signal, for example, synchronous events.
• synchronous events are signaled to PCI Express devices by setting a tag field of posted write request data to a "true" value.
• the tag field can be used in accordance with PCI Express communication approaches to send data relating to the synchronous events from a PCI Express endpoint device to another PCI Express endpoint device using a common PCI
• the tag field can be implemented in accordance with PCI Express requirements allowing the tag field for such requests to include any value.
• the information in the tag field can be transferred across hubs and switches and is correspondingly compatible with PCI Express protocol requirements and checkers.
• FIG. 1 is an arrangement for communications involving the signaling of synchronous events between devices communicatively coupled with a link, according to an example embodiment ofthe present invention
• FIG. 2 is a flow diagram for an approach to signaling synchronous events between endpoints on a PCI Express link, according to another example embodiment ofthe present invention.
• a communications arrangement includes a communications link with at least two endpoint type devices adapted for passing information using a tag (or similar) field of communications over the communications link (e.g., via the tag field of posted write data).
• the communications link may include, for example, a PCI Express bus, switch and/or other component(s).
• the tag field communication can be effected while facilitating the passing ofthe selected information with other communications (i.e., that do not necessarily require or disallow use ofthe tag field).
• the above-discussed approach is implemented with a PCI
• the tag field is identified by a Requester function and returned by a Completer function, and, in some instances, where the Requester function involves a posted write that does not require completion.
• the Requester function is implemented by a Requester (a logical device that introduces a sequence, or logical transfer into the PCI Express domain) that implements a Request, or packet.
• the Completer function is implemented by a Completer (a logical device addressed by the Requester) that generates a Completion, or packet, in response to a Request and that terminates, or partially terminates a sequence.
• the Requester function uses the tag field in any manner, such as for signaling synchronous events.
• PCI Express-compliant See PCI Express-compliant
• the communications system 100 includes a PCI Express switch 110 adapted to pass communications among a host 105 and a plurality of endpoint devices including endpoint devices 150 and 152.
• the host 105 e.g., a CPU, network-based chipset, a host bridge or another PCI Express type link
• a plurality of downstream ports including downstream ports 140, 142, 144 and 146 are also coupled to the virtual PCI Express bus 130, each downstream port being adapted to pass data to and receive data from a PCI Express endpoint device.
• Each ofthe endpoint devices 150 and 152 are configured for communicating synchronous event information using the tag field of posted write packets passed on the virtual bus 130. For instance, when endpoint device 150 is communicating information in packet form via the virtual bus 130, a tag field in a portion ofthe packet can be set with data related to a synchronous event. Endpoint device 152 then parses the packet(s) and uses information in the tag field to ascertain the synchronous event information.
• endpoint device 150 acts as a requester in posting write data, with a write request being posted to the virtual PCI Express bus 130 in packet form.
• This write request includes a "tag in" signal (e.g., one or more bits) in a header ofthe write request, alerting recipients ofthe write request to a synchronous event condition.
• the tag in data is set when the synchronous event is "true” and removed (or not set) when the synchronous event is not true.
• An endpoint device e.g., endpoint device 152 parsing the posted write request identifies the synchronous event using the tag in data and responds to the synchronization event signal from endpoint device 150 with appropriate action.
• This endpoint device acts here as a completer device that does not respond to the endpoint device 150 (i.e., with the requests including tag field signaling not requiring completion).
• the intended recipient ofthe posted write data is not necessarily the intended recipient ofthe synchronous event signal.
• the completer device 152 and/or another endpoint device coupled to one ofthe downstream ports 140-146 may process the synchronous event data, while a different endpoint device processes other portions ofthe posted write data.
• an adapter is used to create packets for transmission on the virtual PCI Express bus 130 in response to requests by each endpoint device.
• Each adapter may be implemented, for example, in connection with a PCI Express endpoint device generating a posted write or at the PCI Express switch 110.
• Each adapter has an input and a corresponding output (e.g., a single bit or an extended bit up to about 8 bits wide) that is used in providing the synchronous event signal in the tag field.
• the adapter is used with input and output signals for providing the synchronous event signal as follows.
• An input signal is sampled with an address at an input interface with the adapter (e.g., a dynamic termination logic (DTL) target interface).
• This input signal e.g., one or more bits
• An output signal e.g., one or more bits
• the most significant bit ofthe tag field (bit 7 of byte 6) for the memory write drives this output signal from the header of all memory write commands with timing consistent with memory address out timing.
• the output signal is zero for all other cycles (i.e., cycles in which synchronous event-signaling is not carried out) and is only valid when the address out is valid.
• synchronization signaling is disabled when connecting to a non-user PCI Express component and/or system. For instance, when the endpoint devices 150 and 152 are of different types, with the endpoint device 152 implemented with a non- user PCI Express component and/or system, signaling from the endpoint device 150 is disabled. This disabling may be implemented, for example, using a switch or gate type approach. In addition, this approach may be implemented as discussed above in connection with the selective use of synchronous event signaling with compatible manufacturers of endpoint devices. The approaches discussed above in connection with FIG.
• the tag field of posted write data in a PCI Express arrangement is implemented and defined such that each outstanding transaction requiring a complete (non posted operation requiring a response) has a unique tag. These outstanding transactions are not implemented for communicating synchronous event data in the tag field, and are compliant with PCI Express type communications.
• read operations use the four least significant bits (LSBs) with the four MSBs unused and accordingly being implemented with a "0" value.
• Completion logic is configured to ignore the tag field for posted writes, which is typically implemented for PCI Express type communications, as discussed above.
• the tag field is implemented for synchronous event communication with posted write data (i.e., data not requiring a complete).
• the length ofthe tag field is tailored to the particular application in which the PCI Express arrangement is employed and is further implemented in accordance with available bits. For example, 5 bits may typically be reserved for the tag field in many PCI Express implementations. In other implementations, the tag field is implemented with 8 or more bits (e.g., when an extended tag is enabled) as discussed in the preceding paragraph.
• a JetStream PCI Express core available from Perle Systems of Nashville, Tennessee is used in connection with a tag field synchronization approach.
• endpoint devices implemented for synchronous event signaling with tag fields are configured to limit event signaling to selected device types. For example, when synchronous events are to be signaled for receipt by devices that meet particular manufacturer criteria, a code or other recognition approach is implemented for ensuring that endpoint devices receiving the synchronous event signals meet the criteria (e.g., are manufactured by the particular manufacturer).
• Synchronous event signaling can be enabled after the code or other recognition approach identifies that the criteria have been met. For instance, when synchronous event signaling is to be carried out for two PCI Express endpoint devices having a common manufacturer, signaling by a first PCI Express endpoint device is enabled after determining that the other PCI Express endpoint device is ofthe same manufacturer.
• the tag in signal (e.g., single bit or multiple bits) is added to the tag field using, for instance, an adapter that places the tag signal in the communication header. This tag in signal is set when the 'Synchronization Event' is true, for instance, when a last write or vertical sync pulse is true, with timing being optionally implemented substantially identical to any address line.
• a tag out signal (e.g., single bit or multiple bits) is added to the tag field ofthe communication in order to remove the synchronization event information from additional communications effected via the adapter.
• the tag out can be implemented in a similar manner to the implementation of the tag in signal discussed above.
• an adapter can be used to take bit(s) out of the tag field of a header in a manner that is similar to the extraction of an address bit from a header, thus providing a new signal(s) with the same timing as address out timing.
• FIG. 2 shows a flow diagram for synchronous event signaling, according to another example embodiment ofthe present invention.
• write data is generated at a first PCI Express endpoint device for posting to a PCI Express communications link. If a synchronous event is active at block 220, a tag field header ofthe write data is set at block 230, indicating the active nature ofthe synchronous event. At block 240, the write data is posted with a synchronous event signal (e.g., data indicative of a synchronous event, such as a "true" bit). If a synchronous event is not active at block 220, write data is instead posted at block 225 without a synchronous event signal. Posted write data is accessed at block 250 (e.g., received at another PCI Express endpoint device).
• a synchronous event signal e.g., data indicative of a synchronous event, such as a "true" bit
• the posted write data has a synchronous event signal at block 260, it is processed with the synchronous event signal at block 270. If the posted write data does not have a synchronous event signal at block 260, it is processed (without reference to synchronization) wt block 280. In some instances, the synchronous event signal is processed without processing the write data when, for example, a particular synchronous event is applicable to a PCI Express endpoint device that is not necessarily the intended recipient of other posted write data.
• the approaches discussed herein may be implemented with a variety of PCI Express type arrangements and approaches.
• this approach is, compatible with the PCI Express type protocols for which, regarding requests that do not require completion (posted requests), the value in the tag field is undefined and may contain any value (see PCI Express Base Specification Revision 1.0a, referenced above).
• This approach is further compatible with PCI Express protocols indicating that, for posted requests, the value in the tag field must not affect receiver processing ofthe request; non zero tag bits are thus legal.
• this approach can be implemented such that the tag field does not affect receiver processing ofthe request.

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• 2005
  • 2005-03-19 WO PCT/IB2005/051031 patent/WO2005091156A2/en not_active Application Discontinuation
  • 2005-03-19 KR KR1020067019311A patent/KR20060130664A/ko not_active Withdrawn
  • 2005-03-19 EP EP05718562A patent/EP1728170A2/en not_active Withdrawn
  • 2005-03-19 JP JP2007503488A patent/JP2007529815A/ja not_active Withdrawn
  • 2005-03-19 CN CNA2005800087305A patent/CN1934558A/zh active Pending

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