JP2007134432A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method which can improve the embeddability of a metal gate electrode in a gate opening. <P>SOLUTION: The semiconductor device comprises a gate insulation film 3 formed on a substrate 1, a metal gate electrode 4 containing a metal which is formed on the gate insulation film 3, and a side wall insulation film 5 formed on the side wall of the metal gate electrode 4. The side wall insulation film 5 consists of a first insulation film 6 formed on a lower part of the side wall of the metal gate electrode 4, and a second insulation film 7 which is outside the first insulation film 6 and is formed on the overall side wall of the metal gate electrode 4. The width of the upper part of the metal gate electrode 4 is larger than that of a lower part thereof. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a metal gate containing a metal and a manufacturing method thereof.

  As transistor generation progresses, scaling by miniaturization is constantly performed. In the international semiconductor technology roadmap (ITRS), a gate length (Lg) of 20 nm or less is expected in a transistor called hp (half pitch) 45 nm generation. For this generation of transistors, it is necessary to scale the effective thickness (EOT: Effective Oxide Thickness) of the gate insulating film and the depth (Xj) of the diffusion layer together with the gate length.

  The scaling of the effective thickness EOT of the gate insulating film is necessary for securing the driving capability (Ids), and the scaling of the depth Xj of the diffusion layer is necessary for suppressing the short channel effect (SCE).

  Here, in order to reduce the effective film thickness of the gate insulating film while suppressing the generation of the gate leakage current, a high dielectric constant (High-k) insulating film may be introduced as the gate insulating film instead of the silicon oxide film. It is being considered. Also, a technique for suppressing gate depletion by introducing a metal gate electrode instead of the polysilicon gate electrode has been studied.

  Materials used for the metal gate electrode, for example, tungsten (W), titanium (Ti), hafnium (Hf), ruthenium (Ru), and Ir (iridium) are highly reactive materials. For this reason, when heat treatment is performed at a high temperature, it reacts with the gate insulating film to cause film quality deterioration of the gate insulating film. Therefore, it is preferable not to perform high-temperature heat treatment after the metal gate electrode is formed. As one method for realizing this, a damascene gate process has been proposed (see Patent Document 1).

In the damascene gate process, after forming a dummy gate made of polysilicon or the like, a diffusion layer to be an extension portion and a source / drain portion is formed, and after forming an interlayer film, the dummy gate is removed. As a result, a buried gate opening is formed in a self-aligned manner with respect to the diffusion layer. Thereafter, a gate insulating film is formed, and a metal gate electrode is embedded in the gate opening. Since the high-temperature heat treatment necessary for activating the diffusion layer has already been performed, the reliability of the metal gate electrode can be ensured.
JP 2003-258121 A

  Incidentally, the gate length required in the hp 45 nm generation is 20 nm or less. If the height of the gate is 50 to 100 nm, the aspect ratio of this generation gate opening is 2.5 to 5.0. As a film formation method for the metal gate electrode material, a sputtering method is mainly used. However, in the case of the sputtering method, when the aspect ratio becomes high, there is a problem that the upper part of the gate opening becomes an overhang shape, so that it becomes difficult to fill the gate opening and voids are generated.

  Thus, in the metal gate electrode formation process, it is required to improve the embedding property of the metal gate electrode in the gate opening.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device having a gate electrode with improved embeddability.
Another object of the present invention is to provide a method of manufacturing a semiconductor device that can improve the embedding property of a metal gate electrode in a gate opening.

  In order to achieve the above object, a semiconductor device according to the present invention includes a gate insulating film formed on a substrate, a metal gate electrode including a metal formed on the gate insulating film, and a sidewall of the metal gate electrode. A sidewall insulating film formed, wherein the sidewall insulating film is formed on a side wall of a lower layer portion of the metal gate electrode, outside the first insulating film, and A second insulating film formed on the entire side wall of the metal gate electrode, and the width of the upper layer portion of the metal gate electrode is wider than the width of the lower layer portion of the metal gate electrode.

In the semiconductor device of the present invention, the first insulating film and the second insulating film are formed on the side wall of the lower layer portion of the metal gate electrode, and the second insulating film is formed on the side wall of the upper layer portion of the metal gate electrode. Yes. As a result, the width of the upper layer portion of the metal gate electrode is larger than the width of the lower layer portion of the metal gate electrode by the thickness of the first insulating film.
Therefore, since the upper part of the gate opening defined by the sidewall insulating film is expanded, the embeddability of the metal gate electrode in the gate opening is improved.

  In order to achieve the above object, a semiconductor device of the present invention sandwiches two extension layers formed on the substrate and the channel region and the end portions of the two extension layers so as to sandwich the channel region of the substrate. The sidewall insulating film formed on the extension layer, the gate insulating film formed on the channel region of the substrate and the end of the extension layer, the sidewall insulating film and the extension layer And the width of the upper layer portion of the metal gate electrode is wider than the width of the lower layer portion of the metal gate electrode.

  In the semiconductor device of the present invention, two extension layers are formed on the substrate so as to sandwich the channel region, and the sidewalls are formed on the extension layer so as to sandwich the channel region and the end regions of the two extension layers. An insulating film is formed. As a result, the width of the gate opening defined by the sidewall insulating film and the extension layer is wider in the upper part than in the lower part. Since the upper part of the gate opening is widened, the embedding property of the metal gate electrode in the gate opening is improved.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a dummy gate on a substrate, and at least a first insulating film and a second insulating film are sequentially stacked on a side wall of the dummy gate. Forming a sidewall insulating film; forming an interlayer insulating film for embedding the sidewall insulating film and exposing the upper surface of the dummy gate; and etching the upper layer portion of the dummy gate to form a groove A step of removing the first insulating film on the sidewall of the trench by etching using a lower layer portion of the dummy gate as a mask, and removing the lower layer portion of the dummy gate to expose the substrate, Forming a gate opening having a wider upper portion than the lower portion, forming a gate insulating film on the substrate exposed in the gate opening, and And forming a metal gate electrode to embed over preparative opening.

  In the semiconductor device manufacturing method of the present invention, a sidewall insulating film in which at least a first insulating film and a second insulating film are sequentially laminated is formed on the side wall of the dummy gate, and the upper layer portion of the dummy gate is etched to form a groove. Then, the first insulating film on the sidewall of the trench is etched using the lower layer of the dummy gate as a mask. Thereafter, by removing the lower layer portion of the dummy gate, a gate opening is formed which has a wider upper portion than the lower portion and exposes the semiconductor substrate. By expanding the upper part of the gate opening, the filling property of the metal layer is improved.

  In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes a step of forming a dummy gate on a substrate, a step of epitaxially growing an extension layer on the substrate on both sides of the dummy gate, and the dummy gate. Forming a side wall spacer on the side wall, forming a side wall insulating film on the side wall of the dummy gate via the side wall spacer, filling the side wall insulating film, and forming an upper surface of the dummy gate Forming an interlayer insulating film to be exposed; removing the dummy gate and the sidewall spacer to expose the substrate; forming a gate opening having a wider upper portion than a lower portion; and the gate opening Forming a gate insulating film on the substrate and the end of the extension layer exposed at the portion; And forming a metal gate electrode embedding the gate opening.

  In the method of manufacturing a semiconductor device according to the present invention, extension layers are formed on both sides of the dummy gate, and sidewall spacers are formed on the extension layer on the extension layer. Thereafter, a sidewall insulating film and an interlayer insulating film are formed, and the dummy gate and the sidewall spacer are removed, thereby forming a gate opening having a width wider than the lower portion by the thickness of the sidewall spacer. By expanding the upper part of the gate opening, the filling property of the metal layer is improved.

According to the semiconductor device of the present invention, the embedding property of the metal gate electrode can be improved, and a semiconductor device having a reliable gate electrode can be realized.
According to the semiconductor device manufacturing method of the present invention, it is possible to improve the embedding property of the metal gate electrode in the gate opening.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view of the semiconductor device according to the present embodiment.

  For example, an element isolation insulating film 2 made of silicon oxide for partitioning an active region is formed on a semiconductor substrate 1 made of silicon. In the case of an nMOS transistor, a p-well is formed in the active region, and in the case of a pMOS transistor, an n-well is formed in the active region.

  A metal gate electrode 4 is formed on the semiconductor substrate 1 via a gate insulating film 3. The gate insulating film 3 is a high dielectric constant film (High-k insulating film) having a dielectric constant higher than that of the silicon oxide film. An example of the high dielectric constant film is hafnium oxide. However, the gate insulating film 3 may be a silicon oxide film.

  The metal gate electrode 4 is made of a pure metal material, an alloy, or a metal compound, and is made of, for example, tungsten (W), titanium (Ti), hafnium (Hf), ruthenium (Ru), or Ir (iridium).

  A sidewall insulating film 5 is formed on the side wall of the metal gate electrode 4. The sidewall insulating film 5 is formed by laminating a first insulating film 6 and a second insulating film 7 in order from the metal gate electrode 4 side. The first insulating film 6 is, for example, a silicon nitride film, and the second insulating film 7 is, for example, a silicon oxide film.

  The first insulating film 6 is formed on the side wall of the lower layer portion of the metal metal gate electrode 4. The second insulating film 7 is formed on the entire side wall of the metal gate electrode 4 outside the first insulating film 6. The upper layer portion of the metal gate electrode 4 is formed on the first insulating film 6. For this reason, the width of the upper layer portion of the metal gate electrode 4 is wider than the width of the lower layer portion of the metal gate electrode 4.

  Extension portions 11 are formed on the semiconductor substrate 1 on both sides of the metal gate electrode 4 and immediately below the sidewall insulating film 5. A source / drain part 12 deeper than the extension part 11 is formed on the semiconductor substrate 1 outside the extension part 11.

  In the case of an nMOS transistor, the extension part 11 and the source / drain part 12 are n-type semiconductors. In the case of a pMOS transistor, the extension part 11 and the source / drain part 12 are p-type semiconductors. The semiconductor device may have a raised extension structure in which an epitaxial layer is formed as an extension portion on the semiconductor substrate 1. Further, epitaxial layers may be formed on the semiconductor substrate 1 as extension portions and source / drain portions, respectively.

  A silicide layer 13 is formed on the surface layer of the source / drain portion 12 exposed from the sidewall insulating film 5. The silicide layer 13 is made of, for example, cobalt silicide, nickel silicide, or platinum silicide.

  In the semiconductor device according to this embodiment, the first insulating film 6 and the second insulating film 7 are formed on the side wall of the lower layer portion of the metal gate electrode 4, and the second insulating film is formed on the side wall of the upper layer portion of the metal gate electrode 4. An insulating film 7 is formed. As a result, the width of the upper layer portion of the metal gate electrode 4 is larger than the width of the lower layer portion of the metal gate electrode 4 by the thickness of the first insulating film 6.

  Accordingly, since the upper part of the gate opening 16 defined by the sidewall insulating film 5 is expanded, the embedding property of the metal gate electrode 4 in the gate opening 16 is improved. As a result, generation of voids in the metal gate electrode 4 can be suppressed, and a semiconductor device including a reliable gate electrode can be realized.

  In addition, since the width of the upper layer portion of the metal gate electrode 4 is larger than the width of the lower layer portion of the metal gate electrode 4, the resistance of the metal gate electrode 4 can be reduced. Therefore, it is possible to realize a semiconductor device including the low-resistance metal gate electrode 4 without gate depletion.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.

  As shown in FIG. 2A, after an element isolation insulating film 2 is formed on a semiconductor substrate 1 made of, for example, silicon by STI (Shallow Trench Isolation) technique, an n well or a p well is formed by ion implantation. Further, if necessary, ion implantation for adjusting a threshold value is performed.

  Next, as shown in FIG. 2B, a laminated pattern of a dummy gate insulating film 21, a dummy gate 22, and a mask layer 23 is formed on the semiconductor substrate 1. A silicon oxide film having a thickness of 0.1 to 5 nm is formed as the dummy gate insulating film 21 by a thermal oxidation method. Thereafter, a polysilicon film to be the dummy gate 22 is formed on the silicon oxide film by a CVD method. The thickness of the polysilicon film is, for example, 100 to 200 nm. As the dummy gate 22, an amorphous silicon film or an amorphous silicon film containing impurities may be formed. Subsequently, a silicon nitride film is formed as a mask layer on the polysilicon film. A resist pattern is formed on the silicon nitride film by lithography, and the silicon nitride film is etched using the resist pattern as a mask, thereby forming a mask layer 23 made of silicon nitride. The pattern of the mask layer 23 is a gate electrode pattern. Thereafter, the polysilicon film is dry-etched by etching using the mask layer 23. Thereby, the dummy gate 22 is processed. The minimum line width of the dummy gate 22 is several nanometers to several tens of nanometers. The mask layer 23 may be formed of a silicon oxide film.

  Next, as shown in FIG. 3A, a silicon nitride film is formed on the entire surface so as to cover the dummy gate 22 by a CVD method, and etched back to thereby form a first sidewall spacer 24 on the sidewall of the dummy gate 22. Form. The thickness of the first sidewall spacer 24 is 5 to 10 nm. The first sidewall spacer 24 may be formed of a silicon oxide film.

  Next, as shown in FIG. 3B, the extension portions 11 are formed in the semiconductor substrate 1 on both sides of the dummy gate 22 by ion implantation using the dummy gate 22 and the first sidewall spacer 24 as a mask. Due to the presence of the first sidewall spacer 24, the extension portion 11 is ion-implanted slightly away from the gate. For this reason, it is possible to suppress the short channel effect that is caused by the diffusion of the implanted impurities by the subsequent heat treatment. In forming the extension portion 11 of the nMOS transistor, an n-type impurity such as arsenic or phosphorus is ion-implanted. In forming the extension portion 11 of the pMOS transistor, a p-type impurity such as boron is ion-implanted.

  Next, as shown in FIG. 4A, sidewall insulating films 5 are formed on both sides of the dummy gate 22. In forming the sidewall insulating film 5, first, a first insulating film 6 made of silicon nitride and a second insulating film 7 made of silicon oxide are formed by CVD to cover the dummy gate 22. Subsequently, the second insulating film 7 and the first insulating film 6 are etched back to form the first insulating film 6 and the second insulating film 7 on the side wall of the dummy gate 22 via the first side wall spacer 24. Sidewall insulating films 5 are formed.

  Next, as shown in FIG. 4B, a source deeper than the extension portion 11 is formed in the semiconductor substrate 1 on both sides of the sidewall insulating film 5 by ion implantation using the dummy gate 22 and the sidewall insulating film 5 as a mask. -The drain part 12 is formed. In forming the source / drain portion 12 of the nMOS transistor, an n-type impurity such as arsenic or phosphorus is ion-implanted. In the formation of the source / drain portion 12 of the pMOS transistor, p-type impurities such as boron are ion-implanted.

  Next, as shown in FIG. 5A, a silicide layer 13 is formed on the surface layer portion of the source / drain portion 12 exposed from the sidewall insulating film 5. In forming the silicide layer 13, first, a metal film is formed on the entire surface so as to cover the source / drain portion 12. As the metal film, nickel, cobalt or platinum is formed. Subsequently, heat treatment is performed to react silicon in the surface layer portion of the source / drain portion 12 with the metal film, thereby forming the silicide layer 13. Finally, the unreacted metal film is removed. Thereby, the silicide layer 13 is formed.

  Next, as shown in FIG. 5B, an interlayer insulating film 14 made of silicon oxide is formed on the semiconductor substrate 1 by a CVD method so as to cover the dummy gate 22.

  Next, as shown in FIG. 6A, the interlayer insulating film 14 is removed by CMP (Chemical Mechanical Polishing) until the upper surface of the mask layer 23 is exposed. Note that the interlayer insulating film 14 may be removed by CMP at this time until the upper surface of the dummy gate 22 is exposed.

  Next, as shown in FIG. 6B, the mask layer 23 and the dummy gate upper layer exposed from the interlayer insulating film 14 are etched to leave the dummy gate lower layer 22a. As a result, a trench 15 is formed in the interlayer insulating film 14. In etching the mask layer 23 made of silicon nitride, hot phosphoric acid is used.

  Next, as shown in FIG. 7A, the first sidewall spacer 24 and the first insulating film 6 exposed in the trench 15 are removed by etching using the dummy gate lower layer portion 22a as a mask. For this etching, hot phosphoric acid is used.

  Next, as shown in FIG. 7B, the dummy gate lower layer portion 22 a and the dummy gate insulating film 21 are etched to expose the semiconductor substrate 1. As a result, the gate opening 16 having a wider upper layer portion than the lower layer portion is formed. The depth of the gate opening 16 is 50 to 100 nm.

Next, as shown in FIG. 8A, the gate insulating film 3 is formed on the semiconductor substrate 1 exposed in the gate opening 16. The gate insulating film 3 is formed so as to cover the gate opening 16. As the gate insulating film 3, a high dielectric constant film, for example, a hafnium oxide film is formed. The hafnium oxide film is formed by forming a hafnium nitride film by a CVD method using HfCl ₂ and NH ₃ , a CVD method using an organic Hf gas, or a sputtering method using a hafnium nitride target. It can be formed by oxidizing.

  Next, as shown in FIG. 8B, a metal layer 4a that fills the gate opening 16 is formed. As the metal layer 4a, a pure metal material layer, an alloy layer, or a metal compound layer is formed. For example, a tungsten film, a titanium film, a hafnium film, a ruthenium film, or an iridium film is formed by a sputtering method.

  Finally, the metal layer 4a on the interlayer insulating film 14 other than the gate opening 16 is removed by CMP to complete the metal gate electrode 4, and the semiconductor device shown in FIG. 1 is manufactured.

  In the manufacturing method of the semiconductor device according to the present embodiment, the sidewall insulating film 5 in which at least the first insulating film 6 and the second insulating film 7 are sequentially stacked is formed on the side wall of the dummy gate 22. After the upper layer portion is etched to form the trench 15, the first insulating film 6 on the sidewall of the trench 15 is etched using the dummy gate lower layer portion 22 a as a mask. Thereafter, by removing the dummy gate lower layer portion 22a and the dummy gate insulating film 21, a gate opening 16 is formed which has a wider upper portion than the lower portion and exposes the semiconductor substrate 1. By expanding the upper part of the gate opening 16, the embedding property of the metal layer 4a can be improved. As a result, the metal gate electrode 4 can be embedded in the gate opening 16 without generating a void even when a film forming method with poor coverage such as a sputtering method is used.

(Second Embodiment)
A method of manufacturing a semiconductor device according to the second embodiment will be described with reference to FIG.

  In the present embodiment, an example in which an etching stopper film 22b is provided between the dummy gate lower layer portion 22a and the dummy gate upper layer portion 22c will be described. In this case, in the step shown in FIG. 2B in the first embodiment, a polysilicon film is formed on the gate insulating film 3 as the dummy gate lower layer portion 22a by the CVD method and left in the atmosphere or hydrochloric acid. A silicon oxide film having a thickness of 1 to 2 nm is formed as an etching stopper film 22b by a treatment using a hydrogen peroxide cleaning solution, and a polysilicon film is sequentially formed as a dummy gate upper layer portion 22c by a CVD method. Thereafter, the polysilicon film, the silicon oxide film, and the polysilicon film are processed by etching using the mask layer 23 as a mask. As described above, the dummy gate 22 having the laminated structure of the dummy gate lower layer portion 22a made of the polysilicon film, the etching stopper film 22b made of the silicon oxide film, and the dummy gate upper layer portion 22c made of the polysilicon film is formed. In place of the polysilicon film, an amorphous silicon film or an amorphous silicon film containing impurities may be formed. Further, the material may be changed between the dummy gate lower layer portion 22a and the dummy gate upper layer portion 22c. In this case, for example, the dummy gate upper layer portion 22c is formed of silicon germanium. Thereafter, similarly to the first embodiment, the structure shown in FIG. 9A is reached through the steps shown in FIGS.

  Next, as shown in FIG. 9B, the mask layer 23 and the dummy gate upper layer portion 22c exposed from the interlayer insulating film 14 are etched. Etching controllability can be improved by providing the etching stopper film 22b under the dummy gate upper layer portion 22c. Thereafter, the etching stopper film 22b made of silicon oxide is removed using dilute hydrofluoric acid.

  As the subsequent steps, similarly to the first embodiment, the semiconductor device shown in FIG. 1 is manufactured through the steps shown in FIGS.

  In the method of manufacturing the semiconductor device according to the present embodiment, the etching amount can be controlled with high accuracy by providing the etching stopper film 22b under the dummy gate upper layer portion 22c. For this reason, the gate opening 16 having a uniform shape can be formed, and the metal gate electrode 4 having a uniform shape can be formed.

(Third embodiment)
A method for manufacturing a semiconductor device according to the third embodiment will be described with reference to FIG.

  This embodiment is different from the second embodiment in that the material of the dummy gate lower layer portion 22a and the dummy gate upper layer portion 22c is changed and the etching stopper film 22b is not provided. In this case, in the step shown in FIG. 2B described in the first embodiment, a polysilicon film is formed on the gate insulating film 3 as the dummy gate lower layer 22a, and the dummy gate upper layer is formed on the polysilicon film. A silicon germanium film is sequentially formed as the portion 22c. Thereafter, the silicon germanium film and the polysilicon film are processed by etching using the mask layer 24 as a mask. Thus, the dummy gate 22 having a laminated structure of the dummy gate lower layer portion 22a made of the polysilicon film and the dummy gate upper layer portion 22c made of the silicon germanium film is formed. In place of the polysilicon film, an amorphous silicon film or an amorphous silicon film containing impurities may be formed. Thereafter, similarly to the first embodiment, the structure shown in FIG. 10A is reached through the steps shown in FIGS.

  Next, as shown in FIG. 10B, the mask layer 23 and the dummy gate upper layer portion 22c exposed from the interlayer insulating film 14 are etched. By changing the materials of the dummy gate lower layer portion 22a and the dummy gate upper layer portion 22c, the dummy gate upper layer portion 22c can be selectively etched with respect to the dummy gate lower layer portion 22a.

  As the subsequent steps, similarly to the first embodiment, the semiconductor device shown in FIG. 1 is manufactured through the steps shown in FIGS.

  In the semiconductor device manufacturing method according to the present embodiment, the dummy gate upper layer portion 22c can be selectively etched with respect to the dummy gate lower layer portion 22a. Therefore, the etching amount can be controlled with high accuracy. For this reason, the gate opening 16 having a uniform shape can be formed, and the metal gate electrode 4 having a uniform shape can be formed.

(Fourth embodiment)
FIG. 11 is a cross-sectional view of the semiconductor device according to the fourth embodiment. In the present embodiment, a semiconductor device having a raised extension structure and a manufacturing method thereof will be described.

  Two extension layers 31 are formed on the active region of the semiconductor substrate 1 with the channel region interposed therebetween. In the case of an nMOS transistor, the extension layer 31 is an n-type silicon epitaxial layer. In the case of a pMOS transistor, the extension layer 31 is a p-type silicon epitaxial layer.

  Sidewall insulating films 5 are formed so as to sandwich a region longer than the channel region, that is, the channel region of the semiconductor substrate 1 and the end regions of the two extension layers 31. The sidewall insulating film 5 is made of, for example, a silicon nitride film.

  Inside the sidewall insulating film 5, the gate insulating film 3 is formed on the channel region of the semiconductor substrate 1 and on the end portion of the extension layer 31. Further, the metal gate electrode 4 is formed by filling the gate opening 16 defined by the sidewall insulating film 5 and the extension layer 31. The materials of the gate insulating film 3 and the metal gate electrode 4 are the same as in the first embodiment.

  A source / drain layer 32 is formed outside the sidewall insulating film 5 and on the extension layer 31. In the case of an nMOS transistor, the source / drain layer 32 is an n-type silicon epitaxial layer. In the case of a pMOS transistor, the source / drain layer 32 is made of a p-type silicon epitaxial layer.

  A silicide layer 33 is formed on the surface layer portion of the source / drain layer 32. The material of the silicide layer 33 is the same as that of the first embodiment.

  In the fourth embodiment, an example in which the source / drain layer 32 made of an epitaxial growth layer is stacked on the extension layer 31 will be described. However, the source / drain layer 32 is not particularly limited. For example, the source / drain regions 30 may be formed by ion implantation of impurities into the extension layer 31 and the semiconductor substrate 1. In this case, the silicide layer 33 is formed on the surface of the extension layer 31.

  In the semiconductor device according to the present embodiment, the two extension layers 31 are formed on the semiconductor substrate 1 so as to sandwich the channel region, and the end regions of the channel region and the two extension layers 31 are sandwiched. A sidewall insulating film 5 is formed on the extension layer 31. Thereby, the width of the gate opening 16 defined by the sidewall insulating film 5 and the extension layer 31 is wider in the upper part than in the lower part. Since the upper part of the gate opening 16 is widened, the embedding property of the metal gate electrode 4 in the gate opening 16 is improved. As a result, generation of voids in the metal gate electrode 4 can be suppressed, and a semiconductor device including a reliable gate electrode can be realized.

  In addition, since the width of the upper layer portion of the metal gate electrode 4 is larger than the width of the lower layer portion of the metal gate electrode 4, the resistance of the metal gate electrode 4 can be reduced. Therefore, it is possible to realize a semiconductor device including the low-resistance metal gate electrode 4 without gate depletion.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.

  As shown in FIG. 12A, a dummy gate insulating film 21, a dummy gate 22, and a mask layer 23 are formed on the semiconductor substrate 1, and a first sidewall spacer 24 is formed on the sidewall of the dummy gate 22. About these formation methods, it is the same as that of 1st Embodiment. For example, in this embodiment, the mask layer 23 and the first sidewall spacer 24 are formed of a silicon nitride film.

  Next, as shown in FIG. 12B, a silicon layer is selectively epitaxially grown on the semiconductor substrate 1. During this epitaxial growth, an n-type impurity or a p-type impurity is added. As a result, extension layers 31 made of a silicon layer containing impurities are formed on both sides of the dummy gate 22. In the case of an nMOS transistor, an n-type impurity is added, and in the case of a pMOS transistor, a p-type impurity is added.

  Next, as shown in FIG. 13A, the second sidewall spacer 25 is formed on the sidewall of the dummy gate 22, and the sidewall insulating film 5 is formed outside the second sidewall spacer 25. For example, the silicon oxide film is formed on the entire surface by covering the dummy gate 22 by the CVD method, and the silicon oxide film is etched back to form the second sidewall spacer 25 made of the silicon oxide film only on the sidewall of the dummy gate 22. Is done. Thereafter, the dummy gate 22 and the second sidewall spacer 25 are covered to form a silicon nitride film on the entire surface by the CVD method, and the silicon nitride film is etched back to form a silicon nitride film outside the second sidewall spacer 25. Sidewall insulating films 5 are formed. The second side wall spacer 25 corresponds to the side wall spacer of the present invention.

  Next, as shown in FIG. 13B, a silicon layer is selectively epitaxially grown on the extension layer 31 outside the sidewall insulating film 5. Thereafter, an n-type impurity or a p-type impurity is ion-implanted into the silicon layer, whereby the source / drain layer 32 is formed. In the case of an nMOS transistor, n-type impurities are ion-implanted, and in the case of a pMOS transistor, p-type impurities are ion-implanted. An impurity may be added during the epitaxial growth. Alternatively, source / drain regions may be formed by ion implantation of impurities into the semiconductor substrate 1 and the extension layer 31 without epitaxial growth. When ion implantation is performed, annealing for activation is performed thereafter.

  Next, as shown in FIG. 14A, a silicide layer 33 is formed on the surface layer of the source / drain layer 32. In forming the silicide layer 33, first, a metal film is formed on the entire surface so as to cover the source / drain layer 32. As the metal film, nickel, cobalt or platinum is formed. Subsequently, heat treatment is performed to react silicon in the surface layer portion of the source / drain layer 32 with the metal film, thereby forming the silicide layer 33. Finally, the unreacted metal film is removed. Thereby, the silicide layer 33 is formed.

  Next, as shown in FIG. 14B, an interlayer insulating film 14 made of silicon oxide is formed on the entire surface so as to cover the dummy gate 22 by the CVD method until the upper surface of the mask layer 23 is exposed by the CMP method. The interlayer insulating film 14 is removed. Note that the interlayer insulating film 14 may be removed by CMP at this time until the upper surface of the dummy gate 22 is exposed.

  Next, as shown in FIG. 15A, the mask layer 23, the dummy gate 22, the dummy gate insulating film 21, the first sidewall spacer 24, and the second sidewall spacer 25 are removed by etching. Thereby, the gate opening 16 exposing the semiconductor substrate 1 is formed. The width of the upper portion of the gate opening 16 is wider than the width of the lower portion of the gate opening 16 by the thickness of the second sidewall spacer 25. The depth of the gate opening 16 is 50 to 100 nm.

  Next, as shown in FIG. 15B, the gate insulating film 3 is formed on the semiconductor substrate 1 exposed in the gate opening 16. The gate insulating film 3 is formed so as to cover the gate opening 16. As the gate insulating film 3, a high dielectric constant film, for example, a hafnium oxide film is formed. Subsequently, a metal layer 4a that fills the gate opening 16 is formed. As the metal layer 4a, a pure metal material layer, an alloy layer, or a metal compound layer is formed. For example, a tungsten film, a titanium film, a hafnium film, a ruthenium film, or an iridium film is formed by a sputtering method.

  Finally, the metal layer 4a on the interlayer insulating film 14 other than the gate opening 16 is removed by CMP to complete the metal gate electrode 4, and the semiconductor device shown in FIG. 1 is manufactured.

  In the manufacturing method of the semiconductor device according to the present embodiment, the extension layers 31 are formed on both sides of the dummy gate 22, and the second sidewall spacer 25 for improving embeddability is formed on the sidewall of the dummy gate 22 and on the extension layer 31. Form. Thereafter, the sidewall insulating film 5 and the interlayer insulating film 14 are formed, and the dummy gate 22 and the second sidewall spacer 25 are removed, so that the upper portion is wider than the lower portion by the thickness of the second sidewall spacer 25. A gate opening 16 is formed. By expanding the upper part of the gate opening 16, the embedding property of the metal layer 4a can be improved. As a result, the metal gate electrode 4 can be embedded in the gate opening 16 without generating a void even when a film forming method with poor coverage such as a sputtering method is used.

The present invention is not limited to the description of the above embodiment.
For example, in the first to third embodiments, a silicon oxide film may be used as the first insulating film 6 constituting the sidewall insulating film 5, and a silicon nitride film may be used as the second insulating film 7. By forming the first insulating film 6 disposed on the metal gate electrode 4 and the source / drain portion 12 side with a silicon oxide film having a low dielectric constant, the fringe capacitance between the metal gate electrode 4 and the source / drain portion 12 is reduced. can do.
In addition, various modifications can be made without departing from the scope of the present invention.

1 is a cross-sectional view of a semiconductor device according to a first embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 2nd Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing of the semiconductor device which concerns on 4th Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 4th Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 4th Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 4th Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 4th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation insulating film, 3 ... Gate insulating film, 4 ... Metal gate electrode, 4a ... Metal layer, 5 ... Side wall insulating film, 6 ... 1st insulating film, 7 ... 2nd insulating film, DESCRIPTION OF SYMBOLS 11 ... Extension part, 12 ... Source / drain part, 13 ... Silicide layer, 14 ... Interlayer insulating film, 15 ... Groove, 16 ... Gate opening part, 21 ... Dummy gate insulating film, 22 ... Dummy gate, 22a ... Dummy gate lower layer , 22b... Etching stopper film, 22c... Dummy gate upper layer part, 23... Mask layer, 24... First side wall spacer, 25. Drain layer 33 ... Silicide layer

Claims (9)

A gate insulating film formed on the substrate;
A metal gate electrode including a metal formed on the gate insulating film;
A sidewall insulating film formed on a side wall of the metal gate electrode,
The sidewall insulating film is
A first insulating film formed on the side wall of the lower layer of the metal gate electrode;
A second insulating film formed outside the first insulating film and over the entire sidewall of the metal gate electrode;
The width of the upper layer part of the metal gate electrode is wider than the width of the lower layer part of the metal gate electrode. Two extension layers formed on the substrate so as to sandwich the channel region of the substrate;
A sidewall insulating film formed on the extension layer so as to sandwich a channel region and the ends of the two extension layers;
A gate insulating film formed on a channel region of the substrate and an end of the extension layer;
A metal gate electrode formed by embedding a gate opening defined by the sidewall insulating film and the extension layer;
The width of the upper layer part of the metal gate electrode is wider than the width of the lower layer part of the metal gate electrode. Forming a dummy gate on the substrate;
Forming a sidewall insulation film in which at least a first insulation film and a second insulation film are sequentially laminated on the sidewall of the dummy gate;
Forming an interlayer insulating film that embeds the sidewall insulating film and exposes the upper surface of the dummy gate;
Etching the upper layer of the dummy gate to form a groove;
Removing the first insulating film on the side wall of the trench by etching using the lower layer of the dummy gate as a mask;
Removing the lower layer portion of the dummy gate to expose the substrate and forming a gate opening having a wider upper portion than the lower portion;
Forming a gate insulating film on the substrate exposed in the gate opening;
Forming a metal gate electrode that embeds the gate opening. The method of manufacturing a semiconductor device according to claim 3, wherein in the step of forming the dummy gate, the dummy gate in which the lower layer portion, the etching stopper film, and the upper layer portion are stacked is formed. The method of manufacturing a semiconductor device according to claim 3, wherein in the step of forming the dummy gate, the dummy gate is formed of different materials in the lower layer portion and the upper layer portion. 4. The semiconductor device manufacturing method according to claim 3, wherein in the step of forming the dummy gate, the dummy gate is formed by laminating the lower layer portion, an etching stopper film, and an upper layer portion made of a material different from the lower layer portion. Method. After the step of forming the dummy gate and before the step of forming the sidewall insulating film, the method further includes the step of forming extension portions on the substrate on both sides of the dummy gate,
4. The method according to claim 3, further comprising a step of forming source / drain portions on the substrate on both sides of the sidewall insulating film after the step of forming the sidewall insulating film and before the step of forming the interlayer insulating film. Semiconductor device manufacturing method. Forming a dummy gate on the substrate;
Epitaxially growing an extension layer on the substrate on both sides of the dummy gate;
Forming a sidewall spacer on the sidewall of the dummy gate;
Forming a sidewall insulating film on the side wall of the dummy gate via the side wall spacer;
Forming an interlayer insulating film that embeds the sidewall insulating film and exposes the upper surface of the dummy gate;
Removing the dummy gate and the sidewall spacer to expose the substrate to form a gate opening having a wider upper portion than the lower portion;
Forming a gate insulating film on the substrate and the end of the extension layer exposed in the gate opening;
Forming a metal gate electrode that fills the gate opening. The method for manufacturing a semiconductor device according to claim 8, further comprising a step of forming a source / drain portion after the step of forming the sidewall insulating film and before the step of forming the interlayer insulating film.

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