JP2000082814A - MIS transistor and method of manufacturing the same - Google Patents

Abstract

(57) [Problem] To reduce the resistance of an S / D diffusion layer and reduce the gate parasitic capacitance. An MIS transistor includes a semiconductor substrate (1).
Source / drain region (S / D diffusion layer) 2 formed in
Is located closer to the gate electrode 6 than the channel formation surface 7 of the semiconductor substrate 1, and the upper surface of the source / drain region 2 is located between the gate insulating film 5 and the gate electrode 6 provided above the channel formation surface 7. It is located closer to the channel forming surface 7 than the boundary surface. In this transistor, a trench 4 is selectively formed on the surface of a semiconductor substrate 1, and impurity diffusion layers 2a and 2b serving as source / drain regions 2 are formed using polysilicon 10 deposited in the trench 4 as a mask. A gate insulating film 5 made of a high dielectric film and a gate electrode 6 may be laminated, or the polysilicon 10 may be selectively formed first and the impurity diffusion layers 2a and 2b may be raised by using this as a mask. After that, the gate insulating film and the gate electrode may be stacked.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MIS transistor and a method of manufacturing the same, and more particularly to a MIS transistor having a large driving current and a small parasitic capacitance, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Metal / insulating film / semiconductor (Metal Insulato)
With the increasing demand for miniaturization of transistors having a MIS-structure, the current MIS
The miniaturization of the transistor having the die structure is steadily progressing.
The miniaturization of the MIS transistor is performed by using a technique called scaling law that forms the source / drain region in proportion to the gate length when considered broadly.
Specifically, when the gate length is reduced, the depth of the junction of an impurity diffusion region serving as a source and a drain, that is, a diffusion layer, is reduced in accordance with the reduction of the gate length.

However, in a fine transistor having a gate length of less than 0.2 μm, the diffusion depth (Xj) becomes too shallow, the resistance at the gate increases, and the parasitic resistance of the entire transistor increases. There is a problem that a substantial driving current is reduced. Therefore, in order to reduce the parasitic resistance, it may be conceivable to reduce the depth of the junction when the source and drain to be introduced are made into metal silicide (silicidation). There is a problem that the junction is not retained in the diffusion layer but penetrates to the substrate side, which causes a junction leak, because it is hard to make the surface shallow.

[0004] The problem that the resistance increases or silicidation becomes difficult when the junction is shallow has been solved by techniques called elevated source drain, concave transistor, and reset channel transistor. Have a structure in which the source and drain surfaces are formed higher than the channel surface of the transistor (eg, SMSze Ph
ysics of Semiconductor Devices second edition, 198
1, pp490). FIG. 14 shows an MIS transistor having such a concave MOS structure, which is provided on a semiconductor substrate 1, a source / drain region 2, a channel forming surface 7 located therebetween, and an upper portion of the channel forming surface 7. The device includes an SiO ₂ film 51 and a gate electrode 6 provided to face the channel forming surface 7 with the SiO ₂ film 51 interposed therebetween.

In FIG. 14, a source / drain region 2
Includes a first impurity diffusion region 2a belonging to the semiconductor substrate 1 more than the channel formation surface 7 and a second impurity diffusion region 2b stacked outside (upper in the figure) than the channel formation surface 7 The structure in which the second impurity diffusion region 2b surrounds the gate electrode 6 with the SiO ₂ film 5 interposed therebetween is considered to be a configuration in which a groove is formed in the source / drain region 2. It can also be considered that the diffusion region 2b is raised (elevated).

[0006]

However, FIG.
In the conventional MIS transistor having the structure shown in FIG. 1, the gate electrode 6 is surrounded by the source / drain diffusion layer 2 via the SiO ₂ (insulating) film 51, so that the gate-drain capacitance and the source There is a problem that the operation speed of the transistor is significantly deteriorated due to an increase in the drain-to-drain capacitance.

As described above, the conventional MIS transistor has a problem that the reduction of the source / drain diffusion layer resistance and the reduction of the gate parasitic capacitance cannot be simultaneously solved.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an M transistor capable of simultaneously reducing the source / drain diffusion layer resistance and the gate parasitic capacitance.
An object of the present invention is to provide an IS transistor and a method for manufacturing the same.

[0009]

To achieve the above object, a MIS transistor according to a first basic structure of the present invention comprises a semiconductor substrate, a source / drain region formed on the substrate, and a source / drain region formed on the semiconductor substrate. A gate electrode provided above the channel region between the regions, wherein the upper surfaces of the source and drain formed on the semiconductor substrate are located closer to the gate electrode than the channel formation surface of the semiconductor substrate, and The upper surfaces of the source and the drain are located closer to the channel forming surface than a boundary surface between the gate insulating film provided on the channel forming surface and the gate electrode, and the dielectric constant of the gate insulating film is a dielectric constant of silicon oxide. It is characterized in that it is formed to be higher than the ratio.

In the MIS transistor according to the first basic structure, a groove is formed on an upper surface of the semiconductor substrate, a bottom surface of the groove is used as the channel forming surface, and a protective film is formed on an opening of the groove. The gate insulating film is formed through the gate insulating film, and a gate electrode is positioned on the gate insulating film. The source / drain is positioned on both sides of the channel forming surface, and the upper surface of the source / drain region, the channel forming surface And the boundary surface may have a predetermined positional relationship.

Further, in the MIS transistor according to the first basic configuration, the upper surface of the source / drain in which a portion of the semiconductor substrate sandwiching the channel forming surface is located closer to the gate electrode than the channel forming surface. The upper surface of the source / drain may be located closer to the channel forming surface than the boundary between the gate insulating film formed on the channel forming surface via a protective film and the gate electrode.

Further, in the MIS transistor according to the first basic configuration, the upper surface of the source / drain region provided with the channel forming surface interposed therebetween is raised above the channel forming surface to be closer to the gate electrode. And the upper surface of the source / drain region is raised, and has a substantially flat surface at a level positioned on the side of the gate electrode, and an inclined surface inclined from the level of the flat surface to the level of the channel forming surface. May be provided.

Further, in the above structure, the shape of the gate electrode surrounded by the gate insulating film provided above the channel forming surface has a T-shaped cross section in which the lower side is tapered through the step. May be.

In the MIS transistor according to the first basic configuration, the shape of a gate electrode surrounded by a gate insulating film provided above the channel forming surface is tapered on the lower side via a step portion. It may have a T-shaped cross section.

Further, in the above structure, the gate insulating film may be formed of a metal oxide film.

In the above structure, the gate insulating film may be made of at least one of a titanium oxide film, an aluminum oxide film, and a tantalum oxide film.

In the above structure, the dielectric constant of the gate oxide film may be set higher than the dielectric constant of the aluminum oxide film.

Further, M according to the second basic configuration of the present invention
An IS type transistor comprising: a semiconductor substrate; a source / drain region formed on the substrate; and a gate electrode provided above a channel region between the source / drain region. The upper surface of the source / drain region provided on both sides thereof is positioned higher on the gate electrode side than the channel forming surface, and the upper surface of the source / drain region is raised on the gate electrode side. A substantially flat surface at a level located therefrom, and an inclined surface inclined from the level of the flat surface to the level of the channel forming surface, and is surrounded by a gate insulating film provided above the channel forming surface. It is characterized in that the shape of the gate electrode has a T-shaped cross section with the lower side tapering through the step.

Further, the MI according to the third basic configuration of the present invention.
A method of manufacturing an S-type transistor includes a method of manufacturing an MIS transistor including a semiconductor substrate, a source / drain region formed on the substrate, and a gate electrode provided above a channel region between the source / drain region. A method of selectively forming an oxide film on the semiconductor substrate, a step of performing etching by using the selectively formed oxide film as a mask, and a step of forming a polycrystalline semiconductor in the groove. After laminating the layers and polishing the upper surfaces of the oxide film and the polycrystalline semiconductor film, removing the oxide film, and diffusing impurities to the surface of the semiconductor substrate using the polycrystalline semiconductor film as a mask Forming a groove-shaped impurity diffusion region including a bottom side of the groove; and forming a gate insulating film made of a high dielectric film in a groove portion of the groove-shaped impurity diffusion region. A step from the upper surface of the portion other than the groove portion of the band formed by positioned on a side away from the semiconductor substrate, is characterized in that it comprises a step of forming a gate electrode on the upper surface of the gate insulating film.

Further, according to a fourth basic configuration of the present invention, M
A method of manufacturing an IS type transistor includes an MIS transistor including a semiconductor substrate, a source / drain region formed on the substrate, and a gate electrode provided above a channel region between the source / drain region. A method of manufacturing, comprising: selectively forming a polycrystalline semiconductor layer on the semiconductor substrate; and diffusing impurities into a surface of the semiconductor substrate using the selectively formed polycrystalline semiconductor layer as a mask. Forming an impurity diffusion region including an impurity diffusion region raised above the channel forming surface to be formed on the masked semiconductor substrate surface; and forming an oxide film on the surface side of the raised impurity diffusion region. Forming and polishing the oxide film surface using the polycrystalline semiconductor layer as a stopper, and then removing the polycrystalline semiconductor layer; and Forming a gate insulating film made of a high dielectric film in a region surrounded by the pure diffusion layer and the oxide film to a height such that an upper surface thereof is farther from the substrate than a boundary surface between the impurity diffusion region and the oxide film; And forming a gate electrode on the upper surface of the gate insulating film.

Further, the MI according to the fifth basic configuration of the present invention.
A method for manufacturing an S-type transistor includes an MIS transistor including a semiconductor substrate, a source / drain region formed on the substrate, and a gate electrode provided above a channel region between the source / drain region. A method of manufacturing, wherein a dummy gate insulating film and a dummy gate electrode including a second semiconductor layer are formed by a method including at least lithography on the channel forming surface surrounded by a selectively formed semiconductor layer. And selectively forming a semiconductor layer serving as a source / drain region on the semiconductor substrate with a region serving as a channel formation surface interposed therebetween such that an inclined surface is formed between an upper surface of the semiconductor layer and the channel formation surface. And forming an impurity diffusion region by diffusing impurities into the surface of the semiconductor substrate using the second semiconductor layer as a mask. A step of removing a dummy gate electrode formed on a portion to be the channel forming surface sandwiched between the impurity diffusion regions by etching; and forming a high dielectric film on the exposed channel forming surface. Depositing an insulating film over the entire surface to form a gate insulating film in a cross-sectional shape having a groove-shaped space on the center side; Forming a gate electrode having a T-shaped cross section by depositing a gate electrode on the upper surface of the substrate.

As described above, in the MIS transistor according to the present invention, the actual thickness of the gate insulating film using the high dielectric film and the actual thickness of the gate insulating film using the trench or the source / drain elevated structure are expressed by the average dielectric constant. By providing the lower surface of the gate electrode at a position higher than the semiconductor substrate surface by an amount larger than the actual film thickness of the gate electrode and the source-drain insulating film having a capacitor equivalent film thickness equal to the capacitor equivalent film thickness obtained by dividing, It is possible to simultaneously reduce the drain diffusion layer resistance and the gate parasitic capacitance.

Further, in the MIS transistor according to the present invention, in the MOS transistor, the average dielectric constant of the first insulating film material used as the gate insulating film is a second insulating film for insulating the upper surface of the trench from the gate material. May be configured to be higher than the average dielectric constant.

Further, in such a MOS transistor, the first insulating film serving as the gate insulating film is formed of Si
It may be constituted by a laminated structure of an insulating film having a higher dielectric constant than the O2 film and a buffer insulating film for protecting the insulating film.

In the MIS transistor, the actual thickness of the gate insulating film is larger than the actual thickness of the second insulating film having a capacitor equivalent thickness which is equal to the capacitor equivalent thickness obtained by dividing the actual film thickness by the average dielectric constant. The lower surface of the gate electrode may be located at a position higher than the surface of the semiconductor substrate by an amount. As described above, according to the present invention, it is possible to simultaneously reduce the source / drain diffusion layer resistance and the gate parasitic capacitance.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a MIS transistor according to the present invention and a method for manufacturing the same will be described below in detail with reference to the accompanying drawings.

FIG. 1 shows an MI according to a first embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a schematic configuration of an S-type transistor. In the drawings, hatching representing a cross section is omitted for clarity of display. Components denoted by the same reference numerals as those in FIG. 14 indicate the same or corresponding components as those of the conventional MIS transistor.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate, and an impurity region 2 used as a source / drain is provided on a front surface side of the semiconductor substrate 1 via a channel region 7. When operating as a transistor, one of the impurity regions 2 is used as a drain electrode and the other is used as a source electrode, and a recess or a groove 4 is formed in a portion over the channel forming surface 7 between the two. ing. A high dielectric gate insulating film 5 is provided in the trench 4 via the protective film 3, and a gate electrode 6 is provided on the upper side of the high dielectric gate insulating film 5. The insulating region 13 is insulated between the impurity region 2 used as a source and a drain and the gate electrode 6. The high dielectric gate insulating film 5 has a dielectric constant higher than the relative dielectric constant 3.9 of the SiO ₂ film 5 in the conventional MIS transistor shown in FIG.

What is important in the above structure is that the level La on the upper surface of the source / drain between the second impurity diffusion region 2b and the insulating film 13 is more distant from the semiconductor substrate 1 than the level Lb on the channel forming surface 7. And is located closer to the semiconductor substrate 1 than the level Lc on the lower surface of the gate electrode 6.

As in the case of the conventional MIS type transistor shown in FIG. 14, the impurity region 2 is a first impurity diffusion region 2a which belongs to the semiconductor substrate 1 rather than the channel forming surface 7.
Outside the channel forming surface 7 (upper side in the figure)
And a second impurity diffusion region 2b laminated on the second impurity diffusion region. The protective film 3 is formed of, for example, a SiN or oxynitride film for protecting the gate insulating film 5, and a first protective film located between the channel forming surface 7 and the gate insulating film 5. 3a and a second protective film 3b located between the second impurity diffusion region 2b.

In the above configuration, the MIS transistor according to the first embodiment of the present invention is the same as the conventional MIS transistor shown in FIG.
Similar to the S-type transistor, the impurity diffusion region 2 used as a source / drain is located on the opposite side of the semiconductor substrate 1 by the thickness of the second impurity diffusion region 2b from the channel forming surface 7 where the channel through which current flows is formed. Is formed. Therefore, compared with the case where the source / drain region is formed only in the first impurity diffusion region 2a below the channel formation surface 7, the resistance of the diffusion layer can be reduced,
Also, when forming silicide with nickel (Ni), titanium (Ti), or the like, it is possible to avoid the occurrence of junction leakage caused by the progress of silicidation to the junction surface.

Further, by providing the lower surface 8 of the gate electrode 6 at a position higher than the upper surface of the impurity diffusion region 2 used as the source / drain, that is, on the side farther from the semiconductor substrate 1, the performance of the gate electrode is reduced. The capacitance between the source and the drain can be greatly reduced as compared with the conventional concave MOS shown in FIG.

Further, the distance between the gate electrode 6 and the source / drain electrode 2b can be made larger than in the conventional example, and the electric field can be kept small. Therefore, leakage current between them can be reduced, and dielectric breakdown can be prevented. This feature applies to all embodiments described below.

Although not shown, the gate insulating film between the gate electrode and the channel forming surface is made of SiO ₂ in a conventional MIS transistor in which the channel forming surface and the upper surfaces of the source / drain regions are flush with _{each other.} If the lower surface 8 of the gate electrode 6 is formed of this Si
O increases with providing the surface 7 than the thickness of ₂ film, an insulating film 13 for insulating the gate electrode and the source and drain SiO ₂
By using a film, the parasitic capacitance can be reduced as compared with a conventional planar MOS transistor.

For example, in the prior art, when the gate length is 0.1 μm, the thickness of the gate oxide film is scaled to about 3 nm.
Designing devices with a protective film O5 and 1nm of SiN (dielectric constant 7.5), in order to equalize the surface charge amount Qs of the transistor, and the keeping equivalent thickness 3nm of SiO _2, the first protective layer 3a Has an actual SiN film thickness of 1 nm,
The equivalent SiO ₂ film thickness is “1 nm × 3.9 / 7.5 = 0.5
2 "nm, and the high dielectric gate insulating film 5 (Ta2O
The SiO2 equivalent film thickness of 5) is “3 nm−0.52 nm =
2.48 nm ”, and the actual film thickness is“ 2.48 nm × 25 ”.
/3.9=15.9 nm ".

That is, the depth of the groove of the impurity diffusion region 2 serving as the source / drain is set to 15.9 nm (the gate insulating film 5).
+1 nm (for the protective film 3 a) = 16.9 nm ”, the lower surface 8 of the gate electrode 6 has the same height as the source / drain surfaces, and 13.9 nm for 3 nm oxidation on the conventional scaling trend. The parasitic capacitance is almost the same as that of a MOS transistor using a film. Here, according to the conventional scaling, the depth of the diffusion layer of the transistor is 0.1
Even a micron transistor is about 40 nm,
Thus, the parasitic resistance can be reduced by increasing the thickness of the diffusion layer to 13.9 nm, that is, 35%.

Here, the relative dielectric constant of SiO ₂ is ε,
The thickness of the _two films is TSiO ₂ , the relative dielectric constant of the high dielectric gate insulating film 5 is ε ₅ , the actual thickness is T ₅ , and the relative dielectric constant of the protective film 3 is ε.
_3, when the actual thickness and _{T 3,} SiO ₂ of TSIO ₂ thickness
The film thickness giving a parallel plate capacity equivalent to the film is given by the following equation: TSiO ₂ / εSiO ₂ = T ₃ / ε ₂ + T ₅ /
It may satisfy the ε _5. When a 1-nm-thick SiN film is used for the protective film and the relative dielectric constants of SiO ₂ and SiN are 3.9 and 7.5, respectively, T5 = ε ₅ (TSiO ₂ /3.9-1
/7.5) (nm), which is the thickness TSiO ₂ on the conventional scaling trend, and the redness of the trench, which is equivalent to the parasitic capacitance, is that the material of the insulating film between the gate, source and drain is Si.
Assuming O ₂ or equivalent dielectric constant, Dconcave = ε ₅ (TSiO ₂ /3.9-1/7.5)
It is given by -TSiO _2. The shallower the trench, the smaller the parasitic capacitance.

In the case of using a titanium oxide film TiO2 film having a relative dielectric constant of about 80 and being thermally stable and requiring no protective film from that point, a similar calculation after removing the protective film portion yields Dconcave = If ε ₅ × TSiO ₂ /3.9-TSiO ₂ and the groove depth is 58.5 nm, the conventional 3 nm
Parasitic capacitance comparable to that of a MOS transistor using an oxide film, and reducing the parasitic resistance by making the diffusion layer 150% thicker than in the case of using a diffusion layer having a depth of 58.5 nm, that is, the conventional 40 nm. Can be.

Next, a method of manufacturing the MIS transistor according to the first embodiment of the present invention will be described with reference to FIGS. 2 (a) to 2 (e). First, as shown in FIG. 2A, SiO _{2 is formed} on a silicon substrate 1 as a semiconductor substrate.
The film 9 is deposited and etched by lithography. Next, the groove 4 is formed by reactive ion etching (RIE-Reactive Ion Etching-) using the SiO ₂ film 9 as a mask (FIG. 2B).

Next, as shown in FIG. ₂ (c), SiO 2
After laminating a thin sacrificial oxide film 11 on the surface of the film 9 and the groove 4 of the silicon substrate 1, a polysilicon 10 is deposited, and a chemical mechanical polishing method (−CMP-Chemical Mechanical Pol) is performed.
ishing) or SiO ₂ using an etch-back technique or the like.
Flatten to the upper surface of the film 9. At this time, the thin sacrificial oxide film 11 is stacked to separate the polysilicon 10 and the silicon substrate 1.

Next, as shown in FIG. 2D, after the silicon oxide (SiO ₂ ) film 9 is removed, the source is formed by ion implantation or solid phase diffusion using the polysilicon 10 as a mask. The drain region 2 is formed. next,
The polysilicon 10 and the sacrificial oxide film 11 are removed by, for example, chemical dry etching (CDE-Chemical Dry Etching-). Thereafter, as shown in FIG. 2E, a SiN film 3 as a protective film is formed by deposition or thermal nitridation. Next, a high dielectric film 5 is formed by a sputtering technique or the like, and a gate electrode 6 is deposited. Finally, silicon (S
i) By forming the oxide film 12, a semiconductor device having the same structure as the MIS transistor shown in FIG. 1 is manufactured.

Next, a method and structure for manufacturing a MIS transistor according to the second embodiment of the present invention will be described with reference to FIGS. 3 (a) to 3 (e). First, a method for manufacturing a MIS transistor will be described with reference to FIGS. After a dummy polysilicon 10 is formed on the semiconductor substrate 1 shown in FIG. 3A via a sacrificial oxide film 11 and patterned, and further oxidized to wrap the dummy polysilicon 10 with an oxide film, FIG. As shown in (), the source / drain region 2 is formed by ion implantation or the like.

Next, after the silicon is elevated by the selective epitaxial growth technique, an impurity is again implanted and diffused into the raised portion by additional ion implantation. In the method of manufacturing the MIS transistor according to the first embodiment, the trench 4 is formed first, and the impurity is implanted and diffused from above into the trench.
However, in the method of manufacturing the MIS transistor according to the second embodiment, the depth of the source / drain region 2 below the channel formation surface 7 is smaller than the depth of the channel formation surface 7. Since it is determined by the degree of impurity implantation, there is an effect that control is easy.

Next, first, a silicon (Si) oxide film 12 is deposited on the source / drain region 2 with the polysilicon 10 left, and the silicon oxide film 12 is formed by the CMP technique using the polysilicon 10 as a stopper. 1
It is flattened to the upper surface of 0. Here, as shown in FIG. 3C, the polysilicon 10 and the sacrificial oxide film 11 are peeled off by CDE or the like, and silicon nitride (SiN) is formed from the side surfaces of the silicon oxide film 12 and the source / drain region to the upper surface of the channel forming surface 7. A protective film 3 is deposited.

Next, as shown in FIG. 3D, a high dielectric gate insulating film 5 is deposited to a position higher than the upper surface of the source / drain region 2 by sputtering, CVD or the like. When adopting such a process, if the thickness of the high dielectric gate insulating film 5 is smaller than the depth of the groove, the insulation between the gate electrode and the source / drain must be maintained by the protective film 3. As compared with the case where the high dielectric gate insulating film 5 is provided higher than the groove 4 as in the present embodiment, the thickness of the protective film 3 must be increased.

Next, as shown in FIG. 3E, a gate electrode 6 is formed on the high dielectric gate insulating film 5 by sputtering and CVD.
The silicon oxide film 12 is deposited to substantially the same height as that of the silicon oxide film 12 by the method described above. Further, as described above, if the thickness of the high dielectric gate insulating film 5 is smaller than the depth of the groove, the distance between the gate electrode 6 and the upper surface of the source / drain region 2 is separated by the protective film 3. In such a state, Dconcave = ε ₅ (TSiO ₂ /3.9-1/7.5).
−TSiO ₂ was satisfied. Therefore, it is desirable to make the groove portion shallower in order to improve the breakdown voltage of the transistor. Alternatively, it is also desirable to increase the thickness of the protective film 3 in the upper part of the groove than in the lower part in order to improve the breakdown voltage. For this purpose, CDE or the like is performed in the step shown in FIG. 3D so that the space between the high-dielectric gate insulating film 5 and the source / drain region 2 is slightly etched and filled back.

According to the method of manufacturing the MIS transistor according to the second embodiment as described above, the source / drain region 2 is formed after forming the trench 4 using the SiO ₂ film as a mask. Through a step different from the manufacturing method, a transistor having substantially the same configuration can be obtained. However, whether the groove 4 is to be formed on the upper surface of the substrate 1 or the source / drain region 2 is to be further raised from the level of the channel forming surface 7 by forming the source / drain region 2 in the substrate 1 There is only.

The MIS according to the first and second embodiments
In each of the type transistors, the protective film 3 is formed between the high dielectric gate insulating film 5 and the source / drain region 2, but the material of the high dielectric gate insulating film 5 or the lowering of the process is adjusted. By doing so, the protective film 3 may not be necessary. FIG. 4 shows an MIS transistor according to the third embodiment in which the protective film 3 is not provided. In FIG. 4, a protective film (the protective film 3 in FIG. 1) is provided between the channel forming surface 7 of the silicon substrate 1 as a semiconductor substrate and the high dielectric gate insulating film 5.
a) is not provided, and the side wall of the gate insulating film 5 and the second
Is provided only between the impurity diffusion region 2b and the protective film 3b.

Next, a method of manufacturing the MIS transistor according to the fourth embodiment of the present invention will be described with reference to FIGS. 5 (a) to 5 (e). 5 (a) to 5
The steps up to (c) are basically formed in substantially the same manner as the method of manufacturing the MIS transistor according to the first or second embodiment. Next, the sacrificial oxide film 11 and the polysilicon 10 shown in FIG. 5B are separated by CDE or the like, and silicon nitride (SiN) is formed from the side surfaces of the silicon oxide film 12 and the source / drain region 2 to the upper surface of the channel formation surface 7. 3) A protective film 3 is deposited, and a high dielectric gate insulating film 5 is deposited by CVD or sputtering.

Next, as shown in FIG. 5C, the high dielectric gate insulating film 5 deposited by CVD or sputtering or the like is flattened to the upper surface of the oxide film 12 by using the CMP technique. In the method of manufacturing the MIS transistor according to the third embodiment, the thickness of the high dielectric gate insulating film 5 is determined by the thickness of the silicon oxide film 12 and the depth of the groove 4, so that the gate insulating film 5 An excellent effect that the film thickness can be easily controlled is exhibited.

However, in the case of the method of manufacturing the MIS transistor according to the fourth embodiment, since the gate electrode 6 is formed by performing lithography again,
It is difficult to make the gate electrode 6 self-aligned with the groove 4. For this reason, as shown in FIG. 5E, the groove 4 is formed to be larger than the opening area. Therefore, the parasitic capacitance of the gate electrode 6 is slightly increased. However, since the thickness of the silicon oxide film 12 is sufficiently large and the dielectric constant of the silicon oxide film 12 is small, there is no significant influence. .

FIG. 6 shows a cross section of the MIS transistor according to the fourth embodiment manufactured by the manufacturing method shown in FIGS. 5A to 5E. 6, the MIS transistor includes a silicon substrate 1 as a semiconductor substrate, a first impurity diffusion region 2a located closer to the substrate 1 than the channel forming surface 7, and a gate electrode 6 closer to the channel forming surface 7. Second impurity diffusion region 2
b containing source / drain region 2 and silicon oxide film 12
And silicon oxide film 12 and second impurity diffusion region 2
b, a protective film 3 provided on the inner wall of the groove 4 formed in the groove b, a high dielectric gate insulating film 5 formed in the groove 4 through the protective film 3, and a protective film on the gate insulating film 5. And a gate electrode 6 formed to have an area larger than a range surrounded by the gate electrode 3.

In the MIS transistors according to the first to third embodiments described above, the width of the gate electrode
And the MIS according to the fourth embodiment.
Although the type transistor is described as being formed so that the gate electrode 6 is wider than the gate insulating film 5 due to the difficulty of self-alignment, the present invention is not limited to this, and FIG. As in the fifth embodiment shown, it is needless to say that the present invention can be applied to a transistor in which a side wall is provided on a gate electrode 6 in an LDD (Lightly Doped Drain) structure, for example.

In FIG. 7 showing the MIS transistor according to the fifth embodiment, reference numeral 1 denotes a silicon substrate as a semiconductor substrate, 7 denotes a channel formation surface, 2 denotes a first impurity diffusion region 2a and a second impurity diffusion region. Source / drain region including 2b, 3 a protective film, 5 a high dielectric gate insulating film, 6
Is a gate electrode, and 8 is a side wall of silicon dioxide (SiO ₂ ) provided around the gate electrode 6.

FIGS. 8A to 8E are process diagrams showing a method for manufacturing a MIS transistor according to the fifth embodiment. As shown in FIGS. 8A and 8B, a SiN film 3a serving as a gate insulating film, a high dielectric film 5 made of, for example, Ta ₂ O ₅ , and a TiN film serving as a gate electrode are formed on the semiconductor substrate 1. And polysilicon 6 are sequentially deposited, and a portion to be a gate electrode is formed from the polysilicon 6 by etching as shown in FIG. Next, as shown in FIG. 8D, a sidewall 8 of SiO ₂ is formed around the gate electrode 6 by CVD or the like, and a gate insulating film 5 is formed by CDE or the like using the gate electrode 6 and the sidewall 8 as a mask. .

Finally, as shown in FIG. 8 (e), the gate electrode 6 and the stacked structure of the side wall 8 and the gate insulating film 5 made of polysilicon are etched using a mask, and then the side wall insulating film 3b is formed. Then, after raising the source / drain to form the impurity diffusion region 2b, the source / drain region 2 is formed by ion implantation, solid phase diffusion, or the like. As in the first to fourth embodiments, the source / drain region 2 includes a first impurity diffusion region 2 a formed so as to be located on the inner side of the substrate 1 with respect to the channel formation surface 7, and a channel formation surface 7. The present invention has a gist of a second impurity diffusion region 2b which is closer to the gate electrode 6 side and whose upper surface is lower than the lower surface of the gate electrode 6.

The MIS transistor according to the fifth embodiment formed by the steps shown in FIGS. 8A to 8E has a structure as shown in FIG. 7 and has a high dielectric gate insulating film. 5, at least the lower surface side and the side wall side are surrounded by the protective film 3, and the lower side of the gate insulating film 5 and the substrate 1
A first protective film 3a between the surface and the channel forming surface 7;
A second protective film 3b is provided between the second impurity diffusion region 2b and the gate insulating film 5.

The present invention is not limited to the above-described first to fifth embodiments, but includes a sixth embodiment having the configuration shown in FIG.
The present invention can be extended to the transistor according to the embodiment. In FIG. 9, some of the above are provided with the p + semiconductor substrate 1, the channel forming surface 7, the source region 2 </ b> A, the drain region 2 </ b> B, the high dielectric gate insulating film 5, and the gate electrode 6. Embodiment, particularly MI of the fifth embodiment
The configuration is substantially the same as that of the S-type transistor.

In the transistor according to the sixth embodiment shown in FIG. 9, a low-resistance contact 1 is provided in each electrode region.
5 through the respective terminals, ie gate terminals 16,
A source terminal 17 and a drain terminal 18 are provided. Further, a protective film 3 a is provided between the channel forming surface 7 and the gate insulating film 5, and a side wall 8 surrounding the entire gate electrode 6 low-resistance contact 15 and gate terminal 16.
Is also provided with a protective film 3b.

The gate insulating film 5 has 0x of 1.5 nm.
The low resistance contact 15 has a resistance value of “Rcontact <10 ⁻⁸ Ωcm ² ”, and the channel forming surface 7 has a resistance value of “Rpp15 nm, dRp”.
〜7 nm ”is a very shallow channel (retrograde channel). Further, the source region 2A and the drain region 2B are formed so as to be the second impurity diffusion regions 2b having a low resistance of “Xj <10 nm and R <16Ωμm” and being extremely elevated.

Also in the transistor according to the sixth embodiment having such a structure, the upper surface of the source / drain region is located closer to the gate electrode than the channel formation surface, and
This satisfies the gist of the present invention that it is located on the substrate side with respect to the bottom surface of the gate electrode, and is one of preferred embodiments of the MIS transistor according to the present invention.

Next, a semiconductor device according to a seventh embodiment of the present invention will be described with reference to FIGS. 10 to 13E. First, FIG. 10 shows a cross-sectional structure of a semiconductor device according to the seventh embodiment of the present invention.

In FIG. 10, a gate insulating film 113 made of, for example, TiO ₂ or alumina, or a tantalum oxide film, barium titanate, or lead zirconium titanate is formed on a semiconductor layer 105 made of, for example, p-type Si. For example, a gate electrode 11 made of, for example, polySi, amorphousSi, TiN, W, Pt, RuO ₂ , IrO ₂
4 are formed. Here, assuming that the thickness of the portion of the gate insulating film 113 in contact with the semiconductor layer 105 is t (nm) and the relative permittivity is ε, the relationship of t <1.3ε is satisfied.

In the region 105 on both sides of the gate electrode, for example, P, Sb, or As is grown by ion implantation or solid phase diffusion, and the conductivity of the semiconductor layer 105 is opposite to that of the semiconductor layer 105. Are formed to form an n-type MISFET. Further, the source and drain diffusion layers 110
On the top of which, for example, P, Sb or As is added,
Semiconductor region 104 made of Si, SiGe, SiGeC
Are formed. The semiconductor region 104 is formed above the interface between the gate insulating film 113 and the semiconductor layer 105 in the stacking direction, and has a so-called elevated source / drain structure.

Further, an insulating film 109 made of, for example, a silicon nitride film is formed on a side wall of the gate insulating film 113 where the gate electrode 114 is not formed. Further, between the insulating film 109 and the conductive region 104, an insulating film 108 made of, for example, a silicon oxide film is formed. Further, a conductive layer 115 made of, for example, cobalt silicide, nickel silicide, or titanium silicide is formed on the upper surface of the region 104 where the insulating films 108 and 113 are not formed. This seventh
A characteristic configuration of the embodiment is that the height of the upper surface of the conductive region 104 is lower than the height of the bottom of the gate electrode 114. By doing so, the source / drain region can have an elevated structure while keeping the capacitance between the gate electrode 114 and the conductive region 104 small, and the junction depth of the conductive region 104 can be reduced. However, a low-resistance source / drain with a short channel effect can be realized.

Further, an insulating film 111 and an insulating film 112 made of, for example, a silicon oxide film are formed on the upper surface of the conductive layer 115 by lamination. Gate insulating film 113
Is preferably formed lower than the upper surface height of the insulating film 112 in order to form the contact 116 in a good shape even when the gate insulating film 113 is difficult to etch. Further, an insulating film 118 made of, for example, a silicon oxide film or a silicon nitride film is formed on the gate electrode 114, the gate insulating film 113, and the insulating film 112. In addition, for example, polycrystalline silicon doped with Al, P or B, WSi, TiSi, W, AlSi, A
Contact electrode 11 made of lSiCu, Cu, TiN
6 are formed.

Further, polycrystalline silicon doped with Al, P or B, WS
A metal consisting of i, TiSi, AlSi, AlSiCu, Cu, and W is deposited to form an upper wiring layer 117. In FIG. 10, the contact electrode 116 and the wiring layer 117 for the gate electrode are shown in the same cross section together with the contact electrode 116 and the wiring layer 117 for the source / drain electrode. However, these need not be in the same cross section. ) And FIG. 11B,
The sections may be formed at different heights cut on different planes.

Next, FIG. 12 (a) to FIG. 13 (e)
The manufacturing process of the semiconductor device according to the seventh embodiment
Will be described. First, for example, a boron concentration of 10^Fifteen
cm ^-3The semiconductor layer 105 on which the p-type region is formed
You. Next, 10 p-type boron is added to the p-type semiconductor layer 105.
¹²-10^Fifteencm^-2Ion implantation and well diffusion
Then, the concentration of the semiconductor layer 105 may be optimized. I
The energy of the ON implantation is, for example, 100 eV to 100
It is between 0 eV. The concentration of these well regions is 10 ^Fifteenc
m^-3-10¹⁹cm^-3And it is sufficient. Then, in the figure
Are not shown, for example, LOCOS isolation or trench
An isolation region formed by isolation is formed.

Next, boron or indium is ion-implanted into the p-type semiconductor layer 105 to perform well diffusion, and the semiconductor layer 10 is formed.
5 may be optimized. Next, the surface of the semiconductor layer 105 is oxidized or nitrided, for example, by 3 to 50 nm to form a dummy gate insulating film 102, and the dummy gate electrode 101 is formed.
Is deposited on the entire surface of, for example, 10 to 200 nm. Further, after a silicon oxide film serving as the insulating film 106 is formed, for example, by depositing the entire surface to a thickness of 2 to 200 nm or oxidizing the polycrystalline silicon film, the polycrystalline film serving as the insulating film 106 and the dummy gate electrode 101 is formed by lithography and reactive ion etching. The dummy gate electrode 101 is formed by processing the silicon film so as to reach the insulating film 102. Next, a silicon oxide film serving as the insulating film 103 is deposited on the entire surface to a thickness of, for example, 2 to 50 nm, and then processed by anisotropic etching to form a sidewall insulating film on the steep sidewalls of the dummy gate electrode 101. Leave 103. Thereafter, using the insulating film 103 as a mask, the insulating film 102 is etched to expose the semiconductor layer 105.
The side wall insulating film 103 and the insulating film 106 deposited immediately before lithography surround the dummy gate electrode 101, and it becomes easy to selectively grow a semiconductor on the source / drain layer.

Next, for example, as shown in FIG.
Select i, SiGe mixed crystal, SiGeC mixed crystal
By using a selective growth method or a selective deposition method,
For example, the semiconductor layer 104 is formed to a thickness of 5 to 100 nm.
I do. At this time, doping is also performed at the same time, and the semiconductor layer
Reference numeral 104 denotes a donor impurity addition of 10¹⁶-10²¹cm
^-3Adding As, Sb, or P at a low concentration
Desirable for forming shallow junctions. Semiconductor layer 104
Is, for example, AsH₃And PH₃, And As or P
It is adsorbed on the surface of the body layer 104 and then, for example, Si or S
Selective epitaxial growth of iGe mixed crystal and SiGeC mixed crystal
May be formed.

Further, in particular, the {311} plane is formed on the side wall of the gate as shown in FIG. 12A by patterning the semiconductor substrate on the {100} plane and the gate processing in parallel with the <100> direction. Since the structure can be formed so as to move away from the gate side wall upward, the capacitance between the gate and the source and the capacitance between the gate and the drain can be kept smaller.

Next, for example, at 700-1100 ° C.
A step of diffusing the impurity-added n-type region 110 into the p-type semiconductor layer 105 as shown in FIG. 12B by heating for 0.01 to 60 minutes, for example, in an Ar or N2 atmosphere is added. The diffusion time is typically less than n-type region 110
Is formed to below the dummy gate layer 101,
It is desirable to form the electrode so as to reach below the gate electrode 114 to be formed later in order to increase the current driving capability.

In the step of forming the semiconductor layer 104 and the n-type region 110, for example, first, As, P, and SB ions are implanted at an acceleration voltage of 1 to 100 eV and 10 ¹³ to 10 ¹⁶ cm ⁻² to form the n-type region 110. And then the semiconductor layer 1
04 may be replaced with a step of performing selective epitaxial growth. Further, the semiconductor layer 10 to which no impurity is intentionally added.
4 is formed, As, P, and Sb are accelerated to an accelerating voltage of 1 to 30.
0 eV, 10 ¹³ to 10 ¹⁶ cm ⁻² ions are implanted and n
The step of forming the mold region 110 may be replaced.

Further, for example, a silicon oxide film is
An insulating film 108 is formed by depositing the entire surface to a thickness of 00 nm. Next, for example, a silicon nitride film is deposited on the entire surface to a thickness of 10 to 300 nm, and an insulating film 109 is formed on the side wall of the side wall insulating film 108 which is formed by anisotropic etching, thereby obtaining the shape shown in FIG. it can. Here, the insulating film 108 is a buffer layer for relaxing the stress of the insulating film 109, etching selectivity, and reducing the damage.
If there is no particular problem in the etching selectivity of No. 9, the insulating film 108 may not be provided.

Further, by making the sum of the thicknesses of the insulating film 108 and the side wall insulating film 103 smaller than the thickness of the insulating film 102, the insulating film 109 is exposed when the insulating film 102 is peeled off. Thus, the width of the gate insulating film 113 is preferably determined. The interval between the insulating films 109 is set to be twice or more the thickness of a portion of the gate insulating film 113 in contact with the semiconductor layer 105. Further, the insulating film 109 on the semiconductor layer 104 is etched by using the insulating film 109 as a mask.
Then, silicide or metal is selectively formed on the semiconductor layer 104 to be a source / drain region, and a source or drain electrode 115 is formed. To this end, for example, Ni, Co or Ti is deposited on the entire surface in a thickness of 0.01 to 0.03 μm, and NiS is selectively deposited on the semiconductor layer 104 serving as a source / drain region through a heat process of 600 ° C. or more.
i, CoSi or TiSi to form the remaining metal,
For example, it is removed by etching with a sulfuric acid / hydrogen peroxide solution.

Further, for example, a silicon oxide film is
A total thickness of 00 nm is deposited to form an interlayer insulating film 111. Next, for example, a silicon oxide film, PSG, BPSG, or BSG is deposited over the entire surface to a thickness of 50 to 1000 nm, flattened by, for example, Chemical Mechanical Polishing, and an interlayer insulating film 112 is formed. Thereafter, the dummy gate electrode 10 is formed by lithography and anisotropic etching.
12C, the interlayer insulating film 112, the interlayer insulating film 111, the buffer insulating film 108, the insulating film 106, and a part of the side wall insulating film 103 are etched as shown in FIG. The gate electrode 101 is partially exposed.

At this time, the films 112, 111, 108, 1
06 and 103 are formed of a silicon oxide film, and the insulating film 1 is formed.
09 is formed of a silicon nitride film, so that the films 112, 111, 108,
106 and 103 can be selectively etched. Although illustration is omitted, after this etching, the resist used for patterning may be removed by, for example, ashing or an aqueous solution of sulfuric acid and hydrogen peroxide before etching the film 102. And organic contamination.

Next, the dummy gate electrode 101 is subjected to, for example, reactive etching using a gas containing HBr.
Get rid of all. At this time, the films 112, 111, 10
8, 106 and 103 are left by preserving selectivity. Further, the dummy gate insulating film 102 made of a silicon oxide film is entirely removed by, for example, dilute hydrofluoric acid, an aqueous solution of ammonium fluoride, or HF vapor. At this time, the film 108 and the film 103 made of the silicon oxide film are also etched and removed, leaving the side wall insulating film 109 made of the silicon nitride film, and the gate length can be defined by the interval. In the step of removing the film 102, the semiconductor layer 105 is not damaged so that the semiconductor layer 105 is not damaged.
It is desirable to perform wet etching instead of ion etching.

Next, a gate insulating film 113 made of, for example, TiO ₂ or Al ₂ O ₃ (alumina), a tantalum oxide film, strontium titanate, barium titanate, or lead zirconium titanate is formed on the entire surface to a thickness of 10 to 200 nm. accumulate. Further, for example, poly Si, amorpho
us Si, TiNW, Pt, a gate electrode 114 made of RuO ₂ or IrO ₂ and a thickness blanket deposition of 10 to 200 nm, to obtain the shape of FIG. 13 (d). At this time, the interlayer insulating films 111 and 112 are formed of a silicon oxide film as in the case of the film 102, and recede further when the film 102 is etched, and the etching opening becomes larger above the film 109. Therefore, the width of the gate electrode 114 in this portion is also wider than that of the bottom portion, and the gate has a so-called T-shape shape. This shape is desirable for reducing the resistance of the gate electrode and keeping the capacitance between the gate electrode and the source / drain electrode small. At this time, the opening width is determined by the interlayer insulating film 1.
It is desirable that the edge of 11 remains on the side wall insulating film 109 in order to form a good T-shape shape. If the uniformity of the gate insulating film 113 is not good,
As shown in FIG. 13D, a shape is obtained in which a portion becomes narrower as it goes upward in the stacking direction. When the gate electrode 114 is deposited in this state, a notch (void-void-) is formed below the gate electrode as shown in FIG.

Next, for example, Chemical Mechanical Po
The etching is performed by the lishing method until the film 113 is exposed while the entire surface of the gate electrode 114 is planarized. Further, the film 113 is entirely etched until the interlayer insulating film 112 is exposed, thereby obtaining the shape shown in FIG. Membrane 11
3, if the anisotropic etching can be easily performed in the subsequent contact formation step, the step of removing the film 113 can be omitted.

Hereinafter, although illustration is omitted, for example, a silicon oxide film is formed by depositing an interlayer insulating film 118 made of BSG, PSG, and BPSG to a thickness of, for example, 20 to 1000 nm, and then performing wiring contact by lithography and reactive ion etching. Form 116. Contact 11
The depth of 6 is set to reach the gate electrode 114 or the source / drain conductor electrode 115, and the contact 116 is made of, for example, polycrystalline silicon doped with Al, P or B,
WSi, TiSi, W, AlSi, AlSiCu, C
What is necessary is just to deposit or selectively grow u and TiN to bury them. Furthermore, polycrystalline silicon doped with Al, P or B, WSi, TiSi, AlSi, AlSiCu, C
A metal made of u and W is deposited to a thickness of 20 to 500 nm, and an upper wiring layer 117 is formed to complete the process.

According to the method of manufacturing the MIS transistor according to the seventh embodiment, the impurities in the source / drain electrodes are activated and silicide is formed before the gate insulating film 113 is formed. It is not necessary to perform such a process that deteriorates the characteristics of the gate insulating film 113 after forming the gate insulating film. Therefore, a highly reliable process can be realized.

Further, the width of the gate electrode facing the semiconductor region 105 is (the width of the dummy gate 101) + (the thickness of the insulating film 103) * 2 + (the thickness of the insulating film 108) * 2-
(The thickness of the side wall of the gate insulating film 113) * 2, which can be smaller than the width of the dummy gate 101. Therefore, a gate length smaller than that of lithography can be realized by adjusting the widths of the insulating films 103 and 108.

In this structure, FIGS. 11A and 11B are plan views of a single MISFET showing the positional relationship between the gate electrode 114, the source / drain region 110 and the channel region. In both figures, reference numeral 119 denotes, for example, an element isolation film formed by LOCOS isolation or trench isolation. Further, the position of the contact 116 is indicated by using a circle, and it is assumed that one contact is formed for each of the gate, the source, and the drain. The semiconductor region is a rectangular region sandwiched between two source / drain electrodes 110 and a dashed line therebetween and surrounded by the solid line of the gate electrode 114 and formed below the gate electrode 114. The boundaries of the parts are indicated by dashed lines.

In FIG. 11A, the lower width of the gate electrode 114 shown by a dotted line is made constant over the semiconductor region surrounded by the element isolation 119. In this manner, even if the lithography of the gate electrode is misaligned in the vertical direction, a constant gate length can always be obtained, and the transistor characteristics can be matched to provide a resistance against a storage error. FIG. 11B shows a modification of the gate electrode pattern. The gate length (= a) at the boundary between the element isolation 119 and the semiconductor region is the gate length (==) inside the semiconductor region.
It is longer than b). In the gate insulating film 113 formed by a deposited film, the larger the opening width of the groove, the larger the film thickness deposited on the bottom of the groove. Therefore, by adopting the structure of FIG. 11B, the gate insulating film at the boundary between the element isolation 119 and the semiconductor region can be made larger than the plane portion, and the withstand voltage and leak current characteristics at this portion are improved. Can be done. Here, when trench isolation is used for the element isolation film 119, for example, if the element isolation film 119 is etched by the step of etching the dummy gate electrode 102 and the element isolation film 119 is formed below the semiconductor region, Since the semiconductor region becomes convex toward the element isolation film 119 and the gate electric field is concentrated,
The problem is that the threshold value decreases. However, this can be solved by adopting the structure shown in FIG.

The present invention is not limited to the above embodiments. In the embodiment described above, the insulating films 12, 111, 112, 113, 102, 103, 1
As a method of forming the oxide films 06, 108, 118, and 109, an oxide film may be formed by thermal oxidation, an oxide film in which oxygen is implanted at a low acceleration energy of about 30 keV, a method of depositing an insulating film, The silicon nitride film may be formed by any of the methods for depositing, or may be formed by combining these. In addition, the element isolation film or the insulating film forming method itself is a method other than these methods for converting silicon into a silicon oxide film or a silicon nitride film, such as a method of implanting oxygen ions into deposited silicon or a method of oxidizing deposited silicon. May be used. Of course, a silicon nitride film or other tantalum oxide film, a ferroelectric film such as strontium titanate, barium titanate, or lead zirconium titanate, a monolayer film of a paraelectric film, or a composite film thereof may be used as the insulating film. it can.

In the above embodiment, the semiconductor layers 7,
Although a p-type Si substrate was used as 105, the present invention
It is not limited, and instead, an n-type Si substrate or SOI substrate,
A GaAs substrate or an InP substrate may be used. Also, n-type
It may be applied to p-type MISFET instead of MISFET
In this case, the n-type in the above embodiment is p-type,
Read as a type, and as a doping impurity species As,
Replace P and Sb with In or B
In case of In, As, P, Sb are In, B, BF ₂No
It should be read as the difference.

The gate electrodes 6, 10, and 114 are made of single crystal silicon, polycrystal silicon, porous silicon, amorphous silicon, a mixed crystal of SiGe, a mixed crystal of SiGeC, and GaAs.
s, W, Ta, Ti, Hf, Co, Pt, Pd,
An alloy, or silicide thereof, TaN, TiN, or a conductive nitride can also be used. Further, these may have a laminated structure. In addition, various modifications can be made without departing from the scope of the present invention. The dummy gate 10 is made of SiGe or SiGeC
Preferably, the etching selectivity with respect to the source / drain region 2 during the step of removing the dummy gate 10 is increased. According to the MIS transistor and the method of manufacturing the same according to the seventh embodiment, since the inclined surface is formed from the upper surface of the semiconductor layer serving as the source / drain region to the channel forming surface, the distance from the lower end of the gate electrode is reduced. As a result, the capacitance between the gate and the source and the capacitance between the gate and the drain can be kept smaller.

Further, by forming the gate electrode in a T-shape, the resistance of the gate electrode can be reduced, and the capacitance between the gate electrode and the source / drain electrodes can be kept small. To play.

As described in detail above, according to the MIS transistor and the method of manufacturing the same according to the present invention, the resistance of the impurity diffusion layer forming the source / drain can be reduced, and the parasitic capacitance of the gate can be reduced. The operation speed of the transistor can be significantly improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a MIS transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing each step (a) to (e) in the method for manufacturing the MIS transistor according to the first embodiment.

FIG. 3 is a cross-sectional view showing each step (a) to (e) of a method for manufacturing a MIS transistor according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing a configuration of a MIS transistor according to a third embodiment of the present invention.

FIG. 5 is a sectional view showing steps (a) to (e) in a method for manufacturing a MIS transistor according to a fourth embodiment of the present invention.

FIG. 6 is a sectional view showing a configuration of a MIS transistor according to a fourth embodiment of the present invention.

FIG. 7 is a sectional view showing a configuration of a MIS transistor according to a fifth embodiment of the present invention.

FIG. 8 is a sectional view showing steps (a) to (e) in a method for manufacturing a MIS transistor according to a fifth embodiment of the present invention.

FIG. 9 is a sectional view showing a configuration of a MIS transistor according to a sixth embodiment of the present invention.

FIG. 10 is a sectional view showing a configuration of a semiconductor device according to a seventh embodiment of the present invention.

FIGS. 11A and 11B are plan views showing plan configurations of different cross sections (a) and (b) of the semiconductor device shown in FIG. 10;

FIG. 12A is a manufacturing step (a) of the semiconductor device according to the seventh embodiment;
Sectional drawing which shows and (b).

FIG. 13 is a manufacturing step (d) and (e) subsequent to FIG. 12;
FIG.

FIG. 14 is a cross-sectional view illustrating a configuration of a conventional MIS transistor.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 source / drain region 2A source region 2B drain region 2a first impurity diffusion layer 2b second impurity diffusion region 4 groove 5 high dielectric gate insulating film 6 gate electrode 7 channel forming surface 9 silicon oxide film 10 poly Silicon 101 dummy gate electrode 102 dummy gate insulating film 104 semiconductor region 111 insulating film 112 insulating film 113 gate insulating film 114 gate electrode 115 conductor layer

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Mitsuhiro Noguchi 8 Shinsugitacho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Daisaburo Takashima 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Address: Toshiba Yokohama Works (72) Inventor Akira Nishiyama 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Toshiba Yokohama Works

Claims (13)

[Claims] 1. An MIS transistor comprising: a semiconductor substrate; a source / drain region formed on the substrate; and a gate electrode provided above a channel region between the source / drain region. A gate insulating film in which an upper surface of the source / drain region formed on the substrate is located closer to a gate electrode than a channel forming surface of the semiconductor substrate, and an upper surface of the source / drain region is provided on the channel forming surface; A gate insulating film, which is located closer to the channel forming surface than a boundary surface between the gate insulating film and the gate electrode, and wherein the dielectric constant of the gate insulating film is higher than the dielectric constant of silicon oxide. Transistor. 2. A groove is formed in an upper surface of the semiconductor substrate, and a bottom surface of the groove is used as the channel forming surface. The gate insulating film is formed in an opening of the groove with a protective film interposed therebetween. And the source / drain is positioned on both sides of the channel forming surface so that the upper surface of the source / drain region, the channel forming surface, and the boundary surface have a predetermined positional relationship. 2. The MIS transistor according to claim 1, wherein the MIS transistor is configured as follows. 3. An upper surface of a source / drain in which a portion of the semiconductor substrate sandwiching a channel forming surface is located closer to the gate electrode than the channel forming surface, and formed on the channel forming surface via a protective film. 2. The MIS transistor according to claim 1, wherein an upper surface of the source / drain is located closer to the channel formation surface than the boundary surface between the formed gate insulating film and the gate electrode. 3. 4. An upper surface of the source / drain region provided with the channel forming surface interposed therebetween is positioned higher than the channel forming surface on the gate electrode side, and an upper surface of the source / drain region is 2. The semiconductor device according to claim 1, further comprising: a substantially flat surface raised at a level located on the side of the gate electrode, and an inclined surface inclined from the level of the flat surface to the level of the channel forming surface. 3. The MIS transistor according to claim 1. 5. A gate electrode surrounded by a gate insulating film provided on an upper side of the channel forming surface, wherein the shape of the gate electrode has a T-shaped cross section in which the lower side is tapered through a step. The MIS transistor according to claim 4, wherein 6. A gate electrode surrounded by a gate insulating film provided on an upper side of the channel forming surface has a T-shaped cross section in which the lower side is tapered through a step. The MIS transistor according to claim 1, wherein 7. The MIS transistor according to claim 1, wherein said gate insulating film includes a metal oxide film. 8. The gate insulating film comprises at least one of a titanium oxide film, an aluminum oxide film, and a tantalum oxide film.
The MIS transistor according to claim 7, comprising: 9. The gate oxide film according to claim 8, wherein a dielectric constant of said gate oxide film is higher than a dielectric constant of said aluminum oxide film.
3. The MIS transistor according to claim 1. 10. An MIS transistor comprising: a semiconductor substrate; a source / drain region formed on the substrate; and a gate electrode provided above a channel region between the source / drain region. The upper surface of the source / drain region provided with the formation surface interposed therebetween is positioned higher than the channel formation surface on the gate electrode side, and the upper surface of the source / drain region is raised higher than the gate electrode. A substantially flat surface at a level located on the side, and an inclined surface inclined from the level of the flat surface to the level of the channel forming surface, and a gate insulating film provided above the channel forming surface. MIS, characterized in that the shape of the enclosed gate electrode has a T-shaped cross section with the lower side tapering through the step portion. Transistor. 11. A method of manufacturing a MIS transistor comprising a semiconductor substrate, a source / drain region formed on the substrate, and a gate electrode provided above a channel region between the source / drain regions. A step of selectively forming an oxide film on the semiconductor substrate; a step of forming a groove by performing etching using the selectively formed oxide film as a mask; and laminating a polycrystalline semiconductor layer in the groove. Removing the oxide film after polishing the upper surfaces of the oxide film and the polycrystalline semiconductor film, and diffusing impurities into the surface of the semiconductor substrate using the polycrystalline semiconductor film as a mask to form the trench. Forming a groove-shaped impurity diffusion region including a bottom side; and forming a gate insulating film made of a high-dielectric film in a groove portion of the groove-shaped impurity diffusion region. A step of forming a gate electrode on the upper surface of the gate insulating film; and forming a gate electrode on a side farther from the semiconductor substrate than an upper surface of the other portion. Method. 12. A method of manufacturing an MIS transistor including a semiconductor substrate, a source / drain region formed on the substrate, and a gate electrode provided above a channel region between the source / drain regions. A step of selectively forming a polycrystalline semiconductor layer on the semiconductor substrate; and masking the surface of the semiconductor substrate by diffusing impurities using the selectively formed polycrystalline semiconductor layer as a mask. Forming an impurity diffusion region including an impurity diffusion region raised above the channel formation surface to be formed on the surface of the semiconductor substrate, forming an oxide film on the surface side of the raised impurity diffusion region, Polishing the oxide film surface using the polycrystalline semiconductor layer as a stopper, and then removing the polycrystalline semiconductor layer; and Forming a gate insulating film made of a high dielectric film in a region surrounded by the oxide film to a height at which the upper surface is further away from the substrate than a boundary surface between the impurity diffusion region and the oxide film; Forming a gate electrode on the upper surface of the insulating film. 13. A method of manufacturing an MIS transistor including a semiconductor substrate, a source / drain region formed on the substrate, and a gate electrode provided above a channel region between the source / drain regions. Forming a dummy gate insulating film and a dummy gate electrode including a second semiconductor layer on at least the channel forming surface surrounded by the selectively formed semiconductor layer by a method including at least lithography; A semiconductor layer serving as a source / drain region is selectively deposited on the semiconductor substrate, with a region between the semiconductor layer and the channel forming surface being inclined with a region serving as a channel forming surface interposed therebetween. Forming an impurity diffusion region by diffusing an impurity into the surface of the semiconductor substrate using the second semiconductor layer as a mask; A step of etching and removing a dummy gate electrode formed on a portion to be the channel forming surface sandwiched between the impurity diffusion regions; and a step of forming an insulating film made of a high dielectric film on the exposed channel forming surface. Forming a gate insulating film in a cross-sectional shape having a groove-shaped space on the center side, and forming a gate on the upper surface of the gate insulating film formed on the entire surface in a cross-sectional shape having a groove-shaped space on the center side. Deposit the electrodes,
Forming a gate electrode having a T-shaped cross section.