JP5076168B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for manufacturing a semiconductor memory device suitable for higher integration and higher reliability of a dynamic random access memory (DRAM).

  In order to realize high integration and low price as the capacity of a DRAM increases, it is necessary to advance the miniaturization of the memory cell as its basic component. A general DRAM cell is composed of one MOS transistor and one capacitor. Therefore, in order to advance the miniaturization of memory cells, it is important how to secure a large capacitor capacity with a small cell size.

  In recent years, as a method for securing capacitor capacity, a trench type cell in which a trench is formed in a substrate and a capacitor is formed therein, or a stack type in which a capacitor is three-dimensionally stacked on a MOS transistor. A cell has been proposed and adopted as an actual DRAM cell structure. In particular, with regard to the stack type cell, as a development type, a plurality of storage electrodes are arranged in a direction substantially parallel to the substrate, and the upper and lower surfaces of each storage electrode are used as capacitors, so that the capacity per exclusive area can be reduced to normal. Improved cell structures have been proposed, such as fin-type cells, which have been increased over the stack type, and cylinder-type cells, in which the storage electrode is arranged in a cylindrical shape substantially perpendicular to the substrate, thereby increasing the capacity. .

By applying these cell structures and manufacturing processes thereof, it has become possible to realize a 64 Mbit class integrated DRAM having a design rule of 0.35 μm.
However, these technologies alone are not sufficient to realize a 256 Mbit and 1 Gbit class integration DRAM having a design rule of 0.25 μm to 0.15 μm, which has been further integrated. Therefore, it is necessary not only to reduce the area occupied by the capacitor electrode, but also to reduce as much as possible the alignment margin provided in order to prevent adverse effects such as a short circuit between wirings in the photolithography method. There is also a need to solve the problems that arise in improved cell structures such as cylinder-type cells.

  First, there is a problem with alignment. Conventionally, a method called a self-align contact (SAC) method is known as a method for forming a fine contact window. This method is disclosed, for example, in JP-A-58-115859. That is, the gate electrode is patterned in a state where the first insulating film is formed on the gate electrode of the MOS transistor.

Then, after the source / drain diffusion layer is formed, a second insulating film is further formed, and the second insulating film is exposed by using an anisotropic etching method until the diffusion layer is exposed. Etch. As a result, an insulating film is formed on the side wall of the gate electrode portion including the first insulating film, so that the periphery of the gate electrode can be completely insulated by the first and second insulating films and self-aligned. It is possible to form a contact window region on the diffusion layer in a (self-aligning) manner.

  When a contact window is formed by using such a self-aligned contact method, it is not necessary to take an alignment margin between the underlying conductive layer (gate electrode and source / drain diffusion layer) and the contact window. Can be made fine. However, since a highly integrated DRAM cell uses a multilayer process for miniaturization, such a simple self-alignment contact method is still insufficient.

An example of the improved self-alignment contact technique used in the DRAM cell will be described with reference to the schematic cross-sectional views of FIGS. 34 and 35 are cross-sectional views of a typical memory cell section cut along a direction intersecting with the extending direction of the word line (source-drain direction of the MOS transistor). With reference to this figure, a method for forming a contact window between the bit line or the storage electrode and the source / drain diffusion layer of the MOS transistor by using the self-alignment contact technique will be specifically described.

  First, as shown in FIG. 34A, a gate insulating film 113 is formed on a silicon substrate 111 defined by a LOCOS oxide film 112, and a polycide gate electrode made of polysilicon 114 and tungsten silicide 115 is further formed thereon. Form. Source / drain diffusion layers 116 are formed on both sides of the gate electrode. A nitride film 117 covering the periphery of the polycide gate electrode is formed. The polycide electrode corresponds to a word line.

  Since this process is the same as the self-alignment contact method described above, the method described in Japanese Patent Laid-Open No. 58-115859 may be used. Subsequently, a silicon oxide film 118 is formed on the entire surface. This oxide film is planarized by using a CMP (Chemical Mechanical Polishing) method or the like in order to facilitate the subsequent process.

  Next, as shown in FIG. 34B, a resist is applied onto the planarized oxide film 118, and a resist layer is patterned by using a normal photolithography method, thereby serving as an etching mask. A pattern 119 is formed. Next, as shown in FIG. 35A, the oxide film 118 is etched using the resist pattern 119 as a mask to form a contact window 120 that reaches the diffusion layer 116. At this time, the etching condition of the oxide film is set so that the selection ratio with respect to the silicon nitride film is increased. Therefore, even if the nitride film 117 is exposed by etching the oxide film, the nitride film is not etched so much, so that a region substantially equivalent to the self-aligned contact window region formed by the initially formed nitride film is formed as a contact window.

  Subsequently, the resist pattern 119 is removed by a known technique. Next, as shown in FIG. 35B, a conductive layer 121 is formed on the contact window. The contact window formed by the above method does not cause a short circuit between the conductive layer 121 and the polycide electrode even if the resist pattern 119 is displaced and opened in the upper part or the vicinity of the gate electrode. Therefore, it is not necessary to provide a contact window alignment margin with respect to the polycide electrode.

  That is, according to the present technology, the contact window can be formed by self-alignment while the oxide film 118 serving as an interlayer insulating film is planarized. Such a self-alignment contact technique is hereinafter referred to as “nitride film spacer SAC”. In using the nitride film spacer SAC, there are the following problems.

The first is a problem of deterioration of transistor characteristics when the nitride film spacer SAC is used as a gate electrode. Problems when using nitride sidewalls in the gate electrode structure are, for example, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.38 NO.3 MARCH 1991 “Hot-Carrier Injection Suppression Due to the Nitride-Oxide LDDSpacer Structure” T. Mizuno et.al.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.38 NO.3 MARCH 1991 “Hot-Carrier Injection Suppression Due to the Nitride-Oxide LDD Spacer Structure” T. Mizuno et.al. That is, a MOS transistor having a nitride film as a sidewall was formed. In this case, compared with a MOS transistor having an oxide film as a side wall, characteristic deterioration such as a hot carrier effect is large and its reliability is low. This is considered because there are more traps in the silicon nitride film than in the oxide film.

  In the above paper, as a solution to this problem, there is a method in which an oxide film is provided between the nitride film side wall and the gate electrode and between the nitride film side wall and the substrate, thereby suppressing the influence of the nitride film to suppress the deterioration of the transistor characteristics. It is disclosed. However, such a structure cannot be directly applied to the nitride film spacer SAC structure.

  The problem will be described with reference to FIGS. 36 and 37 are cross-sectional views of a typical memory cell section cut in a direction crossing the extending direction of the word line, as in FIGS. 34 and 35, and are denoted by the reference numerals in FIGS. 34 and 35. The same reference numerals are given to the components corresponding to the reference numerals. FIG. 36A is a process corresponding to FIG. 34B and shows a state in which a resist pattern 119 for forming a contact window is formed on the oxide film 118. A silicon nitride film 122 is formed on the polycide electrode composed of the silicon film 114 and the silicide film 115, and the silicon nitride film 124 is formed on the side wall of the polycide electrode and silicon nitride film 122 through the oxide film 123. Is formed. In addition, an impurity region 116 serving as a source / drain diffusion layer is formed in the substrate 111 next to the gate electrode.

  A resist pattern 119 is formed to form a contact window having a nitride film spacer SAC structure. However, the resist pattern is shifted due to misalignment. When the oxide film 118 is etched in this state, the sidewall oxide film 123 between the nitride film sidewall 124 and the polycide gate electrode is also etched at the same time as shown in FIG. It will be exposed.

  Next, as shown in FIG. 37, when the wiring electrode 121 is formed in the contact window, the wiring electrode 121 and the diffusion layer 116 and the gate electrode are short-circuited through the exposed side wall of the gate electrode. In order to avoid this, it is necessary to provide an alignment margin, and the contact window cannot be formed by self-alignment. That is, the nitride film sidewall structure described in the above paper cannot be applied to the nitride film spacer SAC.

  The second problem in the case of using the nitride film spacer SAC is a problem of peeling of the silicide film caused by combining the nitride film spacer SAC and the polycide conductive layer. Since the polycide structure, which is a stacked structure of a silicon film and a silicide film such as tungsten silicide (WSi) or molybdenum silicide (MoSi), has a lower resistance than a silicon film, a gate electrode, a word line, a bit line, etc. Widely used in

  However, when the nitride film spacer SAC process is applied to the conductive layer made of the polycide film, stress is generated due to the difference in thermal expansion coefficient between the polycide film and the nitride film, and the silicide film is peeled off by the heat treatment in the subsequent process. It turns out that there is a phenomenon that it ends up. Therefore, it has been found that the conventional nitride film spacer SAC cannot be used even for a wiring structure such as a bit line, which is not affected by deterioration of transistor characteristics.

Second, there is a problem in the contact window opening process for the plug conductive film embedded in the contact window.
In a highly integrated DRAM structure, it is necessary to perform a planarization process in order to prevent disconnection of a wiring layer in a later process, and a structure in which a conductive film called a plug is embedded in a contact window is employed. When a contact window is opened in order to make contact between the plug and the upper wiring, a process having a margin for misalignment is desirable. Further, it is preferable to use the SAC method for opening the contact window because miniaturization is possible.

  In the condition that the insulating film around the plug is etched in the contact window opening process, a process margin cannot be taken for misalignment, and the SAC method cannot be used. For this reason, it is necessary to provide an alignment margin, which is a problem in promoting integration.

  Third, there is a problem related to the method of forming the cylinder type storage electrode. Since the cylinder-type storage electrode uses the side surface of the cylinder as a capacitor capacity, it is necessary to make the side area of the cylinder constant in order to stabilize the capacity. In general, a cylinder-type storage electrode is formed by forming an opening in an insulating film, forming a conductive layer serving as a storage electrode only on the side wall and bottom surface of the opening, and then etching away the insulating film.

  When such a forming method is employed, after the formation of the cylindrical conductive layer serving as the storage electrode, in the etching of the outer insulating film, the exposed area of the outer surface of the storage electrode varies depending on the etching amount. For this reason, there has been a problem that the capacity is not changed and stabilized.

  Fourth, there is a problem of opening a contact window to a conductive layer having a large height difference. In order to secure a sufficient capacitor capacity with a small cell area, a structure in which the area of the storage electrode is increased by using a three-dimensional structure such as a cylindrical cell as described above has been studied. In order to secure sufficient capacitor capacity, it is necessary to increase the height of the storage electrode portion. For this reason, the height difference (step) between the cell portion and the peripheral circuit portion becomes large.

A large step not only causes a problem of cutting the wiring due to the step, but also, for example, when patterning a metal wiring layer on the cell portion and the peripheral circuit portion, the depth of focus of photolithography is insufficient and the dimensional accuracy is reduced. Cause problems. On the other hand, after forming an insulating film, a coating insulating film such as SOG (Spin On Glass) or a resist is buried in the concave portion and then etched back, or the height difference between the cell portion and the peripheral circuit portion is determined by using the CMP method. A method of planarizing the insulating film so as not to occur is disclosed in, for example, Japanese Patent Laid-Open No. 3-155663.
JP, 3-155663, A By performing such flattening, the problem that a depth of focus is insufficient can be solved. However, the following new problems have emerged. In the DRAM structure, many conductive layers requiring contact with upper metal wiring layers, such as source / drain diffusion layers of MOS transistors in the peripheral circuit portion, word lines and bit lines, bit lines in the memory cell portion, and capacitor counter electrodes. A layer exists.

  These conductive layers are not formed at the same layer level, but are formed in a multilayer wiring structure having several interlayer insulating films. Therefore, there is a difference in the distance from the substrate of each conductive layer. When the upper insulating film is planarized by the above-described method, the surface of the insulating film is formed in a plane substantially parallel to the substrate, so that a difference occurs in the depth of the contact window formed in the insulating film.

  Therefore, when the contact window is formed by a single photolithography process, for example, when the opening that exposes the diffusion layer, which is the lowermost conductive layer, is formed, the uppermost conductive layer is opened first. It will be exposed to the etching atmosphere for a long time while exposed. The etching selectivity of the insulating film to the conductive layer cannot be so large. For this reason, the contact window penetrates through the uppermost conductive layer and further etches down to the lower insulating film, and in some cases, the contact window is short-circuited with another conductive layer below the contact window.

  Therefore, in order to form a highly reliable contact window that does not cause a short circuit with the lower wiring layer, the photolithography process must be divided into a plurality of times to increase the number of processes.

  Fifth, there is a problem of flattening. As the integration becomes higher, the manufacturing process of the DRAM becomes complicated due to miniaturization, and the number of steps increases. This also causes a decrease in product yield and ultimately increases costs. On the other hand, for high integration, a multilayer wiring process is used, and flattening of an insulating layer and a wiring layer is important.

Therefore, a technique for flattening without complicating the manufacturing process is necessary.
Sixth, there is a problem of MOS transistor characteristics. As the integration becomes higher, the MOS transistors are also miniaturized, and it is conceivable that the characteristics are deteriorated and the reliability is lowered due to the miniaturization.
JP-A-8-97210 JP 56-27971 A Japanese Patent Laid-Open No. 61-19479 JP 62-261145 A JP-A-6-181209

An object of the present invention is to provide a technique that can apply a nitride film spacer SAC structure to a polycide structure, advance miniaturization of DRAM memory cells, and realize high integration.
Another object of the present invention is to provide a technique that has a process margin for misalignment on a plug and can apply a SAC structure.

Still another object of the present invention is to provide a technique capable of obtaining a stable capacity by making the exposed area of the outer side surface of the cylinder type storage electrode constant.
Another object of the present invention is to provide a MOS transistor structure which can be used in a memory cell portion of a DRAM and has improved characteristics.

According to a first aspect of the invention,
Forming a gate insulating film and a gate electrode on a base plate,
Forming an impurity diffusion layer regions in said substrate a pre Symbol gate electrode as a mask,
Forming a first insulating film covering the front Symbol gate electrode and the impurity diffusion region,
Etching the previous SL first insulating film, forming a first contact window to the impurity diffusion layer region,
Before SL first contact the window, and forming a first contact plug electrically connected to the impurity diffusion layer region,
Forming a first conductive pattern on the first insulating film;
Forming a first silicon nitride film on the top surface of the first conductive pattern;
Forming a second insulating film having different etching characteristics from the previous SL covering the first insulating film and the first silicon nitride film, the first silicon nitride film,
Forming a second silicon nitride films having different etching characteristics from the previous SL on the second insulating film, said second insulating film,
Previous SL second silicon nitride film and the second insulating film is etched, and forming a second contact window reaching said first contact plug,
Forming a accumulation electrodes inside the front Stories second contact window,
A step of forming the capacitor insulating film, forming a pair counter electrode on the capacitor insulating film over the prior SL storage electrode and the second insulating film,
The pre-Symbol counter electrode as a mask, removing the capacitor insulating film and the second silicon nitride film,
After the step of removing the pre-Symbol second silicon nitride film, and forming a third insulating film so as to cover the opposing electrodes,
The third insulating film, by etching the second insulating film and the first silicon nitride film, the first conductive third contact window reaching the conductive pattern is formed, the second insulating film Etching the third insulating film, the counter electrode, and the second silicon nitride film as an etching stopper to form a fourth contact window;
Before Symbol third contact in the window, the second contact plug formed which is electrically connected to the first conductive pattern, the fourth contact in the window, which is electrically connected to the counter electrode Forming a third contact plug ;
Have
End of the previous SL second silicon nitride film has a contact with the third contact window
The method of manufacturing a semiconductor device comprising a call is provided.

  This contributes to DRAM miniaturization, an increase in manufacturing margin, shortening of manufacturing processes, and the like.

  Process design can be performed in consideration of both the effect of obtaining a stabilized capacitance and the effect of facilitating flattening by reducing the height difference between the memory cell portion and the peripheral circuit portion. A DRAM can be manufactured.

It is sectional drawing explaining the basic Example of this invention. It is a schematic plan view which shows a memory cell part. FIG. 6 is a schematic cross-sectional view (part 1) illustrating the manufacturing process of the first DRAM according to the first embodiment of the invention; FIG. 6 is a schematic cross-sectional view (No. 2) showing the manufacturing process of the first DRAM according to the first embodiment of the invention; FIG. 7 is a schematic cross-sectional view (part 3) illustrating the manufacturing process of the first DRAM according to the first embodiment of the invention; FIG. 6 is a schematic cross-sectional view (part 4) illustrating the manufacturing process of the first DRAM according to the first embodiment of the invention; FIG. 10 is a schematic cross-sectional view (No. 5) showing the manufacturing process of the first DRAM according to the first embodiment of the invention; FIG. 22 is a schematic cross-sectional view (No. 6) showing the manufacturing process of the first DRAM according to the first embodiment of the invention; FIG. 17 is a schematic cross-sectional view (No. 7) showing the manufacturing process of the first DRAM according to the first embodiment of the invention; FIG. 16 is a schematic cross-sectional view (No. 8) showing the manufacturing step of the first DRAM according to the first embodiment of the invention; It is a schematic cross section (the 9) which shows the manufacturing process of the 1st DRAM by the 1st Embodiment of this invention. FIG. 10 is a schematic cross-sectional view (No. 10) showing a manufacturing step of the first DRAM according to the first embodiment of the invention; It is a schematic cross section (the 11) which shows the manufacturing process of the 1st DRAM by the 1st Embodiment of this invention. FIG. 22 is a schematic cross-sectional view (No. 12) showing a manufacturing step of the first DRAM according to the first embodiment of the invention; It is a schematic cross section figure (1) which shows the manufacturing process of the 2nd DRAM by the 2nd Embodiment of this invention. It is a schematic cross section (the 2) which shows the manufacturing process of the 3rd DRAM by the 2nd Embodiment of this invention. It is a schematic cross section (the 1) which shows the manufacturing process of the 4th DRAM by the 3rd Embodiment of this invention. It is a schematic cross section (the 2) which shows the manufacturing process of the 4th DRAM by the 3rd Embodiment of this invention. It is a schematic cross section (part 3) showing the manufacturing process of the fourth DRAM according to the third embodiment of the present invention. It is a schematic cross section (the 4) which shows the manufacturing process of the 4th DRAM by the 3rd Embodiment of this invention. It is a schematic cross section figure (5) which shows the manufacturing process of the 4th DRAM by the 3rd Embodiment of this invention. It is a schematic cross section explaining the effect of the 3rd embodiment of the present invention (the 1). It is a schematic cross section explaining the effect of the 3rd embodiment of the present invention (the 2). It is a schematic cross section which shows the manufacturing process of the 5th DRAM by the 4th Embodiment of this invention (the 1). It is a schematic cross section (the 2) which shows the manufacturing process of the 5th DRAM by the 4th Embodiment of this invention. It is a schematic cross section (part 3) showing the manufacturing process of the fifth DRAM according to the fourth embodiment of the present invention. It is a schematic cross section (part 4) showing the manufacturing process of the fifth DRAM according to the fourth embodiment of the present invention. It is a schematic cross section figure (5) which shows the manufacturing process of the 5th DRAM by the 4th Embodiment of this invention. It is a schematic cross section (the 1) which shows the manufacturing process of the 6th DRAM by the 5th Embodiment of this invention. It is a schematic cross section (No. 2) showing the manufacturing process of the sixth DRAM according to the fifth embodiment of the invention. It is a schematic cross section which shows the manufacturing process of the 7th DRAM by the 6th Embodiment of this invention. It is a schematic cross section which shows the manufacturing process of the 8th DRAM by the 7th Embodiment of this invention. It is a schematic cross section which shows the manufacturing process of the 9th DRAM by the 8th Embodiment of this invention. FIG. 6 is a schematic cross-sectional view (part 1) illustrating a nitride film spacer SAC. FIG. 6 is a schematic cross-sectional view (part 2) for explaining the nitride film spacer SAC. It is a schematic cross section explaining the problem of a prior art (the 1). It is a schematic cross section explaining the problem of a prior art (the 2).

Embodiments of the present invention will be described below with reference to the drawings. 1A and 1B show a semiconductor device according to a basic embodiment of the present invention and its modification.
A basic embodiment of the present invention will be described with reference to FIG. In FIG. 1A, 1 is a silicon substrate, 2 is a field insulating film, 3 is a gate oxide film, 4 is a silicon film, 5 is a silicide film, 6 is a silicon oxide film, 7 is an impurity diffusion layer region, and 8 is silicon. A nitride spacer, 9 is an interlayer insulating film, and 10 is a contact window.

  A gate electrode made of a laminate of a silicon film 4 and a silicide film 5 is formed on a substrate 1 having an active layer region defined by a field insulating film 2 via a gate oxide film 3. The upper and side surfaces of the gate electrode are covered with the silicon nitride film 8. An oxide film 6 exists between the lower portion of the silicon nitride film 8 as a side spacer and the side wall of the gate electrode.

  Since the oxide film 6 exists below the silicon nitride film 8 serving as a spacer, most of hot carriers generated in the MOS transistor channel portion are trapped in the oxide film 6. The MOS transistor characteristics are hardly affected by the silicon nitride film 8. Therefore, reliability equivalent to that of a MOS transistor using a conventional oxide film spacer can be obtained.

  On the other hand, the oxide film 6 existing between the side wall of the gate electrode and the silicon nitride film functions as a buffer film between the silicide film 5 and the nitride film 8, and the silicide film is peeled off in a later heat treatment process or the like. Can be prevented. Further, since the silicon oxide film 6 exists only on the side wall portion of the gate electrode and the silicon oxide film is not exposed in the region above the gate electrode, a mask is formed when the contact window 10 is formed using the nitride film spacer SAC. Even if the position is shifted, the problem that the conductive layer and the gate electrode are electrically short-circuited as described in the conventional example does not occur.

  FIG. 1B is a diagram for explaining another example according to the basic embodiment of the present invention. In FIG. 1B, 1 is a silicon substrate, 2 is a field insulating film, 3 is a gate oxide film, 4 is a silicon film, 5 is a silicide film, 7 is an impurity diffusion layer region, 8 is a silicon nitride film spacer, An interlayer insulating film, 10 is a contact window, and 11 is a silicon oxide film. In addition, the same number is attached | subjected to the thing corresponded to the number in Fig.1 (a).

  Compared with the structure of FIG. 1A, an oxide film is also provided on the upper part of the silicide film 5 constituting the gate electrode, and the upper part and the side wall of the gate electrode are completely covered with the silicon oxide film 11. In this structure, since the silicon nitride film 8 and the silicide film 5 are not in direct contact with each other, the structure becomes stronger against peeling due to a process such as a subsequent heat treatment.

The structure shown in FIGS. 1A and 1B can be applied not only to the gate electrode of the MOS transistor but also to other wiring layers such as a bit line having a polycide structure.
Hereinafter, more specific embodiments will be described. In addition, the same code | symbol is used for the code | symbol in a figure which is the same or equivalent in each embodiment.

  FIG. 2 is a schematic plan view of the memory cell portion of the DRAM. In the figure, 11 is an active region, 12 is a word line that also serves as a gate electrode of a MOS transistor, 13 is a bit line, 14 is a contact window between the bit line and the source / drain diffusion layer of the MOS transistor, and 15 is a cylinder-type storage electrode. This is a contact window with the source / drain diffusion layer of the MOS transistor. A wiring layer such as a backing word line formed on the gate electrode or the bit line is not shown in the drawing.

Here, the basic example and the prior art will be described briefly.
Japanese Patent Application Laid-Open No. 8-97210 describes a structure that looks similar to FIG. However, this publication does not describe any problem that the silicide film is peeled off by forming the nitride film directly on the silicide film, and by forming an oxide film between the nitride film, There is no description about the effect of preventing peeling.

  In the invention described in this publication, for example, as shown in FIG. 1 of the publication, a sidewall silicon oxide film is formed up to a region above the gate electrode, and a silicon nitride film region covering the gate electrode is formed. In this structure, an oxide film bites into the silicon nitride film, and a part of the silicon nitride film is thinly formed. In such a structure, when the contact window is formed in a later process, the nitride film is etched to expose the side wall oxide film, and the wiring layer formed in the contact window and the gate electrode may be short-circuited. There is.

  According to the first aspect of the present invention, the oxide film on the side wall is only on the side wall of the gate electrode and does not penetrate into the silicon nitride film covering the gate electrode, so that the structure is different. Since the oxide film does not penetrate, the nitride film thickness is not reduced, and the danger that the gate electrode is exposed when the contact window is formed can be avoided.

  In this publication, an oxide film is formed by a CVD method in order to form an oxide film on the side of the silicon nitride film on the gate electrode. However, in the present invention, not only a CVD oxide film but also an oxide film can be formed by a thermal oxidation method. By using the oxide film formed by the thermal oxidation method, the effect of preventing the separation of the silicide film can be increased as compared with the case of using the CVD oxide film.

  Furthermore, since the oxide film obtained by thermally oxidizing the substrate has a better interface state between the substrate and the oxide film than the CVD oxide film, the thermal oxide film exists between the substrate and the silicon nitride film. As compared with the case where the CVD oxide film is between the substrate and the silicon nitride film, the MOS transistor characteristics are improved and the reliability is increased.

  Japanese Patent Laid-Open No. 61-16571 describes a structure in which a laminated structure of an oxide film and a nitride film is provided on a gate electrode, and a nitride film sidewall is provided on the side wall of the gate electrode. However, in this publication, there is no oxide film on the side wall of the gate electrode, which is completely different in that the nitride film and the gate electrode are in direct contact with each other, and there is no description about the problems in the case of the polycide structure. Not.

  Japanese Patent Application Laid-Open No. 56-27971 describes a structure in which the upper surface and side walls of a gate electrode are covered with an oxide film and a nitride film as Example 2. However, there is no oxide film under the nitride film on the side wall of the gate electrode, and the structure is different from that of the present invention, and the effect of improving the characteristics of the MOS transistor cannot be expected. In addition, this publication does not describe any problems caused by using a polycide structure or forming a nitride film on the polycide.

  Japanese Patent Application Laid-Open No. 61-194779 describes a structure in which an upper surface and a side wall of a gate electrode are covered with an oxide film and a nitride film. However, this publication does not describe any problems caused by using a polycide structure or forming a nitride film directly on the polycide. Japanese Patent Application Laid-Open No. 62-261145 describes forming a composite film composed of an oxide film and a silicon nitride film around a wiring layer having a polycide structure. However, the object of the invention described in this publication is to use a silicon nitride film to prevent metal contamination from a silicide film formed by sputtering, and is completely different from that related to the nitride film sidewall SAC structure.

  In addition, this publication describes that a silicon nitride film may be provided under an oxide film, and the silicon nitride film may be in direct contact with the polycide. By forming the nitride film directly on the silicide film, There is no description about the problem that the film is peeled off, nor is there any mention of the effect of preventing peeling by forming an oxide film between the film and the nitride film.

  Further, this publication forms a composite film of an oxide film and a silicon nitride film after patterning the polycide structure, and after patterning after forming an oxide film and a silicon nitride film on the polycide of the present invention, continues. This is different from the method of forming the sidewall oxide film or silicon nitride film. In addition, by making the oxide film thickness on the electrode made of polycide thicker than the oxide film thickness formed on the electrode sidewall, the effect of preventing the peeling of the nitride film can be increased. There is no mention of that point.

Thus, the above five known examples are completely different from the basic embodiments of the present invention, and nothing that suggests them is described.
According to the second aspect of the present invention, there is a nitride film functioning as an etching stopper layer around the conductive layer for wiring formed in the contact window, and an underlying interlayer insulating film such as an oxide film or BPSG is formed. Since it is not exposed on the surface, the lower insulating film around the conductive layer is etched even when misalignment occurs when the contact window of the upper interlayer insulating film formed on the nitride film is formed. No, it is a process with a large margin against misalignment.

Further, when the contact window is formed on the side of the upper wiring layer, the lower insulating film is not etched, so that the SAC process can be performed.
According to the third aspect of the present invention, when the cylinder-type storage electrode is formed, a nitride film functioning as an etching stopper film is formed under the insulating film outside the storage electrode. Since all of the outer insulating film can be removed, the area of the outer surface of the cylinder-type storage electrode can be made constant, the variation in capacitor capacitance is small, and a stable DRAM cell can be manufactured. .

It is also possible to manufacture a DRAM cell without greatly increasing the height difference between the cell region and the peripheral circuit portion.
According to the fourth aspect of the present invention, even if the contact window has a different depth, the window can be opened by a single photolithography process, and means for reducing the number of manufacturing processes is provided. is there.

  According to the fourth aspect of the present invention, when a contact window is formed in a plurality of wiring layers, a nitride film is provided under the upper wiring layer, and the contact window is formed by etching using the nitride film as a stopper. It is possible to prevent the wiring layer from penetrating from the upper wiring layer to the insulating layer below the nitride film and reaching the lower wiring layer. Accordingly, short-circuiting between layers can be prevented, so that contact windows of upper and lower wiring layers having different contact window depths can be formed by a single photolithography process, thereby shortening the process. it can.

  Further, by forming a nitride film on the intermediate wiring layer between the upper layer and the lower layer, performing the first step etching using the nitride film as a stopper, and then performing the second step etching for etching the nitride film, It is possible to prevent the contact window from reaching the lower wiring layer by penetrating through the insulating layer under the nitride film from the upper wiring layer or through the intermediate wiring layer and further through the lower insulating layer. Accordingly, short circuit between layers can be prevented, so that contact windows of upper layers, intermediate layers, and lower wiring layers having different contact window depths can be formed by a single photolithography process, thereby shortening the process. it can.

According to the fifth aspect of the present invention, there is provided a method that simplifies the manufacturing process by applying a planarization step to the nitride film spacer SAC.
According to the fifth aspect of the present invention, when the insulating film on the wiring group used for the nitride film spacer SAC is planarized, a new layer serving as a stopper is formed by using the nitride film as a CMP stopper. It is possible to flatten without. Therefore, accurate planarization is possible without increasing new processes. Also, in the step of planarizing the insulating film formed on the wiring layer group having a different distance from the substrate, the nitride film provided on the wiring group having the largest distance from the substrate is used as a stopper in the CMP process. Thus, the insulating film provided on the wiring layer group can be planarized with high accuracy.

  At this time, since the film below the insulating film on the wiring group that is not the longest distance from the substrate is not exposed to polishing as a stopper, it is possible to maintain a constant thickness and maintain a withstand voltage. . Japanese Patent Laid-Open No. 6-181209 discloses a method in which a silicon nitride film is provided on the upper surface of a conductive layer and an insulating film formed thereon is planarized by CMP using the silicon nitride film as a stopper. FIG. 4 of this publication describes that, as a conventional technique, a silicon nitride film is provided between the upper and side surfaces of a conductive layer patterned into a desired shape and between conductive layers, and this is used as a stopper film for CMP. ing.

However, this publication does not describe anything about the nitride film spacer SAC, and does not describe any problems when the nitride film spacer SAC is used in a DRAM.
In the DRAM manufacturing method, the nitride film on the conductive layer is used as a stopper layer, so that the insulating film formed thereon can be planarized and the variation in film thickness can be reduced.

  If the thickness of the planarized insulating film varies, the etching amount when the contact window is formed by the nitride film spacer SAC in the subsequent process is distributed, and the nitride film region is reduced when the contact window is formed, and the conductive layer is contacted with the conductive layer. There is an increased risk of a short circuit with the upper conductive layer formed in the window.

  The nitride layer spacers necessary for using the nitride film spacer SAC can be used as they are instead of forming the stopper layer, so that a new process is not increased.

  In the above-mentioned known example, there is no description about a specific problem when such a nitride film spacer SAC is used in a DRAM, and there is no suggestion about means for solving it. Furthermore, in the present invention, the wiring layers are provided at different distances from the substrate, and only the nitride film of the wiring layer having the longest distance from the substrate is used as a stopper, and nitriding on the wiring layer at a level closer to the substrate than that is used. By preventing the film from functioning as a stopper, the breakdown voltage of the nitride film of the wiring layer close to the substrate can be prevented from being lowered, but this is not described anywhere in this publication.

  According to the sixth aspect of the present invention, impurities for preventing junction leakage are introduced only into the capacitor side source / drain region of the memory cell portion, and junction leakage is introduced into the source / drain region on the side connected to the bit line. Impurities are not newly introduced to prevent this.

  By performing the impurity implantation only on the side to which the capacitor is connected, one of the source / drain of the MOS transistor can have a shallow junction depth, which can reduce the short channel effect of the transistor and the leakage current between elements. Adverse effects can be suppressed, and junction leakage can be suppressed on the capacitor side that is severe with respect to junction leakage.

[First embodiment]
With reference to FIGS. 3 to 13, a method for forming a contact window in the DRAM according to the first embodiment of the present invention by using a self-alignment contact technique will be described in detail. 3 to 13 are schematic cross-sectional views of a wiring structure as a typical example of the AA ′ portion of FIG. 2 for the memory cell portion and a typical example of the peripheral circuit portion. First, as shown in FIG. 3A, a thick oxide film 17 (field oxide film) is formed on a p-type silicon substrate 16 by using a well-known LOCOS method (LOCal Oxidation of Silicon). An active area is defined. In the figure, MC represents a memory cell region and PC represents a peripheral circuit region.

  Since various circuits are formed in the peripheral circuit region, normally, an n-channel MOS transistor formation region and a p-channel MOS transistor formation region in which an n-channel MOS transistor formation region for forming these circuits is formed Are formed in an n-type well formed in a p-type silicon substrate, and an n-channel MOS transistor formation region is formed in a p-type well formed in a p-type silicon substrate. And those formed in a p-type well (triple well structure) further formed in an n-type well formed in a p-type silicon substrate. These configurations may be appropriately selected depending on desired characteristics.

  Therefore, although not shown, p-type impurities and n-type impurities are ion-implanted into other regions of the peripheral circuit region PC before and after the LOCOS process to form p-type wells and n-type wells, respectively. By introducing a p-type impurity further into a part of the n-type well region, a p-type well surrounded by the periphery and bottom of the n-type well is formed.

  At this time, if necessary, a p-type impurity or an n-type impurity is ion-implanted below the field oxide film 17 in consideration of the impurity type of the well to form a channel stop layer. Further, although not shown in the figure, an impurity for controlling the threshold value (Vth) is introduced into the active region in accordance with the characteristics of each MOS transistor.

  The above-described well layer, channel stop layer, and Vth control ion implantation do not necessarily have to be performed at this position in the process. A gate oxide film formation process, a gate electrode formation process, and the like, which will be sequentially described below, are performed. It goes without saying that it doesn't matter later.

  As shown in FIG. 3 (b), the substrate surface is oxidized to form a gate oxide film 18 having a thickness of 8 nm, a phosphorous-doped silicon film 19 is 50 nm, a tungsten silicide (WSi) film 20 is 50 nm, The silicon nitride film 21 is sequentially formed to a thickness of 80 nm by using a known CVD method (Chemical Vapor Deposition chemical vapor deposition method).

  These laminates are patterned into a desired pattern using a known photolithography method so as to become a gate electrode of a MOS transistor. In the cell portion, the polycide structure of these stacked bodies is a word line (corresponding to 12 in FIG. 1).

  As shown in FIG. 4A, an oxide film 22 is grown by 2 to 10 nm by thermal oxidation. This oxidation forms an oxide film on the sidewalls of the polycide structure silicon film 19 and WSi film 20 and on the surface of the silicon substrate 16 in the active region, but the silicon nitride film is not oxidized. A film is not formed. Further, since the silicon film 19 has a higher impurity concentration than the substrate 11, the thickness of the oxide film 22 is thicker than that of the substrate.

Next, using the gate electrode as a mask, phosphorus, which is an n-type impurity, is ion-implanted into the entire surface of the substrate at a dose of 1 × 10 ¹³ cm ⁻² . As a result, an impurity diffusion layer 23 corresponding to an n ⁻ layer having an LDD (Lightly Doped Drain) structure is formed in the n-channel MOS transistor region. At this time, this n-type impurity is also introduced into the p-channel MOS transistor region, but there is no problem because it can be substantially eliminated by ion implantation of a high-concentration p-type impurity layer in a later step. If this n-type impurity region is left around the p-type impurity diffusion layer serving as the source / drain portion, it is possible to play a role of preventing punch-through.

  As shown in FIG. 4B, a silicon nitride film having a thickness of 50 to 150 nm is formed by a CVD method and anisotropically etched by a known RIE (Reactive Ion Etching) method or the like, thereby nitriding the side wall of the gate electrode. A sidewall spacer made of a film is formed. At this time, it is more preferable to finish the etching in the state where the oxide film 22 in the region not covered with the nitride film such as the substrate 16 is left because the etching damage is less, but it is not always necessary to leave it. Absent.

  This sidewall nitride film is integrated with the nitride film 20 on the polycide electrode to form a nitride film region 24 that continuously covers the side surface from the upper surface of the gate electrode. By this step, the periphery of the polycide electrode composed of the silicon film 19 and the WSi film 20 is covered with the nitride film region 24. However, since the oxide film 22 exists in the side wall portion of the polycide electrode, the WSi film 20 is subjected to a heat treatment in a later step. Can be prevented from peeling from the substrate.

  Subsequently, an oxide film is grown by 2 to 10 nm by thermal oxidation. At this time, the oxide film 22 exposed on the silicon substrate may be oxidized after being removed with a hydrofluoric acid-based etchant. Although it is better to remove from the controllability of the film thickness, there is a risk that the field oxide film 17 and the oxide film 22 below the sidewall nitride film may be removed. By this oxidation, the surface of the silicon substrate on the active region is mainly oxidized and integrated with the oxide film 22. The silicon film 19 and the WSi film 20 covered with the nitride film region 24 are not oxidized. In the present embodiment, the integrated oxide film is hereinafter referred to as an oxide film 22.

Subsequently, a resist pattern is formed so that the n-channel MOS transistor region in the peripheral circuit region excluding the memory cell region is exposed, and an n-type impurity is formed in the opening region of the resist using the gate electrode having the nitride film region 24 as a mask. Is implanted at a dose of 5 × 10 ¹⁵ cm ⁻² . As a result, a high concentration impurity diffusion layer region 25 is formed as an n ⁺ layer having an LDD structure in the n channel MOS transistor region in the peripheral circuit region.

The reason why the ion implantation of the high-concentration n-type impurity layer is not performed in the source / drain layer of the transistor in the memory cell region is that leakage from the capacitor that prevents a crystal defect due to introduction of the high-concentration impurity and stores a minute charge. This is to suppress the current. Subsequently, a resist pattern is formed so as to expose the p-channel MOS transistor region in the peripheral circuit region, and 5 × 10 5 BF ₂ ⁺ ions are formed in the opening region of the resist using the gate electrode having the nitride film region 24 as a mask. Ion implantation is performed at a dose of ¹⁵ cm ⁻² to form an impurity diffusion layer region that becomes a source / drain region of the p-channel MOS transistor.

  As shown in FIG. 5A, after a borophosphosilicate glass (BPSG) film 26 is grown to a thickness of 100 to 200 nm by a CVD method, heat treatment is performed at a temperature of 750 to 900 ° C., and reflow is performed to flatten the surface. In order to perform further planarization, an etch back method or a CMP method may be used, or a combination of these may be used for planarization.

When the etch back method or the CMP method is used, the BPSG film is grown as thick as the film thickness to be removed so that the film thickness after the etch back or CMP process becomes 100 to 200 nm. Subsequently, a resist pattern having an opening exposing the source / drain region of the MOS transistor in the memory cell region is formed, and a BPSG film 26 and an oxide film 22 in the opening are used, for example, a mixed gas of C ₄ F ₈ and CO. Etching is sequentially performed by the RIE method to expose the substrate surface and form the contact window 27.

  The bottom of the contact window 27 is defined by the spacer of the nitride film region 24 in a self-aligned manner. Even if the opening of the resist pattern is displaced, the entire area of the polycide gate electrode is covered with a nitride film and the oxide film is not exposed, so that it is not removed by etching. The gate electrode and the contact electrode as described in the conventional example are not short-circuited.

Desirably, the etching of the BPSG film 26 and the oxide film 22 is preferably performed under the condition that the etching selectivity to the nitride film is 10 or more so that the nitride film region 24 is not etched. Subsequently, after removing the resist pattern, phosphorus as an n-type impurity is ionized at a dose of 3 × 10 ¹³ cm ⁻² into the silicon substrate of the contact window 27 using the BPSG film 26 and the nitride film region 24 as a mask. The n-type diffusion layer 28 is formed by implantation.

  The n-type diffusion layer 28 is not always necessary, but when the contact window 27 is displaced and formed near the edge of the field oxide film 17, n-type impurities for forming the source / drain diffusion layer are introduced. It is possible to prevent a problem that junction leakage increases near the edge of the field oxide film 17 that has not been formed.

  As shown in FIG. 5B, after a silicon film doped with phosphorus is formed on the entire surface by the CVD method, the plug 29 of the silicon film is left in the contact window 27 by using an etch back method or a CMP method. Alternatively, the silicon film plug 29 may be formed by using a selective CVD method without using the etch back method or the CMP method. Subsequently, an oxide film 30 is grown to 30 to 100 nm by a CVD method.

  As shown in FIG. 6A, a resist pattern having an opening in the bit line connection region is formed, and the oxide film 30 is etched using the resist pattern as a mask so that a part of the upper surface of the silicon film plug 29 is exposed. After the contact window 31 is formed, the resist is removed. Subsequently, a silicon film 32 doped with phosphorus, 30 nm, a WSi film 33 of 50 nm, and a silicon nitride film 34 of 80 nm are sequentially formed by CVD.

  These laminates are patterned into a desired wiring pattern using a known photolithography method. The polycide electrode of these stacked bodies becomes a bit line (corresponding to 13 in FIG. 2) in the memory cell portion, and is also used as a wiring layer other than the bit line in the peripheral circuit portion.

  As shown in FIG. 6B, an oxide film 35 is grown by 2 to 10 nm by thermal oxidation. By this oxidation, an oxide film is formed on the side walls of the polycide structure silicon film 32 and the WSi film 33, but the silicon nitride film is not oxidized, and therefore no oxide film is formed on the side wall of the silicon nitride film 34.

  Subsequently, a silicon nitride film having a thickness of 50 to 150 nm is formed by a CVD method and anisotropically etched by the RIE method to form a sidewall made of a nitride film on the side wall of the bit line. This sidewall nitride film is integrated with the nitride film 34 on the polycide electrode to form a nitride film region 36 that continuously covers the side surface from the upper surface of the polycide electrode.

  By this step, the periphery of the polycide electrode composed of the silicon film 32 and the WSi film 33 is covered with the nitride film region 36. Since the oxide film 35 exists on the side wall portion of the polycide electrode, it is possible to prevent the WSi film 33 from being peeled off from the substrate by a heat treatment in a later step.

As shown in FIG. 7, after the BPSG film 37 is grown to a thickness of 500 nm by the CVD method, heat treatment is performed at a temperature of 750 to 900 ° C. and reflow is performed to flatten the surface.
Further, in order to perform planarization, an etch back method or a CMP method may be used, or planarization may be performed by combining these. Note that in the case of using the etch back method or the CMP method, the BPSG film is grown as thick as the film thickness to be removed so that the film thickness after the etch back or CMP process becomes 500 nm.

  The thickness of the BPSG film 37 is one of the conditions for determining the capacity in the case of a cylinder type storage electrode. Therefore, when a larger capacity is required, it is necessary to form the film to a thickness of 500 nm or more.

As shown in FIG. 8, a resist pattern having an opening through which the capacitor connection region is exposed is formed. Using the resist pattern as a mask, the BPSG film 37 and the oxide film 30 in the opening are formed by using, for example, a mixed gas of C ₄ F ₈ and CO. Etching is sequentially performed by a method to form a contact window 38 that exposes the upper surface of the silicon film plug 29.

  Normally, when a cylinder type storage electrode is used, the size of the contact window 38 is related to the bottom area and the peripheral length of the cylinder type storage electrode. Therefore, it is desirable to open as large as possible in order to increase the capacitor capacity. In the present invention, since the contact window 38 is defined by a bit line and self-alignment by the nitride film region 36, the contact window can be extended to the top of the polycide electrode that is the bit line, and the bottom area of the cylinder-type storage electrode and The perimeter can be maximized.

  In addition, since the entire periphery of the polycide electrode (bit line) is covered with the nitride film region 36, the polycide electrode (bit line) is not removed by etching, and the bit line and the storage electrode are not short-circuited. Desirably, the etching of the BPSG film 37 and the oxide film 30 is preferably performed under the condition that the selectivity with respect to the nitride film is 10 or more.

  As shown in FIG. 9, after removing the resist pattern, a silicon film doped with phosphorus is formed by CVD to a thickness of 50 nm, and then the silicon film is formed only on the side wall and bottom surface in the contact window 38 using the etch back method or CMP method. 39 remains.

  As shown in FIG. 10, the BPSG film 37 is subjected to control etching using a hydrofluoric acid-based etchant to leave, for example, about 150 nm, thereby forming a cylindrical storage electrode 39 in which the interior is hollowed out.

As shown in FIG. 11, a capacitor insulating film is formed on the surface of the storage electrode 39 by forming a silicon nitride film with a thickness of 40 nm by the CVD method and thermally oxidizing the film with a thickness of 1 to 2 nm. (The capacitor insulating film is shown integrated with the storage electrode 39 in the figure.)
Subsequently, after forming a silicon film doped with phosphorus by CVD with a thickness of 50 nm, the counter electrode 40 of the capacitor is formed by patterning. At this time, the capacitor insulating film 39a is also removed in accordance with the pattern of the counter electrode 40.

  As shown in FIG. 12, after the BPSG film 41 is grown by 1 μm by the CVD method, heat treatment is performed at a temperature of 750 to 900 ° C. and reflow is performed to flatten the surface. Further, in order to perform planarization, an etch back method or a CMP method may be used, or planarization may be performed by combining these. By such planarization, there is almost no difference in height between the memory cell region and the peripheral circuit region, and a substantially flat surface can be obtained.

  As shown in FIG. 13, contact windows 42 to 45 are formed. The contact window 42 of the counter electrode 40, the contact window 43 of the peripheral circuit wiring layer made of the silicon film 32 and the WSi film 33, and the contact window 44 of the peripheral circuit wiring layer made of the silicon film 19 and the WSi film 20 are contacted. The window 45 is a contact window for the diffusion layer 25 of the MOS transistor in the peripheral circuit.

  Since the BPSG film 41 is flattened, irregularities can be suppressed within the depth of focus of the exposure apparatus in the resist exposure step, and a reduction in dimensional accuracy can be suppressed. The contact windows 42 to 45 are preferably opened in a single photolithography process because the process is shortened. However, since the contact windows have greatly different depths, the contact window 45 of the lowermost diffusion layer 25 is formed. In the meantime, the contact window 42 of the uppermost counter electrode 40 penetrates and may short-circuit with the lower wiring layer in some cases.

  In such a case, the window opening process of the contact windows 42 to 45 is divided into a contact window on the counter electrode and a contact window on another conductive layer, This is done in two separate contact windows on the silicon substrate. By separating the deep contact window and the shallow contact window into a plurality of times and performing the window opening process, it is possible to eliminate the adverse effects such as the contact window penetrating the conductive layer by the etching process.

  As shown in FIG. 14, a titanium film (Ti) is formed by a sputtering method, a titanium nitride film (Tin) is formed by a reactive sputtering method, and a tungsten film (W) is formed by a CVD method in sequence. A wiring layer 46 is formed. The first metal wiring layer 46 is arranged in the cell region in a direction parallel to the word line, and is mainly used for wiring connecting the word decoder and the sub word decoder.

  Thereafter, although not shown, an interlayer insulating film is grown on the first metal wiring layer 46, and is planarized by CMP. After a contact window is formed on the first metal wiring layer 46, a second metal wiring layer is formed and patterned. As the second metal wiring layer, for example, a laminate composed of a TiN film, an aluminum film (Al), and a TiN film can be used.

  In the cell region, the second metal wiring layer is arranged in a direction parallel to the bit line, and is mainly used for wiring connecting the column decoder and the sense amplifier. The second metal wiring layer is also used as a bonding pad. Finally, a silicon oxide film and a silicon nitride film are sequentially formed as a passivation film by plasma CVD, and the passivation film on the bonding pad is removed by etching to complete the DRAM.

  According to the present embodiment, the polycide electrode forming the word line, the gate electrode, the bit line or the wiring layer of the peripheral circuit is covered with the nitride film spacer, but the oxide film is formed on the side wall of the polycide electrode. Therefore, it is possible to prevent the polycide electrode from being peeled off from the substrate by a heat treatment in a later step. Moreover, since the entire area of the polycide gate electrode is covered with a nitride film and the oxide film is not exposed, it is not removed by etching when forming the self-aligned contact window. There is no such thing as a short circuit.

  Note that the thicker the oxide film 22 formed beside the gate electrode is, the stronger the peeling of the silicide film is. However, when the oxide film 22 is formed by the thermal oxidation method, the substrate is also oxidized at the same time, and a region thicker than the gate oxide film called a gate bird's beak is formed at the lower end of the gate electrode. Since there is a possibility of deteriorating the characteristics of the MOS transistor, it is preferable to determine the film thickness in consideration of these.

As shown in FIG. 1A, in the first embodiment, an example in which an oxide film is provided only on the side wall portion of the polycide electrode is shown.
[Second Embodiment]
As shown in FIG. 1B, a configuration in which the polycide electrode is covered with an oxide film will be described as a second embodiment with reference to FIGS. 15 and 16 are schematic cross-sectional views of a wiring structure as a typical example of the peripheral circuit portion of the AA ′ portion of FIG. 2 for the memory cell portion and the first embodiment. It is the same as the form.

  FIG. 15 shows an example in which the configuration shown in FIG. 1B is used for a gate electrode or a word line (corresponding to 12 in FIG. 1) of a cell portion. A field oxide film 17 is formed on the p-type silicon substrate 16 by the same method as described with reference to FIG.

  As shown in FIG. 15A, the substrate surface is oxidized to form a gate oxide film 18 having a thickness of 8 nm, and a phosphorus-doped silicon film 19 and a WSi film 20 having a thickness of 50 nm are sequentially formed by a CVD method. .

  Subsequently, an oxide film 47 is formed to 3 to 50 nm. The formation method may be either a thermal oxidation method or a CVD method, but it is preferable to use the thermal oxidation method because a structure resistant to peeling can be obtained. In addition, if the oxide film is formed by the thermal oxidation method, the thickness of the polycide film becomes thin. Therefore, after forming the oxide film thinly by the thermal oxidation method, the oxide film is formed by the CVD method to have a desired thickness. This method is also effective.

  Subsequently, after a silicon nitride film 21 is formed to a thickness of 80 nm by using the CVD method, these stacked bodies are patterned to become gate electrodes and wiring layers. Unlike the first embodiment, a laminate including the silicon film 19, the WSi film 20, the oxide film 47, and the silicon nitride film 21 is formed.

As shown in FIG. 15B, when an oxide film is grown by thermal oxidation to 2 to 10 nm, an oxide film is formed on the side walls of the polycide structure silicon film 19 and the WSi film 20 and integrated with the oxide film 47. An oxide film region 48 can be formed.

Subsequently, as in the first embodiment, using the gate electrode as a mask, phosphorus, which is an n-type impurity, is ion-implanted into the entire surface of the substrate at a dose of 1 × 10 ¹³ cm ⁻² to form an n-channel MOS transistor region. Then, an LDD (impurity diffusion layer 23 corresponding to the n ⁻ layer of the structure is formed. Subsequently, a silicon nitride film is formed to a thickness of 50 to 150 nm by a CVD method, and then is anisotropically etched to form a nitride film region 24. Is formed so as to cover oxide film region 48.

  Thereafter, the same process as in the first embodiment is taken to create a DRAM. According to the present embodiment, since the oxide film is formed not only on the side walls of the silicon film 19 and the WSi film 20, but also on the upper surface of the WSi film 20, the polycide electrode does not directly contact the silicon nitride film. Therefore, a stronger structure can be obtained against the peeling of the WSi film.

  FIG. 16 shows an example in which the invention described in FIG. 1B is used for a bit line (corresponding to 13 in FIG. 1) in the cell portion. The silicon oxide film 30 is formed on the flattened BPSG film 26 by performing the same process as in FIG. 5B of the first embodiment.

  As shown in FIG. 16A, a resist pattern having an opening in the bit line connection region is formed, and the oxide film 30 is etched using the resist pattern as a mask so that a part of the upper surface of the silicon film plug 29 is exposed. After the contact window 31 is formed, the resist is removed.

  Subsequently, a silicon film 32 doped with phosphorus is formed with a thickness of 30 nm and a WSi film 33 is formed with a thickness of 50 nm by a CVD method, and then an oxide film 49 is formed with a thickness of 3 to 50 nm. The formation method and configuration are the same as those shown in the example used for the word line. Subsequently, after the silicon nitride film 21 is formed to a thickness of 80 nm by using the CVD method, these stacked bodies are patterned to become bit lines and wiring layers.

  As shown in FIG. 16B, an oxide film is grown by 2 to 10 nm by thermal oxidation, an oxide film is formed on the side walls of the polycide structure silicon film 32 and the WSi film 33, and integrated with the oxide film 49. An oxide film region 50 is formed. Subsequently, a silicon nitride film having a thickness of 50 to 150 nm is formed by CVD and anisotropically etched to form the nitride film region 36 so as to cover the oxide film region 48.

  Thereafter, the same process as in the first embodiment is taken to create a DRAM. In this case as well, the oxide film is formed not only on the side walls of the silicon film 32 and the WSi film 33 but also on the upper surface of the WSi film 33, so that the polycide electrode is directly formed on the silicon nitride film. There is no contact. Therefore, a stronger structure can be obtained against the peeling of the WSi film.

  In the above description, the case where the SAC structure is used for each of the word line and the bit line in the cell portion has been described. However, the SAC structure may be used separately, or two may be combined and applied to both the word line and the bit line. It goes without saying that it doesn't matter. In this embodiment, the thicker the oxide film covering the gate electrode, the stronger the structure against the peeling of the silicide film. However, as described above, when the oxide film is formed by the thermal oxidation method, the gate electrode If an attempt is made to increase the thickness of the sidewall, the characteristics of the MOS transistor are deteriorated, so that the sidewall cannot be made too thick. Therefore, by making the oxide film thickness on the top surface of the gate electrode thicker than the film thickness on the side wall of the gate electrode, it is possible to make the structure strong against peeling without deteriorating the characteristics of the MOS transistor.

[Third Embodiment]
A third embodiment will be described with reference to schematic sectional views of FIGS. As in the first and second embodiments, the memory cell portion is a schematic cross-sectional view of a wiring structure as a typical example of the AA ′ portion of FIG. 1 and the peripheral circuit portion is a typical example.

The process up to the step of FIG. 4B is performed in the same manner as in the first embodiment to form a polycide electrode, a nitride film region 24, and the like, which become a word electrode and a gate electrode.
As shown in FIG. 17A, after the BPSG film 26 is grown to a thickness of 100 to 200 nm by a CVD method, heat treatment is performed at a temperature of 750 to 900 ° C., and the surface is planarized by reflow. Further, the etch back method or the CMP method may be used for planarization, as in the first embodiment. Subsequently, a silicon nitride film 51 is grown by 10 to 50 nm on the planarized BPSG film 26 by a CVD method.

  As shown in FIG. 17B, a resist pattern having an opening exposing the source / drain region of the MOS transistor in the cell region is formed, and the nitride film 51, the BPSG film 26, and the oxide film 22 are sequentially etched to form the substrate surface. The contact window 27 is formed by exposing.

Etching of the nitride film 51 is performed using CF ₄ gas by the RIE method. When the surface of the BPSG film 26 is exposed, the gas is changed to a mixed gas of C ₄ F ₈ and CO, and the nitride film is also selected by the RIE method. The BPSG film is etched under conditions with a large ratio. This is to prevent the nitride film region 24 from being etched, and it is preferable that the selection ratio with the nitride film is 10 or more.

Also in this embodiment, the contact window 27 is defined in a self-aligned manner by the spacer portion of the nitride film region 24, and the entire area of the polycide gate electrode is covered with the nitride film so that the oxide film is exposed. Therefore, even if the opening of the resist is displaced, the spacer is not removed by etching, and the gate electrode and the contact electrode as described in the conventional examples of FIGS. 35 to 37 are short-circuited. There is no such thing. Subsequently, as in the first embodiment, after removing the resist, 3 × 10 ¹³ phosphorus, which is an n-type impurity, is added into the silicon substrate of the contact window 27 using the BPSG film 26 and the nitride film region 24 as a mask. Ions are implanted at a dose of cm ⁻² to form the n-type diffusion layer 28.

  As shown in FIG. 18A, after a silicon film doped with phosphorus is formed on the entire surface by the CVD method, the plug 29 of the silicon film is left in the contact window 27 by using an etch back method or a CMP method.

  Alternatively, the silicon film plug 27 may be formed by using a selective CVD method without using the etch back method or the CMP method. Subsequently, a silicon oxide film 30 is grown by 30 to 100 nm by a CVD method.

  As shown in FIG. 18B, a resist pattern having an opening in the bit line connection region is formed, and the oxide film 30 is etched using the resist pattern as a mask so that a part of the upper surface of the silicon film plug 29 is exposed. After the contact window 31 is formed, the resist pattern is removed.

  Subsequently, a silicon film 32 doped with phosphorus, 30 nm, a WSi film 33 of 50 nm, and a silicon nitride film 34 of 80 nm are sequentially formed by CVD. These laminates are patterned into a desired wiring pattern using a known photolithography method. The polycide electrode of these laminates becomes a bit line (corresponding to 13 in FIG. 1) in the cell portion and is also used as a wiring layer other than the bit line in the peripheral circuit portion.

  As shown in FIG. 19, after a BPSG film 37 is grown to a thickness of 500 nm by a CVD method, heat treatment is performed at a temperature of 750 to 900 ° C., and the surface is planarized by reflow. Further, in order to perform planarization, an etch back method or a CMP method may be used, or a combination of these methods may be used for planarization, as in the first embodiment.

Subsequently, a resist pattern having an opening exposing the capacitor connection region is formed. Using the resist pattern as a mask, the BPSG film 37 and the oxide film 30 in the opening are sequentially formed by, for example, a RIE method using a mixed gas of C ₄ F ₈ and CO. Etching is performed to form a contact window 38 that exposes the upper surface of the silicon film plug 29. At this time, since the entire periphery of the polycide gate electrode is covered with the nitride film region 36, the polycide gate electrode is not removed by etching, and the bit line and the storage electrode are not short-circuited.

  Further, in the first embodiment, as shown in FIG. 8, since the BPSG film 26 exists under the oxide film 30, the BPSG film 37 and the oxide film 30 are etched to open the contact window 38. Then, there is a risk that the BPSG film 26 is etched and a groove is formed on the side of the plug 29 in the capacitor connection region. For this reason, since the shape of the storage electrode formed on the trench changes and the area changes, the capacitor capacitance changes, and stable element characteristics may not be obtained.

  On the other hand, in the present embodiment, the nitride film 51 exists under the oxide film 30, and when the BPSG film 37 and the oxide film 30 are etched at the contact portion of the storage electrode, the nitride film 51 is formed. Since it functions as a stopper, no groove is formed on the side of the plug 29 in the capacitor connection region. Therefore, a stable capacity can be maintained, which is useful for increasing the yield of DRAM.

  As shown in FIG. 20, after removing the resist, a silicon film doped with phosphorus is formed to 50 nm by the CVD method, and the silicon film 39 is formed only on the side wall and the bottom surface in the contact window 38 using the etch back method or the CMP method. Remain. Subsequently, using a hydrofluoric acid-based etchant, the BPSG film 37 is entirely etched away using the nitride film 51 as an etching stopper, thereby forming a cylindrical storage electrode 39 in which the interior is hollowed out.

  In the first embodiment, as shown in FIG. 9, after the silicon film 39 is left only on the side wall and the bottom surface in the contact window 38, a hydrofluoric acid based etchant is used as shown in FIG. The BPSG film was subjected to control etching to form a columnar storage electrode 39 in which the inside was hollowed out. In the present embodiment, the nitride film 51 can be used as an etching stopper, and the BPSG film 37 outside the silicon film 39 can be completely removed with a hydrofluoric acid-based etchant. Therefore, the etching amount of the BPSG film 37 does not vary, and the area outside the cylinder-type storage electrode can be made constant, so that the variation in the capacitor capacity is small and a stable DRAM cell can be manufactured. Become.

As shown in FIG. 21, a capacitor insulating film is formed on the surface of the storage electrode 37 by forming a silicon nitride film with a thickness of 40 nm by CVD and thermally oxidizing the film with a thickness of 1 to 2 nm. (The capacitor insulating film is not shown in the figure.)
Subsequently, after forming a silicon film doped with phosphorus by CVD to a thickness of 50 nm, patterning is performed to form the counter electrode 40 of the capacitor. Subsequently, the capacitor insulating film and the silicon nitride film 51 are simultaneously etched away in accordance with the pattern of the counter electrode 40.

  At this time, the silicon nitride film 51 may be left. However, if the silicon nitride film is present in the peripheral circuit portion, a step of opening a contact window with respect to the diffusion layer of the peripheral circuit in a later step is performed in the oxide film and the silicon nitride. Since both of the films are complicated to be etched, the silicon nitride film becomes eaves due to the difference in etching characteristics at the contact window, and the metal wiring layer formed in the contact window may be broken. It is better to keep it.

  Further, when the silicon nitride film 51 is etched, the silicon nitride film region 36 around the wiring layer in the peripheral circuit portion formed simultaneously with the bit line in the cell portion is also etched at the same time, so that the silicon nitride film region 36 is formed. The film thickness of the silicon nitride film 34 on the WSi film 33 is preferably set larger than the film thickness of the silicon nitride film 51.

  The subsequent steps are the same as those in the first embodiment, and a DRAM can be formed by opening a contact window or forming a metal wiring layer. In the present embodiment, compared to the first embodiment, since there is the nitride film 51 that functions as an etching stopper layer, the area can be made constant during the formation of the storage electrode contact and the storage electrode, Since a stable capacity can be maintained, it is useful for increasing the yield of DRAM.

As another effect, an effect of stably opening the contact window of the bit line can be expected. Hereinafter, this point will be described with reference to FIGS.
22 and 23 are schematic cross-sectional views of the cell section cut along AA 'in FIG. 1, and show a case where the contact window 31 formed in FIG. 18B is displaced. 22 corresponds to the first embodiment in which the silicon nitride film 51 is not provided under the oxide film 30, and FIG. 23 corresponds to the third embodiment in which the silicon nitride film 51 is provided under the oxide film 30. Equivalent to.

  As shown in FIG. 22, according to the process corresponding to the first embodiment, when the contact window 31 is opened in a shifted position, the BPSG film 26 is also etched by etching the oxide film 30, and the silicon film A groove is dug in the side of the plug 29. There is a risk that the upper bit line is broken due to this groove, the groove is not filled and remains as a void, or the plug 29 is short-circuited by the wiring layer remaining in the groove. There is.

  On the other hand, as shown in FIG. 23, according to the present embodiment, even when the contact window 31 is opened in a shifted position, the nitride film 51 serves as a stopper, so that the BPSG film 26 is etched. There is no danger, and no groove is dug in the side of the plug 29 of the silicon film, so the above-mentioned adverse effects do not occur. Further, the nitride film stopper 49 can be used positively to make the size of the contact window 31 larger than that of the plug 29 of the silicon film, and the margin of the contact window opening process can be increased.

[Fourth Embodiment]
A fourth embodiment will be described with reference to schematic sectional views of FIGS. As in the first and second embodiments, the memory cell portion is a schematic cross-sectional view of a wiring structure as a typical example of the AA ′ portion of FIG. 1 and the peripheral circuit portion is a typical example.

  The process up to the step of FIG. 6B is performed in the same manner as in the first embodiment, and a polycide electrode, silicon, which becomes a wiring layer in the bit line and the peripheral portion, is formed on the word line and the peripheral MOS transistor. A nitride film region 36 and the like are formed.

As shown in FIG. 24, after a BPSG film 52 is grown on the entire surface by a CVD method, heat treatment is performed at a temperature of 750 to 900 ° C. and reflow is performed to flatten the surface.
Further, in order to perform planarization, an etch back method or a CMP method may be used, or planarization may be performed by combining these. Subsequently, a silicon nitride film 53 and a BPSG film 54 are sequentially grown by the CVD method. Here, the film thickness of the BPSG films 52 and 54 is set to 500 nm in total, and the silicon nitride film 53 is set to 10 to 50 nm.

  Note that the thickness of the BPSG film 52 is necessary to the extent that it can be flattened, and the thickness of the BPSG film 54 defines the area of the outer surface of the cylinder-type storage electrode that is directly related to the capacity. It is necessary to choose by. Accordingly, the film thickness ratio of the BPSG films 50 and 52 and the total film thickness may be appropriately selected in consideration of these.

As shown in FIG. 25, a resist pattern having an opening exposing the capacitor connection region is formed, and the BPSG film 54 in the opening is etched by the RIE method using a mixed gas of C ₄ F ₈ and CO using the resist pattern as a mask. Subsequently, the nitride film 53 is etched by RIE using CF ₄ gas, and then the BPSG film 52 and the oxide film 30 are sequentially etched again by RIE using a mixed gas of C ₄ F ₈ and CO to form silicon. A contact window 38 is formed so that the upper surface of the membrane plug 29 is exposed.

  As shown in FIG. 26, after removing the resist, a silicon film doped with phosphorus is formed to a thickness of 50 nm by the CVD method, and then the silicon film 39 is formed only on the side wall and the bottom surface in the contact window 38 using the etch back method or the CMP method. To remain.

  As shown in FIG. 27, the BPSG film 54 outside the silicon film 39 is removed using a hydrofluoric acid-based etchant. Since the nitride film 53 functions as an etching stopper, only the BPSG film 54 can be removed. In this process, a cylindrical storage electrode 39 is formed in which the interior is hollowed out.

  Also in the present embodiment, as in the third embodiment, all the BPSG film 54 outside the cylinder-type storage electrode 39 can be removed. Therefore, since the area outside the cylinder-type storage electrode can be made constant, variation in capacitor capacity is small, and a stable DRAM cell can be manufactured.

As shown in FIG. 28, a silicon nitride film having a thickness of 40 nm is formed by a CVD method and thermally oxidized by 1 to 2 nm, thereby forming a capacitor insulating film on the surface of the storage electrode 39. (The capacitor insulation film is not shown in the figure)
Subsequently, after forming a silicon film doped with phosphorus by CVD with a thickness of 50 nm, the counter electrode 40 of the capacitor is formed by patterning. Subsequently, the capacitor insulating film and the silicon nitride film 53 are also removed in accordance with the pattern of the counter electrode 40.

  At this time, the silicon nitride film 53 may be left. However, if the silicon nitride film exists in the peripheral circuit portion, a step of opening a contact window with the diffusion layer in a later process causes both the oxide film and the silicon nitride film to be removed. Etching is complicated, and due to the difference in etching characteristics at the contact window, the silicon nitride film becomes eaves and the metal wiring layer formed in the contact window may be broken. This is more preferable as in the third embodiment.

  Subsequent processes are similar to those in the first embodiment, and a contact window is formed and a metal wiring layer is formed, whereby a DRAM can be formed. In the present embodiment, only the BPSG film 54 outside the cylinder storage electrode 39 can be removed. Therefore, since the area outside the cylinder-type storage electrode can be made constant, variation in capacitor capacity is small, and a stable DRAM cell can be manufactured.

  As shown in FIG. 11 of the first embodiment, after the capacitor counter electrode 40 is formed, the insulating film is completely planarized. Needless to say, the smaller the difference in height between the cell portion and the peripheral circuit portion as in the present embodiment, the easier the flattening in the subsequent process. That is, according to the present embodiment, the process is designed in consideration of both the effect of obtaining a stable capacitance and the effect of facilitating flattening by reducing the height difference between the memory cell portion and the peripheral circuit portion. Therefore, it is possible to manufacture a DRAM having stable characteristics.

  Since the nitride film 53 is removed at the same time when the counter electrode 38 is etched, the problem caused by the presence of the silicon nitride film in the peripheral circuit portion is the same as described in the third embodiment. Can be avoided. At this time, in the present embodiment, unlike the third embodiment, since the BPSG film 52 exists under the silicon nitride film 53, the silicon nitride film 53 can be etched using this as an etching stopper, and the cell portion It is also possible to obtain an effect that the silicon nitride film region 36 around the wiring layer of the peripheral circuit portion corresponding to the bit line is not etched.

[Fifth Embodiment]
A fifth embodiment will be described with reference to FIGS. 29 and 30. FIG. The present embodiment relates to a method of forming contact windows 42 to 45 with the first metal wiring layer shown in FIG. 13 of the first embodiment.

FIG. 29 shows a state in which, after the counter electrode 40 is formed, a BPSG film is formed and flattened according to the third embodiment, and contact windows 42 to 45 are formed along the present embodiment. First, in the step of opening the contact windows 42 to 45, as a first step, the BPSG film 41 is etched under a condition that the selection ratio with the nitride film is sufficiently large. For this etching, a mixed gas of C ₄ F ₈ and CO used for forming the nitride film SAC structure may be used.

  The etching in the first step is performed until the surface of the lowermost diffusion layer 25 is exposed. At this time, the uppermost counter electrode 40 is etched and removed. However, since the nitride film 51 exists under the counter electrode, the etching stops here, and the BPSG film 26 underneath is etched. There is no. Further, the etching of the contact windows 43 and 44 is also stopped at the nitride film regions 36 and 24, respectively.

Subsequently, as the etching of the second step, using a mixed gas of CHF ₃ and O _2, to etch the silicon nitride film is greater conditions of the oxide film and the selectivity. As a result, the nitride film regions 36 and 25 at the bottoms of the contact windows 43 and 44 can be removed to make contact. Although the nitride film 51 under the counter electrode 40 is also etched by this nitride film etching, the etching stops at the lower BPSG film 26, so that the counter electrode 40 is connected to the lower wiring layer at the contact window 42. There is no worry of shorting. Even in such a contact window structure, the first metal wiring layer formed in the contact window is electrically connected by the side wall of the counter electrode 40, so there is no problem.

  FIG. 30 shows a state in which, after the counter electrode 40 is formed and then the BPSG film is formed and planarized according to the fourth embodiment, and the contact windows 42 to 45 are formed along the present embodiment. 30 also has the nitride film 53 and the BPSG film 52 under the counter electrode 40 as in FIG. 29, so that the above-described two-step etching can be applied without causing a problem such as a short circuit with the lower layer wiring. The contact windows 42 to 45 can be formed by a single photolithography process.

  According to this embodiment, even if the contact window has a different depth, the window can be opened by a single photolithography process, and the process can be shortened. If a nitride film is not formed on the bottom surface of the contact window 41 or 42 and the surface of the wiring layer or the gate electrode can be exposed in the first step, it is necessary to perform the nitride film etching in the second step. Absent.

  Further, the method for forming the contact window described in this embodiment is not limited to the above embodiment, and a nitride film is provided below the upper wiring layer in a plurality of wiring layers, and the nitride film is a stopper. It goes without saying that the same effect can be obtained by etching. However, if used in the form according to the present embodiment, not only the effects of the present embodiment but also the effects described in the third embodiment and the fourth embodiment can be achieved. Therefore, it is advantageous.

[Sixth Embodiment]
A sixth embodiment will be described with reference to the schematic cross-sectional view of FIG.
In FIG. 5A of the first embodiment, the BPSG film 24 is planarized by reflow, etch back method, or CMP method. In this embodiment, as shown in FIG. 31, the BPSG film 26 formed on the gate electrode and the word line is planarized using the CMP method, and the silicon nitride film region 24 is used as the stopper layer.

  The distance from the substrate of the silicon nitride film region 24 that covers the periphery of the polycide electrode differs depending on whether it is on the active layer as a gate electrode or on the field oxide film 17 as a wiring layer. Only the higher nitride spacer is used as a stopper layer, and the BPSG film 26 remains on the lower nitride spacer.

  At this time, by using, for example, a silica-based abrasive as the abrasive, it is possible to polish the BPSG film with a high etching selectivity with respect to the silicon nitride film. This stopper layer can not only flatten the BPSG film 26 but also reduce variations in film thickness.

  If the thickness of the flattened BPSG varies, a distribution occurs in the etching amount when forming a contact window in a later process. In order to secure contact, all of the BPSG film in the contact window must be removed by etching, so that the amount of overetching of the BPSG film must be increased. Therefore, when the nitride film spacer SAC is used, the film thickness of the nitride film spacer is reduced by this overetching, and the risk of shorting between the polycide electrode and the upper layer wiring is increased. is important.

  In the present embodiment, a layer serving as a stopper is not bothered to be formed, but the nitride film region 24 necessary for using the nitride film spacer SAC can be used as it is, resulting in an increase in new processes. There is no. Further, after planarization by CMP, a BPSG film may be further formed to increase the interlayer film thickness to reduce the parasitic capacitance, or as shown in the third embodiment, silicon silicon may be used. The contact window forming step may be performed after forming the nitride film.

  Note that since the film thickness of the BPSG film 26 affects the parasitic capacitance of the bit line formed in the upper layer, the variation in the bit line capacitance can be reduced by reducing the film thickness variation by the method of this embodiment. It is possible to increase the stability of the operation of the DRAM. Further, in this embodiment, only the nitride film spacer on the field insulating film used as the word line or wiring layer is used as the stopper layer, and the nitride film spacer on the active layer used as the gate electrode is used as the stopper. The role is not given.

  Therefore, when the BPSG film is planarized by the CMP method, the nitride film spacer on the active layer is not polished and the film thickness does not decrease. In the nitride spacer SAC, the contact window is formed by self-alignment using the nitride spacer as a mask. Of course, this contact window is not formed on the field insulating film but formed on the diffusion layer in the active layer region. Therefore, the nitride film spacer SAC process can be used as a mask with a nitride film whose thickness is not reduced by planarization by the CMP method. Therefore, in this embodiment, controllability is achieved by the CMP method using the stopper layer. An effect of preventing a short circuit between the polycide electrode and the upper wiring layer can be obtained by forming a contact window by the nitride film spacer SAC while performing good planarization.

As described above, according to the present embodiment, it is possible to obtain the effects of improving the product yield and increasing the operation stability without increasing the number of steps.
[Seventh Embodiment]
A seventh embodiment will be described with reference to the schematic cross-sectional view of FIG. In this embodiment mode, the technique shown in the sixth embodiment mode is used for a planarization step on a conductive layer that becomes a bit line.

  In FIG. 7 of the first embodiment, the BPSG film 37 is planarized by reflow, etch back method or CMP method. In the present embodiment, as shown in FIG. 32, the BPSG film 37 formed on the bit line is planarized using the CMP method, and the silicon nitride film region 36 is used as a stopper layer.

  At this time, it is possible to polish the BPSG film in a state where the etching selectivity with respect to the silicon nitride film is increased by using, for example, a silica-based polishing agent. Same as described in The stopper layer can not only flatten the BPSG film 37 but also reduce variations in film thickness.

  If the thickness of the flattened BPSG varies, there is a risk that the etching amount at the time of forming the contact window in the subsequent process is distributed, the nitride film region 36 is reduced, and the polycide electrode and the upper storage electrode are short-circuited. In order to increase, the point that the stability of the BPSG film thickness is particularly important is the same as that described in the sixth embodiment. Also in this embodiment, the nitride film region 36, which is necessary for using the nitride film spacer SAC, can be used as it is instead of forming the stopper layer. There is no invitation.

  Since the thickness of the BPSG film 37 affects the area of the storage electrode and affects the capacitor capacity, after the planarization by CMP, a BPSG film is further formed to obtain a desired capacity. The thickness may be set, or as shown in the fourth embodiment, a nitride film may be formed between two BPSG films.

[Eighth Embodiment]
With reference to the schematic cross-sectional view of FIG. 33, an eighth embodiment will be described.
In FIG. 5A of the first embodiment, an n-type diffusion layer 26 is formed to reduce junction leakage. In the present embodiment, as shown in FIG. 33, in order to form n-type diffusion layer 28 only in the source / drain region on the capacitor side of the memory cell portion, the source / drain region on the side to which the bit line is connected is resisted. Then, phosphorus, which is an n-type impurity, is ion-implanted into the silicon substrate of the contact window 27 at a dose of 3 × 10 ¹³ cm ^{−2 using} the BPSG film 26 and the nitride film region 24 as a mask.

  As described in the first embodiment, the n-type diffusion layer 28 can prevent the problem of increased junction leakage. On the other hand, however, this ion implantation increases the junction depth of the source / drain, which causes problems such as adversely affecting the short channel effect of the transistor and increasing the leakage current between the elements. The diffusion layer on the capacitor side that stores minute charges is required to have a sufficiently low junction leakage, whereas the diffusion layer on the side to which the bit line is connected is not so severe with respect to the junction leakage.

  Therefore, in the present embodiment, by performing the ion implantation only on the side to which the capacitor is connected, one of the source / drain of the MOS transistor can have a shallow junction depth, and the short channel effect of the transistor can be reduced. It is possible to suppress adverse effects on the leakage current between elements.

  Although the present invention has been described according to the first to eighth embodiments, the present invention is not limited to the above embodiments. Needless to say, the present invention can be widely applied to processes having the same technical idea as the above-described processes.

  In the above description, WSi is used as the polycide electrode, but other silicides such as MoSi and TiSi may be used. Further, not only silicide but also metal or metal compound such as tungsten (W), molybdenum (Mo), titanium nitride (TiN), titanium tungsten (TiW) can be used. In the case of a metal or a metal compound, it is difficult to form an oxide film by a thermal oxidation method. Therefore, an oxide film by a CVD method or the like may be used.

  In the above description, an example of the silicon oxide film is described as the insulating film provided between the nitride film, but other insulating films can be used as long as the stress of the silicon nitride film can be relieved. In particular, the use of a silicon oxynitride film (SiON) film is preferable because it can be used as an antireflection film on the silicide film, which shortens the process. Further, although an example of BPSG is shown as the interlayer insulating film, PSG, silicon oxide film, or the like can also be used.

  In addition, although an example of using isotropic etching by wet etching and anisotropic etching by RIE as an etching method has been shown, other etching methods such as other isotropic plasma etching methods and etching methods using ECR are shown. Can also be used as appropriate according to the application. Moreover, although the example of the silicon film which doped phosphorus as the plug formed in a contact window was shown, if it forms on a p-type diffused layer or a p-type silicon layer, the silicon film doped with p-type impurities, such as boron, is used. Use it. The plug is not limited to a silicon film, and may be a metal such as W or TiW, a metal compound, or a metal silicide.

Further, although an example in which the nitride film is oxidized as the capacitor insulating film has been shown, a tantalum oxide film (Ta ₂ O ₅ ), a high dielectric film such as PZT, a ferroelectric film, or the like can be used. In that case, it is preferable to use a metal for the storage electrode and the counter electrode because it is possible to prevent a reduction in capacitance due to a natural oxide film of the electrode and a reaction between the capacitor insulating film and the silicon film.

  Further, polysilicon or amorphous silicon may be used as the silicon film, and the impurity doping may be performed simultaneously with the growth of the film, or may be performed by using a diffusion method or an ion implantation method after the growth. . In the embodiment, the manufacturing method of the cylinder type capacitor is shown as an example, but it goes without saying that the method may be applied to other capacitor structures such as a stack type and a FIN type.

4, 19, 114 Silicon film 5, 20, 115 Silicide film 6, 22 Silicon oxide film 7, 23, 116 n ^- type impurity diffusion layer 8, 24, 117 Silicon nitride film region 9, 26, 118 BPSG film 10, 27 119 Contact window 25 n ⁺ -type impurity diffusion layer 28 n-type impurity diffusion layer 31 Contact window 32 Silicon film 33 Silicide film 34 Silicon nitride film 35 Silicon oxide film 36 Silicon nitride film region 38 Contact window 39 Cylinder storage electrode 40 Opposite capacitor Electrode 41 BPSG film 42, 43, 44, 45 Contact window 48, 50 Silicon oxide film region 51, 53 Silicon nitride film 52, 54 BPSG film 123 Silicon oxide film 124 Silicon nitride film

Claims (5)

Forming a gate insulating film and a gate electrode on a base plate,
Forming an impurity diffusion region in said substrate a pre Symbol gate electrode as the mask,
Forming a first insulating film covering the front Symbol gate electrode and the impurity diffusion region,
Etching the previous SL first insulating film, forming a first contact window to the impurity diffusion layer region,
Before SL first contact the window, and forming a first contact plug electrically connected to the impurity diffusion layer region,
Forming a first conductive pattern on the first insulating film;
Forming a first silicon nitride film on the top surface of the first conductive pattern;
Forming a second insulating film having different etching characteristics from the previous SL covering the first insulating film and the first silicon nitride film, the first silicon nitride film,
Forming a second silicon nitride films having different etching characteristics from the previous SL on the second insulating film, said second insulating film,
Previous SL second silicon nitride film and the second insulating film is etched, and forming a second contact window reaching said first contact plug,
Forming a accumulation electrodes inside the front Stories second contact window,
A step of forming the capacitor insulating film, forming a pair counter electrode on the capacitor insulating film over the prior SL storage electrode and the second insulating film,
The pre-Symbol counter electrode as a mask, removing the capacitor insulating film and the second silicon nitride film,
After the step of removing the pre-Symbol second silicon nitride film, and forming a third insulating film so as to cover the opposing electrodes,
The third insulating film, by etching the second insulating film and the first silicon nitride film, the first conductive third contact window reaching the conductive pattern is formed, the second insulating film Etching the third insulating film, the counter electrode, and the second silicon nitride film as an etching stopper to form a fourth contact window;
Before Symbol third contact in the window, the second contact plug formed which is electrically connected to the first conductive pattern, the fourth contact in the window, which is electrically connected to the counter electrode Forming a third contact plug ;
Have
End of the previous SL second silicon nitride film has a contact with the third contact window
The method of manufacturing a semiconductor device comprising a call. A step of forming a fourth insulating film between the first insulating film and the second insulating film;
Manufacturing method of the preceding Symbol second contact windows according to claim 1 Symbol mounting a semiconductor device, characterized in that it is formed so as to reach into the fourth insulating film penetrates the second insulating film. Bottom portion of the accumulation electrode, method of manufacturing a semiconductor device according to claim 2, characterized in that it is formed in a portion of the fourth insulating film of the second contact window. Further comprising a step of forming an element isolation region on the base plate,
The method of manufacturing a semiconductor device before Symbol second end portion of the silicon nitride film according to any one of claims 1 to 3, characterized in that it is formed on the element isolation region. Before Stories second insulating film is a silicon oxide film, the third insulating film is a method of manufacturing a semiconductor device of any one of claims 1 to 4, characterized in that a silicon oxide film.

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