JPH11312804A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, in which the short circuit generating between a gate electrode and a source or drain region in connection hole can be prevented when a wiring is formed, even when positional deviation is generated on the connection hole formed on an interlayer insulating film, and to provide a manufacturing method of the semiconductor device. SOLUTION: A polycrystalline Si film and an offset insulating film are formed on a semiconductor substrate 1 via a gate insulating film 4, and a gate electrode 5 is formed by patterning. After the formation of an SiN film 10 on the entire surface of the substrate, the SiN film 10 is etched back and the SiN film is left in sidewall-like form on the sidewall of the gate electrode and the offset insulating film. After the insulating film has been removed, n-type impurities are ion-implanted, an n<+> -type source region 12 and a drain region 13 are formed, and the gate electrode 5 is formed into n<+> -type. Then, after the formation of a Co film on the entire surface of the substrate, the Co film is heat-treated, silicified, and CoSi films 15, 16 and 17 are formed on the gate electrode, and the source and the drain regions. After an SiN film 18 has been formed on the entire surface of the substrate, the film 18 is etched back, and the SiN film is left on the upper inside surface of the gate electrode of the sidewall-like SiN film and the outside surface of the SiN film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a MIS field effect transistor (MISFET).

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device using a MOSFET, the gate length of a transistor is shortened and the resistance at the time of driving is decreasing year by year as the elements are miniaturized.
However, due to the increase of the contact resistance of the wiring due to the reduction of the diameter of the contact hole and the shallow junction of the diffusion layer,
The parasitic resistance tends to increase, and the reduction in current driving capability due to the parasitic resistance has become a serious problem year by year. As one of the methods to reduce such parasitic resistance,
After a sidewall made of silicon oxide (SiO ₂ ) is formed on the side surface of a gate electrode made of polycrystalline silicon (Si), a refractory metal film is formed on the entire surface of the substrate, and heat treatment is performed to form the refractory metal film and the gate. A refractory metal silicide film is formed on the gate electrode, the source region, and the drain region by alloying the electrode and the underlying Si substrate, and then the unreacted refractory metal film is removed by etching. Self-aligned silicide (SALIDE) leaving only the high melting point metal silicide film on the region and the drain region
Technology was proposed.

In addition, since the distance between the contact hole and the gate electrode cannot be increased due to the miniaturization of the element, an insulating film different from the interlayer insulating film is formed on the upper portion or the side portion of the gate electrode. Preventing the contact hole from contacting or approaching the gate electrode,
Self-aligned Contact (SA)
C) The technology was proposed.

However, in the conventional self-aligned contact technology, an insulating film (offset insulating film) is formed on a polycrystalline Si film in order to secure insulation between a contact hole and a gate electrode. Is patterned into the shape of a gate electrode, sidewalls are formed on these side surfaces, and a silicon nitride (SiN) film is formed on the entire surface of the substrate, so that an etching selection at the time of etching for forming a contact hole in an interlayer insulating film is performed. It was necessary to secure a ratio.

For this reason, in the conventional self-alignment type contact technique, it has not been possible to form a refractory metal silicide film on the gate electrode, the source region and the drain region all at once. So, to solve this problem,
After an insulating film is formed on the polycrystalline Si film, these are patterned into the shape of a gate electrode, sidewalls made of SiN are formed on these side surfaces, and then the insulating film on the gate electrode is removed by etching. By performing a heat treatment for the formation of a high melting point metal film and silicidation,
A method of realizing a self-aligned contact with a sidewall made of SiN itself has been proposed. One example of this method is shown in FIGS.

According to this method, first, as shown in FIG. 14, a groove 102 is formed in a predetermined portion of a p-type Si substrate (or p-well) 101, and SiO ₂ is formed inside the groove 102.
The element isolation region 103 is formed by burying the film. next,
After ion implantation (channel doping) for controlling the threshold voltage is performed in the active region surrounded by the element isolation region 103, a gate insulating film 104 made of a SiO ₂ film is formed on the surface of the active region. Next, a non-doped polycrystalline Si film and phosphorus silicate glass (PS
G) After the films are sequentially formed, the polycrystalline Si film and the PSG film are patterned into a shape of a gate electrode. Thereby, the gate electrode 105 and the gate electrode 10
5 is formed.

[0007] Next, as shown in FIG.
The n ⁻ -type layers 107 and 108 are formed in a self-aligned manner with respect to the gate electrode 105 by ion-implanting n-type impurities into the active region at a low concentration using the mask 05 and the PSG film 106 thereon as a mask. Next, an SiO ₂ film 1 is formed on the entire surface of the substrate.
09 and a SiN film 110 are sequentially formed.

Next, the SiN film 110 and the SiO ₂ film 1
By etching back 09, as shown in FIG. 16, the SiN film 110 is left in a sidewall shape on the side surface of the gate electrode 105 and the PSG film 106 thereabove.

Next, as shown in FIG. 17, a resist 111 is applied sufficiently thick over the entire surface of the substrate.

Next, as shown in FIG.
1 is etched back until the SiN film 110 is exposed.

Next, the resist 111 and the SiN film 11
By performing etching using 0 as a mask, FIG.
As shown in FIG. 7, the PSG film 106 and the SiO ₂ film 109 on both sides thereof are removed by etching. Thus, a structure in which the sidewall-shaped SiN film 110 higher than the gate electrode 105 is formed on the side surface of the gate electrode 105 is obtained.

Next, after removing the resist 111, FIG.
As shown in FIG. 0, after the n-type impurity is ion-implanted at a high concentration over the entire surface of the substrate, a heat treatment is performed to electrically activate the implanted impurity. As a result, n ⁺ -type source region 112 and drain region 113 are formed in the active region in a self-aligned manner with respect to gate electrode 105, and the polycrystalline Si film forming gate electrode 105 is made n ⁺ -type. The resistance is reduced. The source region 112 and the drain region 113 form the sidewall-shaped SiN film 11.
0, the n ^- type layers 107, 10
8 having low impurity concentration portions 112a and 113a.

Next, as shown in FIG. 21, a cobalt (Co) film 114 is formed on the entire surface of the substrate.

Next, by performing a heat treatment, the Co film 1 is formed.
14 is alloyed (silicidized) with the gate electrode 105, the source region 112 and the drain region 113 which are in contact therewith, and as shown in FIG. 22, these gate electrode 105, source region 112 and drain region 113 are formed.
Cobalt silicide (CoSi) films 11
5, 116 and 117 are formed. Thereafter, unreacted Co
The film 114 is removed by etching.

Next, as shown in FIG. 23, S
After forming an interlayer insulating film 118 such as an iO ₂ film, the interlayer insulating film 118 is selectively etched away to form contact holes 119 and 120 for the source region 112 and the drain region 113.

Thereafter, though not shown, the necessary MOS type semiconductor integrated circuit is formed through necessary steps such as formation of wiring connected to the source region 112 and the drain region 113 via the contact holes 119 and 120. Complete the device.

[0017]

However, in the conventional method of manufacturing a MOS type semiconductor integrated circuit device shown in FIGS. 14 to 23, a lithography process for forming contact holes 119 and 120 in interlayer insulating film 118 is performed. 24, the contact hole 120 shifts from the design position to the gate electrode 105 side, and the gate electrode 10
In the case of 5, the subsequent formation of the wiring causes a short circuit between the gate electrode 115 and the drain region 113 inside the contact hole 120, causing a problem that a defect occurs.

Accordingly, an object of the present invention is to provide a semiconductor device having a connection hole formed in an interlayer insulating film provided so as to cover a MIS field effect transistor, even if the connection hole is misaligned. It is an object of the present invention to provide a semiconductor device capable of preventing a short circuit between a gate electrode and a source region or a drain region inside the device, and a method for manufacturing the same.

[0019]

According to a first aspect of the present invention, a first sidewall made of an insulating material higher than the gate electrode is provided on a side surface of the gate electrode. In a semiconductor device having a MIS field-effect transistor, a second sidewall made of an insulating material is provided on a surface above a gate electrode inside a first sidewall. is there.

In the first aspect of the present invention, typically, the second sidewall is etched at the time of etching for forming a connection hole in an interlayer insulating film provided so as to cover the MIS field effect transistor. It is made of a resistant insulating material. Specifically, as a material of the second sidewall, besides silicon nitride (SiN) which is usually used as a material of the first sidewall, high-resistance polycrystalline Si, aluminum oxide (Al ₂ O ₃ ), and the like. Is mentioned. Further, typically, an alloy film of a high melting point metal and a semiconductor, for example, a high melting point metal silicide film is provided on the gate electrode, the source region, and the drain region, respectively.

According to a second aspect of the present invention, there is provided a step of forming a gate electrode on a semiconductor substrate via a gate insulating film, and forming a first sidewall made of an insulating material higher than the gate electrode on a side surface of the gate electrode. Forming a second sidewall made of an insulating material on the inner surface of the first sidewall above the gate electrode.

In the second aspect of the present invention, typically, after a film made of an insulating material is formed on a semiconductor substrate, the film made of the insulating material is etched back to form a film above the gate electrode. A second sidewall is formed on a portion of the portion inside the first sidewall and a portion outside the first sidewall. Also, typically, a step of forming an interlayer insulating film on a semiconductor substrate after forming a second sidewall, and forming a connection hole for a source region and a drain region by selectively etching the interlayer insulating film. Forming step. Here, this second
Is typically made of an insulating material having an etching resistance during etching for forming a connection hole in an interlayer insulating film, as in the first invention. Is formed using a material such as polycrystalline Si or Al ₂ O ₃ .

In a second aspect of the present invention,
Typically, a step of sequentially forming a film for forming a gate electrode and an offset insulating film on a semiconductor substrate via a gate insulating film, and patterning the film for forming a gate electrode and the offset insulating film into a predetermined shape. Forming a gate electrode and forming the offset insulating film into the same shape as the gate electrode; forming a first sidewall on the side surface of the gate electrode and the offset insulating film; Selectively removing the first side wall. Most typically, a step of sequentially forming a film for forming a gate electrode and an offset insulating film on a semiconductor substrate via a gate insulating film, and patterning the film for forming a gate electrode and the offset insulating film into a predetermined shape. Forming a gate electrode and forming the offset insulating film into the same shape as the gate electrode, forming a first sidewall on the side surface of the gate electrode and the offset insulating film, and forming the offset insulating film on the gate electrode. And a step of selectively removing the first sidewall, a step of forming a refractory metal film on the semiconductor substrate, and performing heat treatment to alloy the refractory metal film with the gate electrode and the semiconductor substrate. Forming an alloy film of a refractory metal and a semiconductor on the gate electrode, the source region, and the drain region, respectively. And a step of removing the refractory metal film in the reaction.

In the present invention configured as described above, the second sidewall made of an insulating material is formed on the inner surface of the first sidewall above the gate electrode. A margin for misalignment in a lithography process for forming a connection hole in an interlayer insulating film provided so as to cover the MIS field effect transistor is increased by the width of the second sidewall. In other words, even if a misalignment occurs in the lithography process and the connection hole is formed so as to be deviated from the design position, the wiring is formed thereafter unless the connection hole extends beyond the second sidewall to the inside portion thereof. Sometimes, a short circuit between the gate electrode and the source or drain region can be prevented.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding portions are denoted by the same reference numerals.

1 to 12 show a method of manufacturing a MOS type semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

In this embodiment, first, as shown in FIG. 1, a groove 2 is formed in a predetermined portion of a p-type Si substrate (or p-well) 1 and, for example, SiO ₂ is formed inside the groove _2.
The element isolation region 3 is formed by burying the film. Next, after channel doping is performed on the active region surrounded by the element isolation region 3, S is formed on the surface of the active region by thermal oxidation.
A gate insulating film 4 made of an iO ₂ film is formed. The thickness of the gate insulating film 4 is, for example, 4 nm. Next, after a non-doped polycrystalline Si film and a PSG film are sequentially formed on the entire surface of the substrate by, for example, a CVD method, the polycrystalline Si film and the PSG film are patterned into a shape of a gate electrode. Thus, the gate electrode 5 and the PSG film 6 having the same shape as the gate electrode 5 are formed. Here, the thicknesses of the polycrystalline Si film 5 and the PSG film 6 are, for example, 1
50 nm and 200 nm.

Next, as shown in FIG. 2, n-type impurities such as phosphorus (P) are ion-implanted at a low concentration into the active region using the gate electrode 5 and the PSG film 6 thereon as a mask. ^- forming a self-aligned manner type layer 7,8 with respect to the gate electrode 5. Next, an SiO ₂ film 9 and a SiN film 10 are sequentially formed on the entire surface of the substrate by, for example, a CVD method. Here, the thicknesses of the SiO ₂ film 9 and the SiN film 10 are, for example, 5 nm and 80 nm, respectively.

Next, the SiN film 10 and the SiO ₂ film 9 are etched back by an anisotropic etching method such as a reactive ion etching (RIE) method.
As shown in FIG. 3, the gate electrode 5 and the PSG
The SiN film 10 is left in a sidewall shape on the side surface of the film 6.

Next, as shown in FIG. 4, a sufficiently thick resist 11 is applied to the entire surface of the substrate. The thickness of the resist 11 is, for example, 500 nm.

Next, as shown in FIG. 5, the resist 11 is etched back by, for example, RIE until the SiN film 10 is exposed. The etching amount at this time is, for example, 350
nm.

Next, using the resist 11 and the SiN film 10 as a mask, wet etching is performed using, for example, a dilute hydrofluoric acid solution, thereby forming the PSG film 6 and the SiO ₂ film 9 on both sides thereof as shown in FIG. Is removed by etching. As the diluted hydrofluoric acid solution used for this wet etching, for example, a solution having a composition of water: hydrofluoric acid = 20: 1 is used, and the etching time is, for example, 100 seconds. Thus, a structure in which the sidewall-shaped SiN film 10 higher than the gate electrode 5 is formed on the side surface of the gate electrode 5 is obtained.

Next, the resist 11 is removed by, for example, a plasma ashing method. Next, as shown in FIG. 7, an n-type impurity such as P is ion-implanted at a high concentration over the entire surface of the substrate, and a heat treatment is performed to electrically activate the implanted impurity. As this heat treatment, for example, 100
Lamp annealing is performed at 0 ° C. for 10 seconds. Thereby, the n ⁺ type source region 12 and the drain region 1 are formed in the active region.
3 is formed in a self-aligned manner with respect to the gate electrode 5, and the polycrystalline Si film forming the gate electrode 5 is made to be n ⁺ -type, so that the resistance is reduced. These source region 12 and drain region 13 are formed by sidewall-shaped SiN film 10.
Are provided with low impurity concentration portions 12a and 13a formed of the n ⁻ -type layers 7 and 8 formed earlier.

Next, as shown in FIG. 8, a Co film 14 is formed on the entire surface of the substrate by, for example, a sputtering method or a vacuum evaporation method. The thickness of the Co film 14 is, for example, 20 nm.

Next, by performing a heat treatment, the Co film 1 is formed.
4 and the gate electrode 5 and the source region 12 which are in contact therewith.
And the drain region 13 are alloyed (silicidized), and CoS is formed on the gate electrode 5, the source region 12 and the drain region 13 as shown in FIG.
The i-films 15, 16 and 17 are formed in a self-aligned manner. As this heat treatment, for example, 30 minutes at 550 ° C.
Second lamp annealing is performed. Thereafter, the unreacted Co film 14
Is removed by etching. This etching is performed by, for example, wet etching using sulfuric acid and hydrogen peroxide. Next, C
700 ° C. for stabilization of the oSi films 15, 16 and 17
For 30 seconds.

Next, as shown in FIG. 10, an SiN film 18 is formed on the entire surface of the substrate by, for example, a CVD method. This Si
The thickness of the N film 18 is, for example, 30 nm.

Next, the SiN film 18 is etched back by an anisotropic etching method such as RIE, for example, so that the SiN film left in a sidewall shape on the side surface of the gate electrode 5 as shown in FIG. 10, the gate electrode 5
The SiN film 18 is left in a sidewall shape on the inner surface of the upper portion and the outer surface of the SiN film 10.

Next, as shown in FIG. 12, an interlayer insulating film 19 such as a SiO ₂ film is formed on the entire surface of the substrate by, eg, CVD.
Is formed, the interlayer insulating film 19 is selectively removed by etching to form contact holes 20 and 21 for the source region 12 and the drain region 13. here,
In this etching, the etching rate of the interlayer insulating film 19 is, for example, 3 times the etching rate of the SiN films 10 and 18.
This is performed under the condition that the magnification becomes 0 times.

Thereafter, though not shown, the required MOS type semiconductor integrated circuit is formed through necessary steps such as formation of wiring connected to the source region 12 and the drain region 13 through the contact holes 20 and 21. Complete the device.

As described above, according to this embodiment,
Sidewall-shaped S formed on the side surface of gate electrode 5
Since the sidewall-shaped SiN film 18 is formed on the inner surface of the portion of the iN film 10 above the gate electrode 5, the interlayer insulating film 19 has a width corresponding to the width of the sidewall-shaped SiN film 18. Contact hole 20 formed in
The margin for the displacement of 21 is increased. For this reason, misalignment occurs in a lithography process for forming contact holes 20 and 21 in interlayer insulating film 19, and as a result, as shown in FIG.
1 is shifted from the design position toward the gate electrode 5 side, the gate electrode 5 of the sidewall-shaped SiN film 10
The gate electrode 5 and the drain region are formed inside the contact hole 21 when a wiring is formed thereafter, unless the CoSi film 15 extends over the sidewall-shaped SiN film 18 formed on the inner surface of the upper portion. 13 can be prevented from being short-circuited. Conversely, the margin for the alignment of the contact holes 20 and 21 is increased as compared with the related art, and the margin for the process is also increased, so that the production yield can be improved. Further, since the margin of the process can be allocated to the improvement of the degree of integration, it is possible to reduce the cost, increase the speed, and reduce the power consumption of the MOS semiconductor integrated circuit device by reducing the design rule.

As described above, one embodiment of the present invention has been specifically described. However, the present invention is not limited to the above-described embodiment, and various modifications based on the technical idea of the present invention are possible. .

For example, the numerical values, structures, processes, and the like described in the above-described embodiment are merely examples, and different numerical values, structures, processes, and the like may be used as needed.

In the above-described embodiment, the case where the present invention is applied to a MOS type semiconductor integrated circuit device has been described.
The present invention can be applied to an OS type semiconductor integrated circuit device and the like.

[0044]

As described above, according to the semiconductor device of the present invention, the second sidewall made of an insulating material is provided on the inner surface of the first sidewall above the gate electrode. Accordingly, even when a connection hole formed in an interlayer insulating film provided to cover the MIS field effect transistor is displaced,
When a wiring is formed thereafter, a short circuit between the gate electrode and the source or drain region inside the connection hole can be prevented.

According to the method of manufacturing a semiconductor device of the present invention, the second side wall made of an insulating material is formed on the inner surface of the first side wall above the gate electrode. Therefore, even if a connection hole formed in an interlayer insulating film formed so as to cover the MIS field effect transistor is displaced, when a wiring is formed thereafter, the gate electrode and the gate electrode are formed inside the connection hole. Short circuit with the source region or the drain region can be prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a method for manufacturing a MOS semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a method for manufacturing a MOS type semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 3 is a sectional view for explaining the method for manufacturing the MOS-type semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining the method for manufacturing the MOS-type semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining the method for manufacturing the MOS-type semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining the method for manufacturing the MOS-type semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining the method for manufacturing the MOS-type semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 8 is a cross-sectional view for explaining the method for manufacturing the MOS-type semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 9 is a cross-sectional view for explaining the method for manufacturing the MOS-type semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 10 is a cross-sectional view for explaining the method for manufacturing the MOS-type semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 11 is a cross-sectional view for explaining the method for manufacturing the MOS-type semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 12 is a cross-sectional view for explaining the method for manufacturing the MOS-type semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 13 is a cross-sectional view for explaining the method for manufacturing the MOS-type semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 14 is a cross-sectional view for describing a method for manufacturing a conventional MOS-type semiconductor integrated circuit device.

FIG. 15 is a cross-sectional view for explaining a method for manufacturing a conventional MOS-type semiconductor integrated circuit device.

FIG. 16 is a cross-sectional view for explaining a method for manufacturing a conventional MOS-type semiconductor integrated circuit device.

FIG. 17 is a cross-sectional view for explaining the method for manufacturing the conventional MOS-type semiconductor integrated circuit device.

FIG. 18 is a cross-sectional view for explaining the method for manufacturing the conventional MOS-type semiconductor integrated circuit device.

FIG. 19 is a cross-sectional view for explaining the method for manufacturing the conventional MOS-type semiconductor integrated circuit device.

FIG. 20 is a cross-sectional view for explaining a method for manufacturing a conventional MOS-type semiconductor integrated circuit device.

FIG. 21 is a cross-sectional view for explaining a method for manufacturing a conventional MOS-type semiconductor integrated circuit device.

FIG. 22 is a cross-sectional view for explaining the method for manufacturing the conventional MOS-type semiconductor integrated circuit device.

FIG. 23 is a cross-sectional view for explaining the method for manufacturing the conventional MOS-type semiconductor integrated circuit device.

FIG. 24 is a cross-sectional view for explaining the method for manufacturing the conventional MOS-type semiconductor integrated circuit device.

[Explanation of symbols]

1 ... p-type Si substrate, 4 ... gate insulating film, 5 ...
・ Gate electrode, 6 ... PSG film, 10, 18 ... S
iN film, 12 ... source region, 13 ... drain region, 14 ... Co film, 15, 16, 17 ... CoS
i film, 19 ... interlayer insulating film, 20, 21 ... contact hole

Claims (11)

[Claims] 1. A semiconductor device having a MIS field-effect transistor in which a first sidewall made of an insulating material higher than the gate electrode is provided on a side surface of the gate electrode. A semiconductor device, wherein a second sidewall made of an insulating material is provided on an inner surface of the first sidewall. 2. The method according to claim 2, wherein the second side wall includes the MI.
2. The semiconductor device according to claim 1, wherein the semiconductor device is made of an insulating material having etching resistance during etching for forming a connection hole in an interlayer insulating film provided to cover the S-type field effect transistor. 3. The semiconductor device according to claim 1, wherein said second sidewall is made of silicon nitride. 4. The semiconductor device according to claim 1, wherein an alloy film of a refractory metal and a semiconductor is provided on each of the gate electrode, the source region, and the drain region. 5. A step of forming a gate electrode on a semiconductor substrate with a gate insulating film interposed therebetween, and a step of forming a first sidewall made of an insulating material higher than the gate electrode on a side face of the gate electrode. Forming a second sidewall made of an insulating material on a surface inside the first sidewall in a portion above the gate electrode. 6. After forming a film made of an insulating material on the semiconductor substrate, the film made of the insulating material is etched back to form a portion above the gate electrode inside the first sidewall. 6. The method of manufacturing a semiconductor device according to claim 5, wherein said second side wall is formed on a surface of said first side wall and a surface outside said first side wall. 7. A step of forming an interlayer insulating film on the semiconductor substrate after forming the second sidewall, and selectively etching the interlayer insulating film to form connection holes for a source region and a drain region. 6. The method of manufacturing a semiconductor device according to claim 5, further comprising the step of: 8. The semiconductor device according to claim 8, wherein said second sidewall is made of an insulating material having an etching resistance during etching for forming said connection hole in said interlayer insulating film. Production method. 9. The method according to claim 5, wherein said second sidewall is made of silicon nitride. 10. A step of sequentially forming a film for forming a gate electrode and an offset insulating film on the semiconductor substrate via the gate insulating film, and forming the film for forming a gate electrode and the offset insulating film in a predetermined shape. Forming the gate electrode and forming the offset insulating film in the same shape as the gate electrode, and forming the first sidewall on the side surface of the gate electrode and the offset insulating film. 6. The method of manufacturing a semiconductor device according to claim 5, further comprising the step of: selectively removing the offset insulating film with respect to the gate electrode and the first sidewall. 11. A step of sequentially forming a film for forming a gate electrode and an offset insulating film on the semiconductor substrate via the gate insulating film, and forming the film for forming a gate electrode and the offset insulating film in a predetermined shape. Forming the gate electrode and forming the offset insulating film in the same shape as the gate electrode, and forming the first sidewall on the side surface of the gate electrode and the offset insulating film. A step of selectively removing the offset insulating film from the gate electrode and the first sidewall, a step of forming a refractory metal film on the semiconductor substrate, and a heat treatment. Alloying the high melting point metal film and the gate electrode and the semiconductor substrate, the gate electrode,
6. The semiconductor according to claim 5, further comprising a step of forming an alloy film of a refractory metal and a semiconductor on the source region and the drain region, respectively, and a step of removing the unreacted refractory metal film. Device manufacturing method.