JP2008263114A - Manufacturing method of semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device, and the semiconductor device, in which parasitic resistance is sufficiently reduced while a short channel effect is suppressed without employing an unsymmetrical transistor structure for crystal defect suppression in a channel region. <P>SOLUTION: Such a process is carried out in which a gate electrode 16 is formed on an SOI substrate 11 on which an Si layer 11a, SiO<SB>2</SB>layer 11b, and Si layer 11c are stacked in this order through a gate insulating film 15. In the next process, the SOI substrate 11 is dug until the bottom layer Si layer 11a is exposed by etching with the gate electrode 16 as a mask. In the next process, an epitaxial growth layer 22 is formed by epitaxial-growing the Si layer on the surface of the Si layer 11a that has been exposed, and a source-drain region 23 is formed at an epitaxial growth layer 22. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, and more particularly to a method of manufacturing a MOS (Metal Oxide Semiconductor) type field effect transistor (MOSFET) and a MOSFET manufactured by the manufacturing method.

  Conventionally, in the case of forming a MOSFET on a bulk silicon (Si) substrate, the short channel effect has become a problem with miniaturization. Therefore, in order to suppress the short channel effect, a MOSFET is formed on an SOI (Silicon On Insulator) substrate that can suppress the diffusion depth shallow.

Here, the manufacturing method of the MOSFET on the SOI substrate will be described with reference to FIG. 9. For example, a groove is formed on the surface side of the SOI substrate 101 in which the Si layer 101a, the insulating layer 101b, and the Si layer 101c are stacked in this order. Then, an element isolation layer 102 having an STI (Shallow Trench Isolation) structure in which silicon oxide (SiO ₂ ) is buried in the trench is formed.

Next, a gate electrode 104 made of polysilicon is patterned on the SOI substrate 101 through a gate insulating film 103 made of SiO ₂ . At this time, each material film constituting the gate insulating film 103 and the gate electrode 104 and a hard mask (not shown) made of silicon nitride (SiN) are stacked on the SOI substrate 101, and these stacked films are patterned. Etch.

  Next, offset spacers 105 made of TEOS (Tetra Ethoxy Silane) are formed on both sides of the gate insulating film 103, the gate electrode 104, and the hard mask. Thereafter, an impurity region is introduced into the surface layer (Si layer 101c) of the SOI substrate 101 on both sides of the gate electrode 104 provided with the offset spacer 105 by ion implantation, thereby forming the extension region 106.

  Subsequently, sidewalls 107 formed by sequentially laminating a SiN layer 107 a and a TEOS layer 107 b are formed on both sides of the offset spacer 105. Thereafter, an Si layer is epitaxially grown on the exposed surface of the SOI substrate 101 to form an epitaxial growth layer 108.

  Subsequently, impurity ions are introduced into the epitaxial growth layer 108 on both sides of the gate electrode 104 provided with the sidewall 107 and the surface layer (Si layer 101c) of the SOI substrate 101 by ion implantation, thereby forming the source / drain region 109. Form. Subsequently, impurity activation annealing is performed by a rapid thermal annealing (RTA) method. Here, the region of the Si layer 101 c immediately below the gate electrode 104 sandwiched between the source / drain regions 109 via the extension region 106 becomes the channel region 110.

  Next, the hard mask on the surface of the gate electrode 104 is removed, and a metal film (not shown) made of nickel (Ni) is formed on the entire area of the SOI substrate 101 in this state. Thereafter, the silicide layer 111 is formed by siliciding the surface side of the epitaxial growth layer 108 and the surface side of the gate electrode 104 by heat treatment. Thereafter, the unreacted metal film is removed.

  As described above, a MOSFET is formed on the SOI substrate 101. Compared with the case where the source / drain region 109 is formed only on the surface layer of the SOI substrate 101, this MOSFET can increase the occupied volume of the source / drain region 109 as much as the epitaxial growth layer 108 is formed. In addition, parasitic resistance can be suppressed.

  On the other hand, in addition to the method described above, there is a method for suppressing the short channel effect using a bulk Si substrate. For example, after patterning a thermal oxide film on the surface of the Si substrate, the Si single crystal is epitaxially grown on the exposed surface of the Si substrate, and the Si single crystal is grown laterally by recrystallization by heating and melting. Thus, a Si thin film is also formed on the thermal oxide film. Then, an example in which a gate electrode is formed on a Si thin film on the thermal oxide film via a gate insulating film and a source / drain region is formed by an ion implantation method using the gate electrode as a mask has been reported (for example, , See Patent Document 1). In this method, since the thermal oxide film is formed only in the lower layer of the channel region, the source / drain regions can be formed deep in the Si substrate, and the parasitic resistance can be reduced. There is.

  Furthermore, in order to suppress the short channel effect, before forming the gate insulating film and the gate electrode, an insulating layer is formed by oxygen ion implantation in a region below the LDD (Lightly Doped Drain) region of the Si substrate. An example of this is also reported (see, for example, Patent Document 2).

JP-A-6-334178 JP 2003-17693 A

  However, in the method of manufacturing the semiconductor device described with reference to FIG. 9 described above, the epitaxial growth layer 108 is formed on the SOI substrate 101 to increase the occupied volume of the source / drain region 109. If the parasitic capacitance between the gate electrode 104 and the gate electrode 104 is taken into consideration, the height of the epitaxial growth layer 108 is limited. Further, the source / drain region 109 cannot be expanded in the depth direction of the SOI substrate 101 by the insulating layer 101b in the SOI substrate 101, and the parasitic resistance is not sufficiently reduced.

  Further, in the method formed in Patent Document 1, since the gate electrode is formed after forming the thermal oxide film, misalignment is likely to occur between the gate electrode and the thermal oxide film, resulting in asymmetry of the transistor structure. It might be. As a result, this leads to major problems such as transistor characteristic variations and yield deterioration. In addition, the possibility of crystal defects occurring in the Si thin film during recrystallization is very high, and the channel region is provided in the Si thin film, so that transistor characteristics are deteriorated and reliability is deteriorated due to the crystal defects. Is concerned.

  Further, similarly in the method described in Patent Document 2, an insulating layer is formed below the region to be the LDD region, and then a gate insulating film and a gate electrode are formed. Misalignment is likely to occur, and the transistor structure is highly likely to be asymmetric.

  In the method described in Patent Document 2, when the insulating layer is formed by implanting oxygen ions after forming a gate electrode on a Si substrate via a gate insulating film, insulation is performed by self-alignment. Since the layer is formed, the asymmetry of the transistor structure is eliminated. However, since the energy of oxygen ion implantation is very large, the Si substrate is greatly damaged. Therefore, it is necessary to perform an extremely high temperature annealing process (1300 ° C. or higher) for crystal defect recovery and insulating layer formation. However, if such a high temperature annealing process is performed, the gate insulating film is destroyed. A major problem arises that the transistor cannot be operated.

  Therefore, the present invention provides a method for manufacturing a semiconductor device in which the parasitic resistance can be sufficiently reduced and the crystal defects in the channel region are suppressed without making the transistor structure asymmetrical while the short channel effect is suppressed. Another object is to provide a semiconductor device.

  In order to achieve the above-described object, a method for manufacturing a semiconductor device according to the present invention is characterized by sequentially performing the following steps. First, in the first step, a step of forming a gate electrode through a gate insulating film on an SOI substrate in which a Si layer, an insulating layer, and a Si layer are stacked in this order is performed. Next, in the second step, a step of digging up the SOI substrate until the lowermost Si layer is exposed is performed by etching using the gate electrode as a mask. Next, in a third step, a Si-containing layer is epitaxially grown on the exposed surface of the Si layer, and a source / drain region is formed in the Si-containing layer.

  According to such a method for manufacturing a semiconductor device, the SOI substrate is dug by etching using the gate electrode as a mask until the lowermost Si layer is exposed, so that the insulating layer immediately below the gate electrode remains by self-alignment. Therefore, the transistor structure is prevented from being asymmetric without causing a shift in the position of the gate electrode and the insulating layer. In addition, the Si-containing layer is epitaxially grown on the exposed surface of the Si layer, and the source / drain regions are formed in the Si-containing layer, so that the source / drain region is left in the state where the insulating layer remains in the lower layer of the channel region. A drain region is formed deeply to the bottom layer of the SOI substrate. Thereby, the parasitic resistance is reduced in a state where the short channel effect is suppressed. In addition, since the channel region is provided in the surface layer of the SOI substrate, as described in the background art, crystal defects in the channel region are suppressed as compared with the case where the channel region is formed in the recrystallized Si thin film. The

  According to another aspect of the present invention, there is provided a semiconductor device in which a gate electrode is provided on a SOI substrate in which a Si layer, an insulating layer, and a Si layer are stacked in this order via a gate insulating film. Is characterized in that a Si-containing layer formed by epitaxial growth is provided on a region dug until the lowermost Si layer is exposed, and a source / drain region is provided in the Si-containing layer. .

  Such a semiconductor device is manufactured by the above-described manufacturing method, and the SOI substrate on both sides of the gate electrode is epitaxially grown on a region that is dug until the lowermost Si layer is exposed. Since the source / drain regions are provided, the source / drain regions are deeply provided to the bottom layer of the SOI substrate with the insulating layer provided below the channel region, thereby increasing the occupied volume of the source / drain regions. It becomes possible to make it. Thereby, the parasitic resistance is reduced in a state where the short channel effect is suppressed. Further, since the channel region is provided in the surface layer of the SOI substrate, crystal defects in the channel region are suppressed as compared with the case where the channel region is formed in the recrystallized Si thin film.

  As described above, according to the method for manufacturing a semiconductor device and the semiconductor device of the present invention, the transistor structure is prevented from being asymmetrical, so that variations in transistor characteristics and a decrease in yield can be prevented. In addition, since the parasitic resistance can be reduced in a state where the short channel effect is suppressed, the driving current of the transistor can be improved. Further, since crystal defects in the channel region are suppressed, deterioration of transistor characteristics and reliability due to the crystal defects can be prevented. From the above, the characteristics of the transistor can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In each embodiment, the configuration of a semiconductor device will be described in the order of manufacturing steps.

  As an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention, a method for manufacturing a MOSFET will be described with reference to a manufacturing process sectional view of FIG. In addition, the same number is attached | subjected and demonstrated to the structure similar to what was demonstrated by background art.

First, as shown in FIG. 1A, an SOI substrate 11 used in this embodiment will be described. The SOI substrate 11 is formed by laminating an Si layer 11a, an SiO ₂ layer 11b (insulating layer), and an Si layer 11c in this order. The SiO ₂ layer 11b is 50 nm to 200 nm, and the Si layer 11c serving as a surface layer is 10 nm to 100 nm. The film thickness is formed. Here, for example, the SiO ₂ layer 11b is 50 nm and the Si layer 11c is 15 nm.

Next, for example, a SiN film 12 is formed on the SOI substrate 11 as shown in FIG. The SiN film 12 is a hard mask for forming a trench with an STI structure in a later process. The thickness of the SiN film 12 increases the height of the element isolation layer formed in the trench from the surface of the SOI substrate 11. Is defined. Then, as will be described later, in the step of removing the insulating layer 11b of the SOI substrate 11 by anisotropic etching, the element isolation layer made of SiO ₂ is exposed. The film thickness of the SiN film 12 is set so that the height of the element isolation layer is increased.

  Next, as shown in FIG. 1C, a resist pattern (not shown) is formed on the SiN film 12, and the lowermost layer is formed on the SiN film 12 and the SOI substrate 11 by dry etching using the resist pattern as a mask. The STI structure trench 13 having a depth reaching the Si layer 11a is formed with a depth of about 300 nm, for example.

Subsequently, as shown in FIG. 1D, on the SiN film 12 in a state in which the groove 13 is embedded by, for example, a high density plasma chemical vapor deposition (HDP-CVD) method. After the SiO ₂ film is formed, the element isolation layer 14 made of SiO ₂ is removed by removing the SiO ₂ film until the surface of the SiN film 12 is exposed by a chemical mechanical polishing (CMP) method. As described above, the STI structure is formed.

  Next, as shown in FIG. 2E, the SiN film 12 (see FIG. 1D) is removed by wet etching using hot phosphoric acid, for example, and the surface of the SOI substrate 11 is exposed. As a result, the upper portion of the element isolation layer 14 protrudes from the surface of the SOI substrate 11.

  Next, as shown in FIG. 2F, a gate electrode 16 made of, for example, polysilicon (Poly-Si) is formed on the SOI substrate 11 via a gate insulating film 15 made of, for example, silicon oxynitride (SiON). To do. The gate electrode 16 is covered with a hard mask 17 made of SiN. In this case, a SiON film is formed on the SOI substrate 11 with a thickness of about 1.8 nm, a Poly-Si film is formed on the SiON film by 100 nm to 150 nm, and a SiN film is formed on the Poly-Si film by 50 nm to 50 nm. It is formed with a film thickness of 100 nm. Here, for example, the Poly-Si film is 150 nm and the SiN film is 50 nm. Thereafter, a resist pattern is formed on the SiN film, and the laminated film is patterned by etching using the resist pattern as a mask.

Here, the gate insulating film 15 is formed of SiON and the gate electrode 16 is formed of Poly-Si. However, the gate insulating film 15 is formed of a High-k material having a relative dielectric constant higher than that of SiO _2. Alternatively, the gate electrode 16 may be formed of a metal-containing material.

  Subsequently, as shown in FIG. 2G, offset spacers 18 made of, for example, TEOS are formed on both sides of the gate insulating film 15, the gate electrode 16, and the hard mask 17 described above. In this case, for example, a TEOS film having a thickness of about 8 nm is formed on the SOI substrate 11 so as to cover the gate insulating film 15, the gate electrode 16, and the hard mask 17, and then the TEOS film is formed on the SOI substrate. Etch back until surface 11 is exposed.

  Here, although the offset spacer 18 is formed of TEOS, it may be formed of other insulating materials such as SiN.

  Thereafter, an extension region 19 is formed by introducing impurities into the surface layer (Si layer 11c) of the SOI substrate 11 on both sides of the gate electrode 16 by ion implantation, for example. At this time, when forming an N-channel MOSFET (NMOS), for example, a p-type impurity made of boron (B) is introduced from an oblique direction to widen a depletion layer, and an n-type impurity made of arsenic (As) is introduced. As a result, the extension region 19 is formed. When forming a P-channel MOSFET (PMOS), for example, an n-type impurity made of As is introduced from an oblique direction to widen a depletion layer, and a p-type impurity made of B is introduced to form the extension region 19. Form.

  In addition to B, gallium (Ga) and indium (In) are used as p-type impurities, and phosphorus (P) and antimony (Sb) are used as n-type impurities in addition to As.

  Next, as shown in FIG. 2H, a sidewall 20 in which a SiN layer 20 a and a TEOS layer 20 b are stacked in this order is formed outside the offset spacer 18. In this case, a SiN film 20 nm and a TEOS film 50 nm are formed in this order on the SOI substrate 11 so as to cover the gate insulating film 15 provided with the offset spacer 18, the gate electrode 16, and the hard mask 17. Thereafter, the TEOS film and the SiN film are etched back until the surface of the SOI substrate 11 is exposed.

Next, using the gate electrode 16 covered with the hard mask 17 and the sidewalls 20 as a mask, the recess region 21 is formed by performing recess etching in which the SOI substrate 11 is dug until the lowermost Si layer 11a is exposed. . Here, for example, the recess etching is performed by anisotropic etching. At this time, the SiO ₂ layer 11b of the SOI substrate 11 is removed in a state where the element isolation layer 14 made of SiO ₂ is exposed. By forming the layer 14 high, the element isolation layer 14 is prevented from being removed beyond an allowable range. By this etching, the insulating layer 11b immediately below the gate electrode 16 covered with the sidewall 20 by self-alignment remains, so that the position of the gate electrode 16 and the insulating layer 11b does not shift and the transistor structure is asymmetric. Is prevented.

Here, the example in which the element isolation layer 14 is formed high in advance by the amount removed by etching has been described. However, the element isolation layer 14 may be formed so as to have an etching selectivity with the SiO ₂ layer 11b. for example an element isolation layer 14 by forming a high-density SiO ₂ layer than the SiO ₂ layer 11b, may increase the etch selectivity.

  Subsequently, as shown in FIG. 3I, the epitaxial growth layer 22 is formed by selectively epitaxially growing the Si layer on the Si layer 11 a exposed at the bottom of the recess region 21. As a result, the source / drain regions to be formed in the epitaxial growth layer 22 in a later step can be formed deeply up to the lowermost layer 11a of the SOI substrate 11. Here, the volume occupied by the source / drain regions 23 is further increased by forming the epitaxial growth layer 22 so that the surface of the epitaxial growth layer 22 is higher than the surface of the SOI substrate 11. However, in this case, the height of the epitaxial growth layer 22 is adjusted so that the parasitic capacitance generated between the epitaxial growth layer 22 and the gate electrode 16 is suppressed within an allowable range.

  Thereafter, the hard mask 17 (see FIG. 2H) is removed by wet etching using hot phosphoric acid. Next, by introducing impurities into the epitaxial growth layer 22 by ion implantation, source / drain regions 23 are formed in the epitaxial growth layer 22. At this time, when forming an NMOS, an n-type impurity made of, for example, phosphorus (P) is introduced, and when forming a PMOS, a p-type impurity made of, for example, B is introduced. Subsequently, the impurities are activated by spike annealing at about 1050 ° C.

  Here, the region of the Si layer 11 c immediately below the gate electrode 16 sandwiched by the source / drain regions 23 via the extension region 19 becomes the channel region 24. Therefore, as described above, by forming the source / drain regions 23 in the epitaxial growth layer 22, the source / drain regions 23 are formed on the SOI substrate 11 with the insulating layer 11 b remaining in the lower layer of the channel region 24. It is formed deep up to the lowermost Si layer 11a, and the occupied volume of the source / drain region 23 can be increased. Thereby, the parasitic resistance is reduced in a state where the short channel effect is suppressed. Furthermore, since the insulating layer 11b remains below the extension region 19 here, the short channel effect is more reliably suppressed.

  In this embodiment, the example in which the impurity is introduced by ion implantation to form the source / drain region 23 has been described. However, the present invention is not limited to this, and the impurity is added when the Si layer is epitaxially grown. It may be introduced (in-situ dope). In this case, it is preferable to introduce impurities by ion implantation because not only the process is simplified but also crystal defects due to impurity introduction are suppressed and the impurities are sufficiently activated. Further, after the impurities are introduced by in-situ dope, the missing portion may be introduced by ion implantation.

  Subsequently, as shown in FIG. 3J, the entire region on the SOI substrate 11 in this state, that is, on the gate electrode 16, the sidewall 20, the epitaxial growth layer 22, and the element isolation layer 14 is formed by sputtering. For example, a metal film (not shown) made of a Ni film is formed with a film thickness of about 8 nm. Thereafter, heat treatment is performed to silicide the surface of the gate electrode 16 and the surface of the epitaxial growth layer 22, thereby forming a silicide layer 25. Thereafter, the unreacted metal film is removed.

  As the metal film, in addition to Ni, another metal such as cobalt (Co) or nickel platinum (NiPt) may be formed.

Next, as shown in FIG. 3 (k), for example, by HDP-CVD, the entire region on the SOI substrate 11 in this state, that is, on the silicide layer 25, the sidewall 20 and the element isolation layer 14, for example, An interlayer insulating film 26 made of SiO ₂ is formed with a thickness of 300 nm. Subsequently, a resist pattern (not shown) is formed on the interlayer insulating film 26, and etching is performed using this resist pattern as a mask to form the silicide layer 25 on the surface side of the gate electrode 16 and the surface side of the source / drain region 23. A contact hole 27 reaching the silicide layer 25 is formed. Thereafter, for example, W is buried in the contact hole 27 through a barrier metal layer made of, for example, titanium nitride (TiN) that prevents W from diffusing into the interlayer insulating film, thereby forming the contact plug 28.

  According to the semiconductor device manufacturing method and the semiconductor device obtained by this manufacturing method, the lowermost Si layer 11a is exposed on the SOI substrate 11 by etching using the gate electrode 16 provided with the sidewall 20 as a mask. Since the insulating layer 11b immediately below the gate electrode 16 remains due to self-alignment, the transistor structure is prevented from being asymmetric without causing a shift in the position of the gate electrode 16 and the insulating layer 11b. The Therefore, variations in transistor characteristics and a decrease in yield can be prevented.

  In addition, since the source / drain regions 23 are formed in the epitaxial growth layer 22 formed on the exposed surface of the Si layer 11a, the SOI layer 11b remains in the lower layer of the channel region 24 and the extension region 19 while the SOI layer 11b remains. The source / drain region 23 can be formed deeply up to the lowermost layer 11 c of the substrate 11. Thereby, in a state where the short channel effect is suppressed, the parasitic resistance can be reduced, and the driving current of the transistor can be improved.

  Further, since the channel region 24 is provided in the surface layer (Si layer 11c) of the SOI substrate 11, as described in the background art, the channel region 24 is compared with the case where the channel region is formed in the recrystallized Si thin film. Crystal defects in the region 24 are suppressed. Therefore, deterioration of transistor characteristics and deterioration of reliability due to this crystal defect can be prevented.

  From the above, according to the semiconductor device and the manufacturing method of the semiconductor device of this embodiment, the characteristics of the transistor can be improved.

  In the first embodiment described above, an example in which the epitaxial growth layer 22 forming the source / drain region 23 is composed of an Si layer has been described. However, the epitaxial growth layer 22 is a mixture of atoms having different lattice constants between Si and Si. It may be composed of crystal layers. For example, when forming an NMOS, in the step described with reference to FIG. 3I, Si and carbon (C) having a lattice constant smaller than that of Si and Si are formed on the Si layer 11a exposed at the bottom of the recess region 21. The epitaxial growth layer 22 is formed by epitaxially growing the mixed crystal layer. This makes it possible to apply a tensile stress to the channel region 24 and improve carrier mobility. Further, when forming a PMOS, in the above process, a mixed crystal layer of germanium (Ge) having a lattice constant larger than that of Si and Si is epitaxially grown on the Si layer 11a exposed at the bottom of the recess region 21. Then, the epitaxial growth layer 22 is formed. This makes it possible to apply a compressive stress to the channel region 24 and improve carrier mobility. Even when the mixed crystal layer is epitaxially grown as described above, impurities may be introduced when the mixed crystal layer is epitaxially grown.

  In the first embodiment, the sidewall 20 having the two-layer structure of the SiN layer 20a / TEOS layer 20b has been described in the step described with reference to FIG. 2H. Thus, the sidewall 20 ′ having a single layer structure may be used. In this case, in the process described with reference to FIG. 2H, the gate insulating film 15, the gate electrode 16, and the hard mask 17 (see FIG. 2H) provided with the offset spacer 18 are covered. Thus, for example, a SiN film with a thickness of 70 nm is formed on the SOI substrate 11. Thereafter, the SiN film is etched back until the surface of the SOI substrate 11 is exposed, thereby forming a sidewall 20 '.

  Further, as shown in FIG. 4B, the sidewall 20 ″ may have a three-layer structure. In this case, an offset spacer 18 is provided in the process described with reference to FIG. For example, TEOS / SiN / TEOS is formed to a thickness of 10 nm / 20 nm / 34 nm on the SOI substrate 11 so as to cover the gate insulating film 15, the gate electrode 16, and the hard mask 17 (see FIG. 2H). The film is formed. Thereafter, the laminated film is etched back until the surface of the SOI substrate 11 is exposed, whereby the sidewall 20 ″ in which the TEOS layer 20a ″, the SiN layer 20b ″, and the TEOS layer 20c ″ are laminated in this order is formed. Form.

  In the above embodiment, the epitaxial growth layer 22 is formed so as to be higher than the surface of the SOI substrate 11 in the step described with reference to FIG. 3I. However, the present invention is not limited to this, and FIG. As shown in FIG. 4, the epitaxial growth layer 22 ′ may be formed so as to have the same height as the surface of the SOI substrate 11. In this case, the parasitic resistance increases as compared with the first embodiment, but the parasitic capacitance between the epitaxial growth layer 22 ′ and the gate electrode 16 can be reduced.

  Furthermore, in the above embodiment, the extension region 19 is formed by ion implantation in the process described with reference to FIG. 2G. However, the present invention is not limited to this, and the surface of the SOI substrate on both sides of the gate electrode. An extension region may be formed in the silicon-containing layer formed by recessing the layer and epitaxially growing in the recess region. In this case, as shown in FIG. 6A, after the offset spacer 18 is formed, the gate electrode 16 covered with the hard mask 17 and the offset spacer 18 is used as a mask, and the surface layer of the SOI substrate 11 is used. A recess region 29 is formed by digging down a certain Si layer 11c. Here, the Si layer 11 c is dug down so that the Si layer 11 c remains at the bottom of the recess region 29.

  Next, as shown in FIG. 6B, an Si-containing layer is epitaxially grown on the Si layer 11 c exposed at the bottom of the recess region 29 to form an epitaxial growth layer 30. In this case, the epitaxial growth layer 30 is preferably formed of a mixed crystal layer of atoms having different lattice constants from Si and Si described above. By forming the mixed crystal layer, the Si layer immediately below the gate electrode 16 is formed. It is possible to effectively apply stress to the channel region formed in 11c. Impurities may be introduced into the epitaxial growth layer 30 by in-situ dope, or impurities may be introduced by ion implantation after the epitaxial growth layer 30 made of a mixed crystal layer not containing impurities is formed. As described above, the extension region 19 ′ composed of the epitaxial growth layer 30 is formed.

Here, the Si layer 11c is dug so that the Si layer 11c remains at the bottom of the recess region 29. However, the SOI substrate 11 may be dug until the SiO ₂ layer 11b is reached. In this case, the epitaxial growth layer 30 is formed by performing epitaxial growth in the lateral direction from the Si layer 11 c directly below the gate electrode 16 covered with the sidewall 20.

(Second Embodiment)
FIG. 7 is a manufacturing step sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment. In the first embodiment, the process up to the step of forming the gate electrode described with reference to FIGS. 1A to 2F is performed by the same method as in the first embodiment. Further, the same components as those in the first embodiment will be described with the same numbers.

  First, as shown in FIG. 7A, after an offset spacer 18 made of, for example, TEOS is formed on both sides of the gate insulating film 15, the gate electrode 16, and the hard mask 17, the SOI substrate 11 is formed by ion implantation, for example. A first extension region 19a '' is formed by introducing impurities into the Si layer 11c on the front surface side.

  Subsequently, an epitaxial growth layer 31 is formed by epitaxially growing a Si layer on the SOI substrate 11 (in-situ dope). As a result, the epitaxially grown layer 31 becomes the second extension region 19b ″, and the extension region 19 ″ including the first extension region 19a ″ and the second extension region 19b ″ is formed. Can also be formed on the SOI substrate 11. However, in this case, the height of the epitaxial growth layer 31 is adjusted so that the parasitic capacitance generated between the epitaxial growth layer 31 and the gate electrode 16 is suppressed within an allowable range.

  Here, the Si layer is epitaxially grown as the epitaxial growth layer 31, but Si and Si have lattice constants similar to the epitaxial growth layer 22 described with reference to FIG. 3I in the first embodiment. The epitaxial growth layer 31 may be composed of different mixed crystal layers.

  Here, the epitaxial growth layer 31 is formed by epitaxially growing a Si layer containing impurities. However, after the Si layer containing no impurities is epitaxially grown, the impurities may be introduced by ion implantation. In this case, before forming the first extension region 19a ″ by ion implantation, the epitaxial growth layer 31 is formed on the SOI substrate 11 without containing impurities. Thereafter, an impurity is introduced into the epitaxial growth layer 31 and the surface layer (Si layer 11c) of the SOI substrate 11 by ion implantation, thereby forming an extension region 19 ''.

  Furthermore, although illustration is omitted here, an extension region may be formed only in the epitaxial growth layer 31 formed on the SOI substrate 11. In this case, it is preferable to introduce impurities during the epitaxial growth.

  The subsequent steps are performed in the same manner as in the first embodiment. That is, as shown in FIG. 7B, the SiN layer 20a and the TEOS layer 20b are laminated in this order on both sides of the gate insulating film 15, the gate electrode 16 and the hard mask 17 provided with the offset spacer 18. Sidewall 20 is formed. Next, using the gate electrode 16 covered with the hard mask 17 and the sidewalls 20 as a mask, anisotropic recess etching is performed in which the epitaxial growth layer 31 and the SOI substrate 11 are dug until the lowermost Si layer 11a is exposed. Thus, the recess region 21 is formed.

  Subsequently, as shown in FIG. 7C, the epitaxial growth layer 22 is formed by selectively epitaxially growing the Si layer on the exposed Si layer 11a. Thereafter, the hard mask 17 (see FIG. 7B) is removed by wet etching using hot phosphoric acid. Next, by introducing impurities into the epitaxial growth layer 22 by ion implantation, source / drain regions 23 are formed in the epitaxial growth layer 22. Subsequently, the impurities are activated by spike annealing at about 1050 ° C.

  Thereafter, a metal film (not shown) made of, for example, Ni is formed over the entire area of the SOI substrate 11 in this state by, for example, sputtering, and then heat treatment is performed, so that the surface of the gate electrode 16 and the surface of the epitaxial growth layer 22 Is silicided to form a silicide layer 25.

  Even in such a semiconductor device manufacturing method and semiconductor device, the SOI substrate 11 is dug until the lowermost Si layer 11a is exposed by etching using the gate electrode 16 provided with the sidewall 20 as a mask. Since the source / drain regions 23 are formed in the epitaxial growth layer 22 formed on the surface of the Si layer 11a, the same effects as in the first embodiment can be obtained.

  In addition, according to the present embodiment, by forming the second extension region 19b ″ in the epitaxial growth layer 31, the occupied volume of the extension region 19 ″ can be increased, so that the parasitic resistance can be further reduced. Become.

(Modification 1)
As a first modification of the second embodiment, as shown in FIG. 8A, the side surface of the epitaxially grown layer 31 ′ has a surface inclined with respect to the surface of the SOI substrate 11, that is, a so-called facet shape. You may do it. For the formation of the epitaxial growth layer 31 ′ having such a facet shape, “A Planar transistor for 32-nm node and beyond with an ultra-shallow junction fabricated using in-situ doped selective Si epitaxy” 36 European Solid-State Device Research Conference, p. 81.

  Thus, by forming the epitaxial growth layer 31 ′ having a facet shape, the fringe between the second extension region 19b ″ formed in the epitaxial growth layer 31 ′ and the gate electrode 16 is compared with the second embodiment. This is preferable because the capacity is reduced.

  The subsequent steps are performed in the same manner as the method described with reference to FIGS. 7B to 7C in the second embodiment. That is, as shown in FIG. 8B, the SiN layer 20a and the TEOS layer 20b are laminated in this order on both sides of the gate insulating film 15, the gate electrode 16 and the hard mask 17 provided with the offset spacer 18. Sidewall 20 is formed. As a result, the groove between the offset spacer 18 and the epitaxial growth layer 31 'is filled with the SiN layer 20a.

  Next, using the gate electrode 16 covered with the hard mask 17 and the sidewalls 20 as a mask, anisotropic recess etching is performed in which the epitaxially grown layer 31 ′ and the SOI substrate 11 are dug until the lowermost Si layer 11a is exposed. By doing so, the recess region 21 is formed.

  Subsequently, as shown in FIG. 8C, the epitaxial growth layer 22 is formed by selectively epitaxially growing the Si layer on the exposed Si layer 11a. Thereafter, the hard mask 17 (see FIG. 8B) is removed by wet etching using hot phosphoric acid. Next, by introducing impurities into the epitaxial growth layer 22 by ion implantation, source / drain regions 23 are formed in the epitaxial growth layer 22. Subsequently, the impurities are activated by spike annealing at about 1050 ° C.

  Thereafter, a metal film (not shown) made of, for example, Ni is formed over the entire area of the SOI substrate 11 in this state by, for example, sputtering, and then heat treatment is performed, so that the surface of the gate electrode 16 and the surface of the epitaxial growth layer 22 Is silicided to form a silicide layer 25.

  Even in such a semiconductor device manufacturing method and semiconductor device, the SOI substrate 11 is dug until the lowermost Si layer 11a is exposed by etching using the gate electrode 16 provided with the sidewall 20 as a mask. Since the source / drain region 23 is formed in the epitaxial growth layer 22 formed on the surface of the Si layer 11a, and the second extension region 19b '' is formed in the epitaxial growth layer 31 ′, the same as in the second embodiment. There is an effect.

  Furthermore, according to the present embodiment, the epitaxial growth layer 31 ′ provided with the second extension region 19b ″ has a facet shape, thereby reducing the fringe capacitance between the second extension region 19b ″ and the gate electrode 16. be able to.

FIG. 6 is a manufacturing process cross-sectional view (No. 1) for describing the first embodiment of the semiconductor device manufacturing method of the present invention; FIG. 6 is a manufacturing process sectional view (No. 2) for describing the first embodiment of the manufacturing method of the semiconductor device of the invention; It is manufacturing process sectional drawing (the 3) for demonstrating 1st Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows the other example of the sidewall in 1st Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows the other example of the epitaxial growth layer in 1st Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which shows the other example of the extension area | region in 1st Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing for demonstrating 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing for demonstrating the modification 1 of 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device.

Explanation of symbols

11 ... SOI substrate, 11a, 11c ... Si layer, 11b ... SiO ₂ layer, 15 ... gate insulating film, 16 ... gate electrode, 19, 19 ', 19''... extension regions, 20, 20', 20 '' ... Side walls, 22, 22 ', 31, 31' ... epitaxial growth layers, 23 ... source / drain regions

Claims (8)

A first step of forming a gate electrode through a gate insulating film on an SOI substrate in which a silicon layer, an insulating layer, and a silicon layer are stacked in this order;
A second step of digging the SOI substrate until the lowermost silicon layer is exposed by etching using the gate electrode as a mask;
And a third step of epitaxially growing a silicon-containing layer on the exposed surface of the silicon layer and forming a source / drain region in the silicon-containing layer. In the manufacturing method of the semiconductor device according to claim 1,
Between the first step and the second step,
After performing a step of forming extension regions on the surface layer of the SOI substrate on both sides of the gate electrode, performing a step of forming sidewalls on both sides of the gate insulating film and the gate electrode,
In the second step,
A method of manufacturing a semiconductor device, wherein the SOI substrate is dug down by etching using the gate electrode provided with the sidewall as a mask. The method of manufacturing a semiconductor device according to claim 2.
In the step of forming the extension region, a silicon-containing layer is epitaxially grown on the SOI substrate, and the extension region is formed in the silicon-containing layer and the surface layer of the SOI substrate. Method. The method for manufacturing a semiconductor device according to claim 3, wherein the silicon-containing layer provided with the extension region is formed so that a side surface thereof has a facet shape inclined with respect to a surface of the SOI substrate. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
Between the first step and the second step,
After epitaxially growing a silicon-containing layer on the SOI substrate on both sides of the gate electrode and forming an extension region on the silicon-containing layer, sidewalls are formed on both sides of the gate insulating film and the gate electrode. Perform the process to
In the second step,
A method of manufacturing a semiconductor device, wherein the SOI substrate is dug down by etching using the gate electrode provided with the sidewall as a mask. In the manufacturing method of the semiconductor device according to claim 1,
In the third step, the silicon-containing layer containing impurities is epitaxially grown. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the silicon-containing layer is a mixed crystal layer including silicon and atoms having different lattice constants. In a semiconductor device in which a gate electrode is provided via a gate insulating film on an SOI substrate in which a silicon layer, an insulating layer, and a silicon layer are stacked in this order.
A silicon-containing layer formed by epitaxial growth is provided on a region where the SOI substrate on both sides of the gate electrode is dug until the lowermost silicon layer is exposed,
A semiconductor device, wherein a source / drain region is provided in the silicon-containing layer.

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