CN109585546A - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
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- CN109585546A CN109585546A CN201710907139.8A CN201710907139A CN109585546A CN 109585546 A CN109585546 A CN 109585546A CN 201710907139 A CN201710907139 A CN 201710907139A CN 109585546 A CN109585546 A CN 109585546A
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
一种半导体器件及其形成方法，其中方法包括：提供基底；在基底上形成介质层，介质层中具有贯穿介质层的第一栅开口；在第一栅开口底部形成第一界面层；在第一栅开口的侧壁和底部形成第一栅介质层，第一栅介质层位于第一界面层上；对第一界面层进行退火处理；进行退火处理后，在第一栅开口中形成位于第一栅介质层上的第一栅电极层；在第一栅电极层两侧的介质层中形成第一通孔；在第一通孔底部的基底中形成第一源漏掺杂层。所述方法提高了半导体器件的性能。
A semiconductor device and a method for forming the same, wherein the method comprises: providing a substrate; forming a dielectric layer on the substrate, the dielectric layer having a first gate opening penetrating the dielectric layer; forming a first interface layer at the bottom of the first gate opening; A first gate dielectric layer is formed on the sidewall and bottom of a gate opening, and the first gate dielectric layer is located on the first interface layer; the first interface layer is annealed; after the annealing process, a first gate dielectric layer is formed in the first gate opening. A first gate electrode layer on a gate dielectric layer; a first through hole is formed in the dielectric layer on both sides of the first gate electrode layer; a first source-drain doped layer is formed in the substrate at the bottom of the first through hole. The method improves the performance of the semiconductor device.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor devices and forming method thereof.
Background technique
MOS transistor is one of most important element in modern integrated circuits.The basic structure of MOS transistor includes: half
Conductor substrate；Positioned at the gate structure of semiconductor substrate surface；Source region in the semiconductor substrate of gate structure side；It is located at
Drain region in the semiconductor substrate of the gate structure other side.
The working principle of MOS transistor is: by applying voltage in gate structure, adjusting the electricity of gate structure bottom channel
Stream generates switching signal.
However, the performance for the semiconductor devices that the MOS transistor that the prior art is formed is constituted is poor.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor devices and forming method thereof, to improve the property of semiconductor devices
Energy.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, comprising: provide substrate；In base
Dielectric layer is formed on bottom, and there is the first grid through the dielectric layer to be open in dielectric layer；The is formed in first grid open bottom
One boundary layer；The first gate dielectric layer being located on the first boundary layer is formed in the side wall of first grid opening and bottom；To the first boundary
Surface layer is made annealing treatment；After being made annealing treatment, the first grid being located on the first gate dielectric layer is formed in first grid opening
Electrode layer；First through hole is formed in the dielectric layer of first gate electrode layer two sides；Is formed in the substrate of first through hole bottom
One source and drain doping layer.
Optionally, the material of first boundary layer includes silica；It includes wet for forming the technique of first boundary layer
Method oxidation technology.
Optionally, it is 25 degrees Celsius~200 degrees Celsius that the parameter of the wet process oxidation technology, which includes: temperature,.
Optionally, first interfacial layer thickness is 8 angstroms~10 angstroms.
Optionally, it includes oxygen or nitrogen that the parameter of the annealing, which includes: the gas of use, and temperature is 800 Celsius
~1000 degrees Celsius of degree.
Optionally, after forming first boundary layer, and before carrying out the annealing, the first grid is formed
Dielectric layer, the material of first gate dielectric layer are high K dielectric material.
Optionally, first gate dielectric layer with a thickness of 10 angstroms~20 angstroms.
Optionally, the interval between the technique of first boundary layer and the technique of formation first gate dielectric layer is formed
Time was less than 2 hours.
Optionally, further includes: before carrying out the annealing, formed in the side wall of first grid opening and bottom
Positioned at the first coating of first grid dielectric layer surface.
Optionally, the material of first coating includes TiN or TaN.
Optionally, the method for forming the first source and drain doping layer includes: the shape in the substrate of the first through hole bottom
At the first recess；The one source and drain doping layer of extension growth regulation in first recess.
Optionally, the opening size of first recess is greater than the opening size of the first through hole.
Optionally, it in the extending direction perpendicular to first gate electrode layer and is parallel on the direction on base top surface, institute
First through hole is stated with first size, first recess has the second size, second 1.2 times having a size of first size~
1.5 again.
Optionally, there is the first channel region in the substrate of first gate electrode layer bottom；The first source and drain doping layer
Stress is generated to the first channel region.
Optionally, when the corresponding transistor types of the first gate electrode layer are N-type, the first source and drain doping layer is right
First channel region generates tensile stress；When the corresponding transistor types of the first gate electrode layer are p-type, first source and drain is mixed
Diamicton generates compression to the first channel region.
Optionally, the substrate includes the firstth area and the secondth area；The dielectric layer is located in the firstth area of substrate and the secondth area；
The first grid opening runs through first area's dielectric layer；In the dielectric layer also there is the second gate through second area's dielectric layer to open
Mouthful；The forming method of the semiconductor devices further include: before carrying out the annealing, formed in second gate open bottom
Second interface layer；The second gate dielectric layer being located in second interface layer is formed in the side wall of second gate opening and bottom；Carry out institute
After stating annealing, the second gate electrode layer being located on the second gate dielectric layer is formed in second gate opening；Form second gate
After electrode layer, the first through hole is formed；After forming the first source and drain doping layer, first is formed in the first through hole and is filled out
Fill layer；After forming the first filled layer, the second through-hole is formed in the dielectric layer of the second gate electrode layer two sides；In the second via bottoms
Substrate in form the second source and drain doping layer.
Optionally, the material of first filled layer includes silica；The technique for forming the material of first filled layer
Including atom layer deposition process.
Optionally, after forming the second interface layer, and before carrying out the annealing, the second gate is formed
Dielectric layer；The forming method of the semiconductor devices further include: before carrying out the annealing, be open in the second gate
Side wall and bottom formed be located at second gate dielectric layer surface the second coating.
Optionally, there is the second channel region in the substrate of second gate electrode layer bottom；When the first gate electrode layer
When corresponding transistor types are p-type, when the corresponding transistor types of second gate electrode layer are N-type, second source and drain
Doped layer generates tensile stress to the second channel region；When the corresponding transistor types of the first gate electrode layer are N-type, when described
When the corresponding transistor types of second gate electrode layer are p-type, the second source and drain doping layer generates compression to the second channel region.
The present invention also provides a kind of semiconductor devices formed using the above method.
Compared with prior art, technical solution of the present invention has the advantage that
In the forming method for the semiconductor devices that technical solution of the present invention provides, first boundary layer is for repairing first
The substrate surface of grid open bottom makes annealing treatment the first boundary layer to densify the first boundary layer, to reduce by first
The probability to leak electricity between gate electrode layer and substrate.And to the temperature of the annealing of the first boundary layer progress relative to the first source and drain
The ability to bear of doped layer is higher.Since the first source and drain doping layer is formed after carrying out the annealing, it is avoided that
The performance of first source and drain doping layer is influenced by the high temperature of the annealing, to improve the performance of semiconductor devices.
Further, there is the first channel region, the first source and drain doping layer is to the in the substrate of first gate electrode layer bottom
One channel region generates stress, to improve the mobility of carrier in the first channel region.Since the first source and drain doping layer is carrying out institute
State annealing after formed, therefore can be avoided the first source and drain doping layer is generated during the annealing expansion with
It shrinks, and then the first source and drain doping layer is avoided to incur loss the stress of the first channel region in the annealing, avoid the
Carrier mobility declines in one gate electrode layer bottom channel area.
Further, it after forming first boundary layer, and before carrying out the annealing, is opened in the first grid
First gate dielectric layer is formed on the side wall of mouth and bottom, forms the technique of first boundary layer and forms first gate dielectric layer
Technique between interval time less than 2 hours.Avoid the first boundary layer in the technique and formation first for forming the first boundary layer
Grown in the process gap of gate dielectric layer it is blocked up, to meet the requirement of technological design.
Further, it before carrying out the annealing, is formed in the side wall of first grid opening and bottom and is located at the
First coating on one gate dielectric layer surface, avoids the first gate dielectric layer from being exposed in the process gas of the annealing, into
And it avoids forming defect in the first gate dielectric layer.
Detailed description of the invention
Fig. 1 to Figure 10 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
Specific embodiment
As described in background, the performance for the semiconductor devices that the prior art is formed is poor.
A kind of forming method of semiconductor devices, comprising: substrate is provided；Dummy gate structure is formed on the substrate；In pseudo- grid
Source and drain doping layer is formed in the substrate of pole structure two sides；After forming source and drain doping layer, covering dummy gate structure is formed on the substrate
The dielectric layer of side wall；After forming dielectric layer, dummy gate structure is removed, forms grid opening in the dielectric layer；In grid open bottom shape
At boundary layer；Boundary layer is made annealing treatment；Boundary layer is formed, forms gate electrode layer in grid opening.
However, the performance for the semiconductor devices that the above method is formed is poor, it has been investigated that, reason is:
Boundary layer is made annealing treatment to densify boundary layer, thus reduce leak electricity between gate electrode layer and substrate it is several
Rate.The source and drain doping layer is stressor layers.Source and drain doping layer generates stress to channel region, to improve moving for carrier in channel region
Shifting rate.The source and drain doping layer is formed using epitaxial growth technology.And the temperature made annealing treatment to boundary layer is higher, is greater than
The temperature that source and drain doping layer epitaxially grown needs.
Since the step of forming source and drain doping layer, carries out before making annealing treatment to boundary layer, source and drain doping layer
The high temperature that will receive the annealing influences.During by the annealing, source and drain doping layer generate expansion and
It shrinks, and then source and drain doping layer is caused to incur loss the stress of channel region in the annealing, cause to carry in channel region
Flow transport factor decline.
To sum up, cause the performance of semiconductor devices poor.
On this basis, the present invention provides a kind of forming method of semiconductor devices, comprising: in first grid open bottom shape
At the first boundary layer；The first gate dielectric layer being located on the first boundary layer is formed in the side wall of first grid opening and bottom；To
One boundary layer is made annealing treatment；Later, the first gate electrode layer being located on the first gate dielectric layer is formed in first grid opening；
First through hole is formed in the dielectric layer of first gate electrode layer two sides；The first source and drain is formed in the substrate of first through hole bottom to mix
Diamicton.The method improves the performance of semiconductor devices.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 to Figure 10 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
With reference to Fig. 1, substrate is provided.
It is that example is illustrated by fin formula field effect transistor of the semiconductor devices, correspondingly, base in the present embodiment
Bottom includes semiconductor substrate 100 and the fin 110 in semiconductor substrate 100.In other embodiments, the semiconductor device
Part is the MOS transistor of plane formula, correspondingly, substrate is the semiconductor substrate of plane formula.
In the present embodiment, the material of the semiconductor substrate 100 is monocrystalline silicon.The semiconductor substrate 100 can also be
Polysilicon or amorphous silicon.The material of the semiconductor substrate 100 can also be the semiconductor materials such as germanium, SiGe, GaAs.
In the present embodiment, the fin 110 is formed by the graphical semiconductor substrate 100.In other embodiments
In, it may is that formation fin material layer on the semiconductor substrate, then the graphical fin material layer, to be formed
Fin.In the present embodiment, the material of fin 110 is monocrystalline silicon.In other embodiments, the material of fin be monocrystalline germanium silicon or
Other semiconductor materials.
In the present embodiment, also there is isolation structure 101 in the semiconductor substrate 100, the isolation structure 101 covers fin
The partial sidewall surface in portion 110.The material of the isolation structure 110 includes silica.
In the present embodiment, substrate includes the first area A and the second area B, the type for the transistor that the first area A is used to form and the
The type for the transistor that two area B are used to form is opposite.Substrate the firstth area A and the second area B all have fin 110.In the present embodiment,
It is used to form P-type transistor with the first area A, the second area B is used to form N-type transistor and is illustrated for example.
In other embodiments, substrate only includes the firstth area.
It continues to refer to figure 1, dielectric layer 120 is formed on the substrate, has first through dielectric layer 120 in dielectric layer 120
Grid opening 121.
The material of the dielectric layer 120 includes silica.
In the present embodiment, the dielectric layer 120 is located on substrate the firstth area A and the second area B.The first grid opening 121
Through first area's medium A floor 120.In the present embodiment, also have the through second area's medium B floor 120 in the dielectric layer 120
Two grid opening 122.
Specifically, forming the first dummy gate structure on the firstth area of substrate A；It is formed on the secondth area of substrate B
Second dummy gate structure；The first dummy gate structure of covering and the second dummy gate structure are formed on substrate the firstth area A and the second area B
The dielectric layer 120 of side wall, and dielectric layer 120 exposes the top surface of the first dummy gate structure and the top of the second dummy gate structure
Portion surface；After forming dielectric layer 120, the first dummy gate structure is removed, forms first grid opening 121, removal in dielectric layer 120
Second dummy gate structure forms second gate opening 122 in dielectric layer 120.
In one embodiment, the method for forming the dielectric layer 120 includes: that the first dummy grid of covering is formed on the substrate
The underlying dielectric layer of structure division side wall and the second dummy gate structure partial sidewall；It is pseudo- that covering first is formed in underlying dielectric layer
The top layer dielectric layer of gate structure partial sidewall and the second dummy gate structure partial sidewall, top layer dielectric layer expose the first pseudo- grid
Pole structural top surface and the second dummy gate structure top surface, the density of top layer dielectric layer are greater than the density of underlying dielectric layer.
The method for forming the underlying dielectric layer includes: in substrate, the first dummy gate structure and the second dummy gate structure
Bottom dielectric film is formed, planarization bottom dielectric film is until expose the first dummy gate structure top surface and the second dummy grid knot
Structure top surface；After planarizing bottom dielectric film, it is etched back to bottom dielectric film, bottom dielectric film is made to form underlying dielectric layer.Shape
Technique at the bottom dielectric film includes fluid chemistry gas-phase deposition.
The method for forming the top layer dielectric layer includes: pseudo- in the underlying dielectric layer, the first dummy gate structure and second
Top layer deielectric-coating is formed on gate structure；Planarization top layer deielectric-coating is until expose the first dummy gate structure top surface and the
Two dummy gate structure top surfaces.The technique for forming the top layer deielectric-coating includes high density plasma CVD work
Skill.
In the present embodiment, the first dummy gate structure covers the first area A across first area's A fin 110, the first dummy gate structure
The atop part surface and partial sidewall surface of fin 110, the second dummy gate structure is across second area's B fin 110, the second pseudo- grid
Pole structure covers the atop part surface and partial sidewall surface of second area's B fin 110.121 bottoms correspondingly, the first grid is open
First area's A fin 110 is exposed, second gate 122 bottom-exposeds of opening go out second area's B fin 110.
In the present embodiment, further includes: before forming dielectric layer 120, carried out to the substrate of the first dummy gate structure two sides
First is lightly doped injection, forms the first lightly doped district in the substrate of the first dummy gate structure two sides, specifically, in the first pseudo- grid
The first lightly doped district is formed in the fin 110 of pole structure two sides；Second is carried out to the substrate of the second dummy gate structure two sides gently to mix
Pragma enters, and forms the second lightly doped district in the substrate of the second dummy gate structure two sides, specifically, in the second dummy gate structure two
The second lightly doped district is formed in the fin 110 of side；Before forming dielectric layer 120, the first lightly doped district and second are lightly doped
Area anneals, to activate the ion in the first lightly doped district and the second lightly doped district.First lightly doped district and second are gently mixed
The temperature that miscellaneous area anneals is 1200 degrees Celsius~1300 degrees Celsius, such as 1250 degrees Celsius.
With reference to Fig. 2, the first boundary layer 131 is formed in 121 bottoms of first grid opening；The first grid opening 121 side wall and
The first gate dielectric layer 141 being located on the first boundary layer 131 is formed on bottom.
The material of first boundary layer 131 includes silica.
The technique for forming first boundary layer 131 includes wet process oxidation technology.
It is 25 degrees Celsius~200 Celsius that the parameter for forming the wet process oxidation technology of first boundary layer 131, which includes: temperature,
Degree, the solution of use includes ozone water solution.
Under the Parameter Conditions of above-mentioned wet process oxidation technology, the first boundary layer 131 can grow tool in ozone water solution
There is saturation thickness, the thickness of the first boundary layer 131 will not be with time indeterminate growth, therefore is conducive to preferably control the first boundary
The thickness of surface layer 131.
First boundary layer 131 is located at the substrate surface of 121 bottoms of first grid opening, specifically, the first boundary layer 131
Positioned at 110 surface of fin of 121 bottoms of first grid opening.
The effect of first boundary layer 131 includes: the substrate surface for repairing 121 bottoms of first grid opening, specifically, repairing
First area's A fin, 110 surface of 121 bottoms of multiple first grid opening.
In the present embodiment, the first boundary layer 131 with a thickness of 8 angstroms~10 angstroms.If the thickness of the first boundary layer 131 is blocked up,
Cause the threshold voltage of first area's A transistor excessive, and driving current is smaller；If the thickness of the first boundary layer 131 is excessively thin, cause
The ability for repairing first area's A fin 110 of 121 bottoms of first grid opening is poor.
In the present embodiment, after forming first boundary layer 131, and before subsequent made annealing treatment, described
First gate dielectric layer 141 is formed on the side wall of first grid opening 121 and bottom.
The material of first gate dielectric layer 141 is high K (K is greater than 3.9) dielectric material.
In the present embodiment, the first gate dielectric layer 141 is also located on first area's medium A floor 120.
In the present embodiment, the technique of first boundary layer 131 and the technique of formation first gate dielectric layer 141 are formed
Between interval time less than 2 hours, be advantageous in that: avoid the first boundary layer 131 formed the first boundary layer 131 technique and
Formed in the process gap of the first gate dielectric layer 141 grow it is blocked up, to meet the requirement of technological design.
In other embodiments, after subsequent made annealing treatment, in the side wall and bottom shape of first grid opening
At the first gate dielectric layer.
In the present embodiment, further includes: before subsequent made annealing treatment, the first grid opening 121 side wall and
The first coating 151 for being located at 141 surface of the first gate dielectric layer is formed on bottom.
The material of first coating 151 includes TiN or TaN.
The effect of first coating 151 includes: the work for avoiding the first gate dielectric layer 141 from being exposed to subsequent anneal processing
In skill gas, and then avoid forming defect in the first gate dielectric layer 141；And first coating 151 can be with subsequent first function
Function floor adjusts the threshold voltage of first area's A transistor jointly.
In one embodiment, first coating 151 with a thickness of 10 angstroms~40 angstroms.
In the present embodiment, the first coating 151 is located at 141 surface of the first gate dielectric layer.
In other embodiments, the first coating is not formed.
In the present embodiment, further includes: before subsequent made annealing treatment, form second in 122 bottoms of second gate opening
Boundary layer 132.
The technique for forming the second interface layer 132 includes wet process oxidation technology.
It is 25 degrees Celsius~200 Celsius that the parameter for forming the wet process oxidation technology of the second interface layer 132, which includes: temperature,
Degree, the solution of use includes ozone water solution.
Under the Parameter Conditions of above-mentioned wet process oxidation technology, second interface layer 132 can grow tool in ozone water solution
There is saturation thickness, the thickness of second interface layer 132 will not be with time indeterminate growth, therefore is conducive to preferably control the second boundary
The thickness of surface layer 132.
In the present embodiment, forms the second interface layer 132 and aoxidized with formation first boundary layer 131 using with along with
Technique simplifies technique.
The second interface layer 132 is located at the substrate surface of 122 bottoms of second gate opening, specifically, second interface layer 132
Positioned at 110 surface of fin of 122 bottoms of second gate opening.
The effect of the second interface layer 132 includes: the substrate surface for repairing 122 bottoms of second gate opening, specifically, repairing
Second area's B fin, 110 surface of 122 bottoms of multiple second gate opening.
In the present embodiment, second interface layer 132 with a thickness of 8 angstroms~10 angstroms.If the thickness of second interface layer 132 is blocked up,
Cause the threshold voltage of second area's B transistor excessive, and driving current is smaller；If the thickness of second interface layer 132 is excessively thin, cause
The ability for repairing second area's B fin 110 of 122 bottoms of second gate opening is poor.
In the present embodiment, the first boundary layer 131 and second interface layer 132 are formed in same technique, simplify technique.
In the present embodiment, further includes: after forming the second interface layer 132, and before subsequent made annealing treatment,
The second gate dielectric layer 142 being located in second interface layer 132 is formed in the side wall of second gate opening 122 and bottom.
The material of second gate dielectric layer 142 is high K (K is greater than 3.9) dielectric material.In the present embodiment, second gate is situated between
Matter floor 142 is also located on second area's medium B floor 120.In the present embodiment, is formed while forming the first gate dielectric layer 141
Two gate dielectric layers 142, simplify technique.
In the present embodiment, the technique of the second interface layer 132 and the technique of formation second gate dielectric layer 142 are formed
Between interval time less than 2 hours, be advantageous in that: avoid second interface layer 132 formed second interface layer 132 technique and
Formed in the process gap of the second gate dielectric layer 142 grow it is blocked up, to meet the requirement of technological design.
In other embodiments, after subsequent made annealing treatment, in the side wall and bottom shape of second gate opening
At the second gate dielectric layer.
In the present embodiment, further includes: before subsequent made annealing treatment, the second gate opening 122 side wall and
The second coating 152 for being located at 142 surface of the second gate dielectric layer is formed on bottom.
The material of second coating 152 includes TiN or TaN.
The effect of second coating 152 includes: the work for avoiding the second gate dielectric layer 142 from being exposed to subsequent anneal processing
In skill gas, and then avoid forming defect in the second gate dielectric layer 142；And second coating 152 can be with subsequent second function
Function floor adjusts the threshold voltage of second area's B transistor jointly.
In one embodiment, second coating 152 with a thickness of 10 angstroms~40 angstroms.
In the present embodiment, the second coating 152 is located at 142 surface of the second gate dielectric layer.
In the present embodiment, the second coating 152 is formed while forming the first coating 151, simplifies technique.At it
In its embodiment, the second coating is not formed.
With reference to Fig. 3, the first boundary layer 131 is made annealing treatment.
The effect of the annealing includes: the first boundary layer 131 of densification, to reduce by 141 He of first gate electrode layer
The probability to leak electricity between substrate.
The parameter of the annealing includes: that the gas of use includes oxygen or nitrogen, and temperature is 800 degrees Celsius~1000
Degree Celsius, such as 900 degrees Celsius.
In the present embodiment, the annealing also acts on second interface layer 132, densifies second interface layer 132.The
After second interface layer 132 densifies, the probability to leak electricity between the second gate electrode layer 142 and substrate can reduce.
In the present embodiment, before annealing, the first coating 151 is formd, avoids the exposure of the first gate dielectric layer 141
In the process gas of annealing, and then avoid forming defect in the first gate dielectric layer 141；Before annealing, shape
At the second coating 152, the second gate dielectric layer 142 is avoided to be exposed in the process gas of annealing, and then avoided
Defect is formed in two gate dielectric layers 142.
In one embodiment, the first gate dielectric layer 141 with a thickness of 10 angstroms~20 angstroms, such as 12 angstroms or 15 angstroms；If first
A corresponding crystallite dimension is the first critical dimension after 141 crystallization of gate dielectric layer, then due to the thickness of the first gate dielectric layer 141
Degree is less than or close to the first critical dimension, therefore the material of the first gate dielectric layer 141 is not easy to be crystallized at a high temperature of certain, i.e.,
The ability of first gate dielectric layer, 141 bearing temperature improves.In the case, when the first gate dielectric layer 141 is in the annealing
When being formed before, 141 material of the first gate dielectric layer is also able to maintain unformed without being crystallized, and avoids leaking electricity.
In one embodiment, the second gate dielectric layer 142 with a thickness of 10 angstroms~20 angstroms, such as 12 angstroms or 15 angstroms.If second
A corresponding crystallite dimension is the second critical dimension after 142 crystallization of gate dielectric layer, then due to the thickness of the second gate dielectric layer 142
Degree is less than or close to the second critical dimension, therefore the material of the second gate dielectric layer 142 is not easy to be crystallized at a high temperature of certain, i.e.,
The ability of second gate dielectric layer, 142 bearing temperature improves.In the case, when the second gate dielectric layer 142 is in the annealing
When being formed before, 142 material of the second gate dielectric layer is also able to maintain unformed without being crystallized, and avoids leaking electricity.
In the present embodiment, when forming the first gate dielectric layer 141 and the second gate dielectric layer 142 before annealing, if
The gas that annealing uses includes O2When, it is advantageous in that: a small amount of O2It diffuses between the first boundary layer 131 and first area's A substrate
Interface, specifically, a small amount of O2The interface between the first boundary layer 131 and first area's A fin 110 is diffused to, at the first interface
The very thin oxide layer of a floor is formed between floor 131 and first area's A substrate, specifically with a thickness of 2 angstroms~5 angstroms, thereby reduces the
Interfacial state between one boundary layer 131 and first area's A substrate；A small amount of O2Diffuse to second interface layer 132 and second area's B substrate it
Between interface, specifically, a small amount of O2The interface between second interface layer 132 and second area's B fin 110 is diffused to, on the second boundary
The very thin oxide layer of a floor is formed between surface layer 132 and second area's B substrate to thereby reduce specifically with a thickness of 2 angstroms~5 angstroms
Interfacial state between second interface layer 132 and second area's B substrate.
With reference to Fig. 4, after being made annealing treatment, the be located on the first gate dielectric layer 141 is formed in first grid opening 121
One gate electrode layer 161.
The material of the first gate electrode layer 161 is metal, such as tungsten.
The first gate electrode floor 161 is also located on first area's medium A floor 120.
In the present embodiment, further includes: after carrying out the annealing, formed in second gate opening 122 and be located at second
The second gate electrode layer 162 on gate dielectric layer 142.
The material of second gate electrode layer 162 is metal, such as tungsten.
Second gate electrode layer 162 is also located on second area's medium B floor 120.
In the present embodiment, first gate electrode layer 161 and the second gate electrode layer 162 are formed in same technique, simplify work
Skill.
In the present embodiment, first gate electrode layer 161 is on the first gate dielectric layer 141 and the first coating 151.Second gate electricity
Pole layer 162 is on the second gate dielectric layer 142 and the second coating 152.
In the present embodiment, forms the technique of the first gate dielectric layer 141 and form 161 technique of first gate electrode layer to the
One lightly doped district and the second lightly doped district carry out after being annealed, therefore the first gate dielectric layer 141 and first gate electrode layer 161
Without the high temperature being subjected in annealing to the first lightly doped district and the second lightly doped district, therefore avoid because gently being mixed after to first
Technique that miscellaneous area and the second lightly doped district are annealed and cause first area's A transistor threshold voltage to improve.
In the present embodiment, forms the technique of the second gate dielectric layer 142 and form 162 technique of the second gate electrode layer to the
One lightly doped district and the second lightly doped district carry out after being annealed, therefore the second gate dielectric layer 142 and the second gate electrode layer 162
Without the high temperature being subjected in annealing to the first lightly doped district and the second lightly doped district, therefore avoid because gently being mixed after to first
Technique that miscellaneous area and the second lightly doped district are annealed and cause second area's B transistor threshold voltage to improve.
With reference to Fig. 5, first gate electrode layer 161 and the first gate dielectric layer 141 are planarized until exposing the top of dielectric layer 120
Portion surface.
The technique for planarizing first gate electrode layer 161 and the first gate dielectric layer 141 includes chemical mechanical milling tech.
Specifically, planarization first gate electrode layer 161, the first coating 151 and the first gate dielectric layer 141 are until expose
The top surface of first area's medium A floor 120.
In the present embodiment, further includes: in planarization first gate electrode layer 161, the first coating 151 and the first gate dielectric layer
During 141, the second gate electrode layer 162 of planarization, the second coating 152 and the second gate dielectric layer 142 are until expose the
The top surface of two area's medium B floor 120.
With reference to Fig. 6, first through hole 171 is formed in the dielectric layer 120 of 161 two sides of first gate electrode layer.
In the present embodiment, after forming the second gate electrode layer 162, the first through hole 171 is formed.
The technique for forming the first through hole 171 includes anisotropy dry carving technology.
With reference to Fig. 7, the first source and drain doping layer 181 is formed in the substrate of 171 bottom of first through hole.
The method for forming the first source and drain doping layer 181 includes: to be formed in the substrate of 171 bottom of first through hole
First recess (not shown)；The one source and drain doping layer 181 of extension growth regulation in first recess.
The technological temperature of the first source and drain doping of epitaxial growth layer 181 is 600 degrees Celsius~750 degrees Celsius.
There is the first channel region in the substrate of 161 bottom of first gate electrode layer.
In one embodiment, the opening size of the first recess is greater than the opening size of the first through hole 171.Benefit packet
It includes: first can be made close to the first channel region of first area's A transistor in the first source and drain doping floor 181 of the first concave growth
The stress of 181 pair of first channel region of source and drain doping layer applies abundant；And the edge and first gate electrode layer 161 of first through hole 171
More sufficiently, the technique for forming first through hole 171 is not easy to influence first gate electrode layer 161, first grid Jie at the distance between edge
Matter layer 141 and the first boundary layer 131 can bear the biggish fluctuation range of choice in 171 position of first through hole in process implementing,
Reduce the craft precision requirement to form first through hole 171.
171 opening size of first through hole is smaller, to avoid the adjacent first through hole on 161 extending direction of first gate electrode layer
The thickness of dielectric layer 120 between 171 is excessively thin.In the first recess before extension the first source and drain doping layer, need recessed to first
The fin material for falling into inner wall is started the cleaning processing to remove the oxide thin layer layer of the first recess inner wall, and the oxide layer is in extension
Fin portion surface is exposed in air environment and aoxidizes formation before one source and drain doping layer of growth regulation.Adjacent first through hole 171 it
Between relatively thick dielectric layer 120 be able to bear cleaning treatment cleaning solution impact, avoid between adjacent first through hole 171
Dielectric layer 120 is toppled in cleaning treatment.
In a specific embodiment, in the extending direction perpendicular to first gate electrode layer 161 and it is parallel to substrate top
On the direction on portion surface, the first through hole 171 has first size, and first recess has the second size, the second size
It is 1.2 times~1.5 times of first size.
In the present embodiment, formed described first recess the step of include: etch first through hole bottom substrate, in the firstth area
The first initial recess is formed in substrate；The substrate of the first initial recess side wall is etched to expand the opening of the first initial recess, is made
First initial recess forms first recess.
The first source and drain doping layer, 181 pair of first channel region generates stress.Specifically, working as the first gate electrode layer
When 161 corresponding transistor types are N-type, 181 pair of first channel region of the first source and drain doping layer generates tensile stress；When described
When the corresponding transistor types of first gate electrode layer 161 are p-type, 181 pair of first channel region of the first source and drain doping layer is generated
Compression.To improve carrier mobility in the first channel region.
In the present embodiment, to the first boundary layer 131 carry out annealing temperature relative to the first source and drain doping layer 181
Ability to bear it is higher.Since the first source and drain doping layer 181 is formed after carrying out the annealing, it is avoided that first
The performance of source and drain doping layer 181 is influenced by the high temperature of the annealing, to improve the performance of semiconductor devices.
Specifically, since the first source and drain doping layer 181 is formed after making annealing treatment to the first boundary layer 131, because
This can be avoided the first source and drain doping layer 181 and generates expansion during the annealing and shrink, and then avoid first
The stress of 181 pair of first channel region of source and drain doping layer incurs loss in the annealing, avoids 161 bottom of first gate electrode layer
Carrier mobility declines in portion's channel region.
In the present embodiment, the first source and drain doping layer 181 is formed using epitaxial growth technology, without using ion implanting
Technique is formed, if benefit includes: that the first source and drain doping layer 181 is formed using ion implantation technology, it is also necessary to the first source and drain
Doped layer 181 is annealed to activate the ion in the first source and drain doping layer 181, and if carrying out to the first source and drain doping layer 181
Annealing, the temperature of use are higher than the temperature of the first source and drain doping of epitaxial growth layer 181, and generally 1200 degrees Celsius~1300 is Celsius
Degree degree.During the high temperature annealed to the first source and drain doping layer 181, the first gate dielectric layer and first gate electrode layer are in
To in the annealing of the first source and drain doping layer 181, be easy to cause first area's A transistor threshold voltage improve, first area's A transistor
Driving capability reduces.
The first filled layer is formed in the first through hole 171 after forming the first source and drain doping layer 181 with reference to Fig. 8
191。
The material of first filled layer 191 includes silica.
The technique for forming the material of the first filled layer 191 is depositing operation, such as atom layer deposition process.
In the present embodiment, the process choice atom layer deposition process of the material of the first filled layer 191 is formed, benefit includes:
Make the material of the first filled layer 191 fill the ability in the sidewall bottom region of 171 bottom of first through hole and first through hole 171 compared with
It is good.
In the present embodiment, during forming the atom layer deposition process of the first filled layer 191, if first through hole 171
First filled layer, 191 material at top links together, further includes: etches the top of first through hole 171 using etching technics
First filled layer, 191 material avoids leaving cavity in the first filled layer 191.
With reference to Fig. 9, after forming the first filled layer 191, the is formed in the dielectric layer 120 of 162 two sides of the second gate electrode layer
Two through-holes 172.
The technique for forming second through-hole 172 includes anisotropy dry carving technology.
With reference to Figure 10, the second source and drain doping layer 182 is formed in the substrate of 172 bottom of the second through-hole.
The method for forming the second source and drain doping layer 182 includes: to be formed in the substrate of 172 bottom of the second through-hole
Second recess (not shown)；The two source and drain doping layer 182 of extension growth regulation in second recess.
The technological temperature of the second source and drain doping of epitaxial growth layer 182 is 600 degrees Celsius~750 degrees Celsius.
There is the second channel region in the substrate of second gate electrode layer, 162 bottom.
In one embodiment, the opening size of the second recess is greater than the opening size of second through-hole 172.Benefit packet
It includes: second can be made close to the second channel region of second area's B transistor in the second source and drain doping floor 182 of the second concave growth
The stress of 182 pair of second channel region of source and drain doping layer applies abundant；And second through-hole 172 edge and the second gate electrode layer 162
More sufficiently, the technique for forming the second through-hole 172 is not easy to influence the second gate electrode layer 162, second gate Jie at the distance between edge
Matter layer 142 and second interface layer 132 can bear the biggish fluctuation range of choice in 172 position of the second through-hole in process implementing,
Reduce the craft precision requirement to form the second through-hole 172.
Based on the reason similar with 171 opening size of first through hole, 172 opening size of the second through-hole is smaller, to avoid
The thickness of dielectric layer 120 is excessively thin between adjacent second through-hole 172 on second gate electrode layer, 162 extending direction.Adjacent second through-hole
Thicker dielectric layer 120 is able to bear the impact of the cleaning solution of cleaning treatment between 172, avoids between adjacent second through-hole 172
Dielectric layer 120 topple in cleaning treatment.
In a specific embodiment, in the extending direction perpendicular to the second gate electrode layer 162 and it is parallel to substrate top
On the direction on portion surface, second through-hole 172 has third size, and second recess has the 4th size, the 4th size
It is 1.2 times~1.5 times of third size.
In the present embodiment, formed described second recess the step of include: etch the second via bottoms substrate, in the secondth area
The second initial recess is formed in substrate；The substrate of the second initial recess side wall is etched to expand the opening of the second initial recess, is made
Second initial recess forms second recess.
There is the second channel region in the substrate of second gate electrode layer, 162 bottom；Described 182 pairs of second source and drain doping layer
Second channel region generates stress.Specifically, when the corresponding transistor types of second gate electrode layer 162 are N-type, described the
Two 182 pair second of source and drain doping layer channel regions generate tensile stress；When the corresponding transistor types of second gate electrode layer 162 are
When p-type, 182 pair of second channel region of the second source and drain doping layer generates compression.To improve current-carrying in the second channel region
Transport factor.
In the present embodiment, due to the second source and drain doping layer 182 after being made annealing treatment to second interface layer 132 shape
At, therefore can be avoided the second source and drain doping layer 182 and generate expansion during the annealing and shrink, and then avoid
The stress of second 182 pair of second channel region of source and drain doping layer incurs loss in the annealing, avoids the second gate electrode layer
Carrier mobility declines in 162 bottom channel areas.
In the present embodiment, the second source and drain doping layer 182 is formed using epitaxial growth technology, without using ion implanting
Technique is formed, if benefit includes: that the second source and drain doping layer 182 is formed using ion implantation technology, it is also necessary to the second source and drain
Doped layer 182 is annealed to activate the ion in the second source and drain doping layer 182, and if carrying out to the second source and drain doping layer 182
Annealing, the temperature of use are higher than the temperature of the second source and drain doping of epitaxial growth layer 182, and generally 1200 degrees Celsius~1300 is Celsius
Degree degree.During the high temperature annealed to the second source and drain doping layer 182, the second gate dielectric layer and the second gate electrode layer are in
To in the annealing of the second source and drain doping layer 182, be easy to cause second area's B transistor threshold voltage improve, second area's B transistor
Driving capability reduces.
In the present embodiment, further includes: after forming the second source and drain doping layer 182, form the second filling in the second through-hole 172
Layer.Material and formation process of the material and formation process of second filled layer referring to the first filled layer.
In the present embodiment, further includes: formed the second filled layer after, dielectric layer 120, the first filled layer, the second filled layer,
Top interlayer dielectric layer is formed on first gate electrode layer, the first gate dielectric layer, the second gate electrode layer and the first gate dielectric layer；In top layer
Between dielectric layer, dielectric layer and 120 and first form the first plug open and the second plug open, the first plug open in filled layer
First gate electrode layer two sides are located at, the second plug open is located at the second gate electrode layer two sides, in the first plug open
The first plug of middle formation, is electrically connected in the first plug and the first source and drain doping layer；Second is formed in the second plug open to insert
Plug, the second plug and the second source and drain doping layer are electrically connected.
Correspondingly, the present embodiment also provides a kind of semiconductor devices formed using the above method.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor devices characterized by comprising
Substrate is provided；
Dielectric layer is formed on the substrate, there is the first grid through the dielectric layer to be open in dielectric layer；
The first boundary layer is formed in first grid open bottom；
The first gate dielectric layer being located on the first boundary layer is formed in the side wall of first grid opening and bottom；
First boundary layer is made annealing treatment；
After being made annealing treatment, the first gate electrode layer being located on the first gate dielectric layer is formed in first grid opening；
First through hole is formed in the dielectric layer of first gate electrode layer two sides；
The first source and drain doping layer is formed in the substrate of first through hole bottom.
2. the forming method of semiconductor devices according to claim 1, which is characterized in that the material of first boundary layer
Including silica；The technique for forming first boundary layer includes wet process oxidation technology.
3. the forming method of semiconductor devices according to claim 2, which is characterized in that the ginseng of the wet process oxidation technology
Number includes: that temperature is 25 degrees Celsius~200 degrees Celsius.
4. the forming method of semiconductor devices according to claim 1, which is characterized in that first interfacial layer thickness is
8 angstroms~10 angstroms.
5. the forming method of semiconductor devices according to claim 1, which is characterized in that the parameter packet of the annealing
Include: the gas of use includes oxygen or nitrogen, and temperature is 800 degrees Celsius~1000 degrees Celsius.
6. the forming method of semiconductor devices according to claim 1, which is characterized in that forming first boundary layer
Afterwards, and before carrying out the annealing, first gate dielectric layer is formed, the material of first gate dielectric layer is high K
Dielectric material.
7. the forming method of semiconductor devices according to claim 1 or 6, which is characterized in that first gate dielectric layer
With a thickness of 10 angstroms~20 angstroms.
8. the forming method of semiconductor devices according to claim 6, which is characterized in that form first boundary layer
Interval time between technique and the technique for forming first gate dielectric layer was less than 2 hours.
9. the forming method of semiconductor devices according to claim 6, which is characterized in that further include: it moves back described in the progress
Before fire processing, the first coating for being located at first grid dielectric layer surface is formed in the side wall of first grid opening and bottom.
10. the forming method of semiconductor devices according to claim 9, which is characterized in that the material of first coating
Material includes TiN or TaN.
11. the forming method of semiconductor devices according to claim 1, which is characterized in that form first source and drain and mix
The method of diamicton includes: that the first recess is formed in the substrate of the first through hole bottom；
The one source and drain doping layer of extension growth regulation in first recess.
12. the forming method of semiconductor devices according to claim 11, which is characterized in that the opening of first recess
Size is greater than the opening size of the first through hole.
13. the forming method of semiconductor devices according to claim 12, which is characterized in that perpendicular to first gate electrode
Layer extending direction and be parallel on the direction on base top surface, the first through hole have first size, described first is recessed
Falling into has the second size, the second 1.2 times~1.5 times having a size of first size.
14. the forming method of semiconductor devices according to claim 1, which is characterized in that first gate electrode layer bottom
There is the first channel region in the substrate in portion；The first source and drain doping layer generates stress to the first channel region.
15. the forming method of semiconductor devices according to claim 14, which is characterized in that when the first gate electrode layer
When corresponding transistor types are N-type, the first source and drain doping layer generates tensile stress to the first channel region；When the first grid
When the corresponding transistor types of electrode layer are p-type, the first source and drain doping layer generates compression to the first channel region.
16. the forming method of semiconductor devices according to claim 1, which is characterized in that the substrate includes the firstth area
With the secondth area；The dielectric layer is located in the firstth area of substrate and the secondth area；The first grid opening runs through first area's dielectric layer；Institute
Stating in dielectric layer, also there is the second gate through second area's dielectric layer to be open；The forming method of the semiconductor devices further include:
Before carrying out the annealing, second interface layer is formed in second gate open bottom；Side wall and bottom in second gate opening
Portion forms the second gate dielectric layer being located in second interface layer；After carrying out the annealing, formed in second gate opening
The second gate electrode layer on the second gate dielectric layer；After forming the second gate electrode layer, the first through hole is formed；Described in formation
After first source and drain doping layer, the first filled layer is formed in the first through hole；After forming the first filled layer, in the second gate electrode
The second through-hole is formed in the dielectric layer of layer two sides；The second source and drain doping layer is formed in the substrate of the second via bottoms.
17. the forming method of semiconductor devices according to claim 16, which is characterized in that the material of first filled layer
Material includes silica；The technique for forming the material of first filled layer includes atom layer deposition process.
18. the forming method of semiconductor devices according to claim 16, which is characterized in that forming the second contact surface
After layer, and before carrying out the annealing, second gate dielectric layer is formed；The forming method of the semiconductor devices is also
It include: to be formed in the side wall of second gate opening and bottom before carrying out the annealing and be located at the second gate dielectric layer
Second coating on surface.
19. the forming method of semiconductor devices according to claim 16, which is characterized in that second gate electrode layer bottom
There is the second channel region in the substrate in portion；When the corresponding transistor types of the first gate electrode layer are p-type, the second gate
When the corresponding transistor types of electrode layer are N-type, the second source and drain doping layer generates tensile stress to the second channel region；When described
When the corresponding transistor types of first gate electrode layer are N-type, when the corresponding transistor types of second gate electrode layer are p-type
When, the second source and drain doping layer generates compression to the second channel region.
20. a kind of according to claim 1 to the semiconductor devices that 19 any one methods are formed.
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