CN105590846A - Method for forming semiconductor structure - Google Patents

Abstract

The invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a semiconductor substrate; forming first and second gate stack structures over the semiconductor substrate; forming first and second recesses in the semiconductor substrate; performing a selective growth step to grow a semiconductor material in the first recess and the second recess to simultaneously and respectively form first and second epitaxial regions; and after the selective growth step, performing a selective etch back step on the first and second epitaxial regions, wherein the selective etch back step is performed using a process gas comprising a first gas for growing the semiconductor material and a second gas for etching the first and second epitaxial regions. The invention can reduce the pattern load effect by the selective back etching step so as to form a more uniform epitaxial region and improve the outline of the epitaxial region. The facet of the epi region may be reduced or even eliminated.

Description

Formation method of semiconductor structure

This application is a divisional application of an invention patent application with a filing date of November 12, 2010, an application number of 201010547530.X, and an invention title of "Method for Forming a Semiconductor Structure".

technical field

The invention relates to a method for forming a semiconductor structure, in particular to a selective etching method when forming an epitaxial region of a metal-oxide-semiconductor (MOS) element.

Background technique

In order to enhance the performance of metal-oxide-semiconductor devices (hereinafter referred to as MOS devices), stressors can be introduced into the channel region of the MOS devices to improve carrier mobility. Generally speaking, it is desirable to introduce a tensile stressor in the channel region of an n-type MOS device (hereinafter referred to as NMOS device) and in the direction from source to drain, and to introduce a tensile stressor in a p-type MOS device (hereinafter referred to as PMOS) In the channel region of the device, a compressive stressor is introduced in the source-to-drain direction.

A common method for applying compressive stressors in the channel region of a PMOS device is to grow SiGe stressors in the source and drain regions. This method generally includes the following steps: forming a gate stack structure on a silicon substrate, forming a gate spacer on the sidewall of the gate stack structure, forming a recess in the silicon substrate adjacent to the gate spacer , and epitaxially grow silicon germanium stressors in the above-mentioned recesses. An annealing step is then performed. Since the lattice constant of silicon germanium is larger than that of silicon, silicon germanium stretches after the annealing step and applies a compressive stress to the channel region of the respective MOS device located in a source silicon between the germanium stressor and the drain silicon germanium stressor.

A chip can have different regions with different pattern densities. Due to the pattern loading effect, SiGe stressors grown in different regions have different growth rates. As an example, FIG. 1 shows the formation of silicon germanium regions for PMOS devices in logic device region 300 and static access memory device (SRAM) region 400 . Because the pattern density of the PMOS elements in the static access memory element (SRAM) region 400 is usually higher than the pattern density of the PMOS elements in the logic element region 300, and the size of the SiGe region 410 is usually smaller than that of the SiGe region 310. size, so the growth rate of the SiGe region 410 is faster than that of the SiGe region 310 . As a result, the height H2 of the portion of the SiGe region 410 above the top surface of the substrate 320 may be significantly higher than the height H1 of the portion of the SiGe region 310 above the top surface of the substrate 320 . For example, even if SiGe regions 310 and 410 are formed at the same time, height H2 may be about 20 nm, and height H1 may only be about 5 nm. Since the SiGe region 410 has a large height H2 and a small size, the SiGe region 410 may have a pyramid-shaped top, and the slope of the top may lie on a (111) lattice plane. Such SiGe regions with pyramidal tops create significant problems in subsequent process steps such as the formation of source and drain silicide regions.

Therefore, in this technical field, there is a need for a method for forming a semiconductor structure to overcome the disadvantages of the known techniques.

Contents of the invention

In view of this, an embodiment of the present invention provides a method for forming a semiconductor structure, including forming a gate stack structure above a semiconductor substrate; forming a recess in the semiconductor substrate adjacent to the gate stack structure; performing a selective growth step to grow a semiconductor material in the above-mentioned recess to form an epitaxial region; after performing the above-mentioned selective growth step, performing a selective etch-back step on the above-mentioned epitaxial region, wherein the A process gas of a first gas for semiconductor material and a second gas for etching the epitaxial region performs the selective etch-back step.

Other embodiments of the present invention are disclosed as follows.

The present invention also provides a method for forming a semiconductor structure, which includes the following steps: providing a semiconductor substrate, which includes a first part located in a first element region and a second part located in a second element region; A first gate stack structure is formed in the region and above the semiconductor substrate; a second gate stack structure is formed in the second element region and above the semiconductor substrate; a second gate stack structure is formed in the semiconductor substrate adjacent to the first a first recess of the gate stack structure, and forming a second recess adjacent to the second gate stack structure in the semiconductor substrate; performing a selective growth step to simultaneously grow a first recess in the first recess an epitaxial region, and a second epitaxial region is grown in the second recess, and the growth rate of the second epitaxial region is greater than the growth rate of the first epitaxial region; and a selective etch back step is performed to etch back the A second epitaxial region, wherein the selective growing step and the selective etch-back step are performed in situ.

Another method for forming a semiconductor structure of the present invention includes the following steps: providing a substrate, which includes a semiconductor region located on a surface of the substrate; and performing a selective etching back step on the semiconductor region, which performs the selective The etch back step uses a process gas including a first gas for growing a semiconductor material on the semiconductor region and a second gas for etching the semiconductor material to perform the selective etch back step, wherein the first gas And the second gas is selected from the group consisting of germane, hydrogen chloride gas, dichlorosilane and combinations thereof.

In addition, the present invention also provides a method for forming a semiconductor structure, comprising the following steps: providing a semiconductor substrate including a first element region and a second element region; A first gate stack structure and a second gate stack structure are formed above the semiconductor substrate; a first recess and a second recess are respectively formed in the semiconductor substrate of the first element region and the second element region , and the first recess and the second recess are adjacent to the first gate stack structure and the second gate stack structure respectively; a selective growth step is performed to grow in the first recess and the second recess a semiconductor material to simultaneously and separately form a first epitaxial region and a second epitaxial region, and the growth rate of the second epitaxial region is greater than the growth rate of the first epitaxial region; and after performing the selective growth step, the The first epitaxial region and the second epitaxial region are subjected to a selective etch back step using a first gas for growing the semiconductor material and a gas for etching the first epitaxial region and the second epitaxial region The process gas of the second gas performs the selective etch back step.

The present invention also provides a method for forming a semiconductor structure, including the following steps: providing a substrate, which includes a first semiconductor region and a second semiconductor region located on a surface of the substrate; The second semiconductor region is subjected to a selective etch back step, the etching rate of the second semiconductor region is greater than the etching rate of the first semiconductor region, and the selective etch back step is performed using a method comprising the first semiconductor region and the first semiconductor region. A process gas of a first gas for growing a semiconductor material on the second semiconductor region and a second gas for etching the semiconductor material perform the selective etch-back step, wherein the first gas and the second gas are selected from A group consisting of germane GeH4, hydrogen chloride gas HCl, dichlorosilane DCS and combinations of the above.

The embodiment of the present invention can reduce the pattern loading effect by the selective etch back step, so as to form a more uniform epitaxial region (such as SiGe stressor) and improve the profile of the epitaxial region. Facets in the epitaxial region can be reduced or even eliminated. Additionally, the selective growth step and the selective etch-back step can be performed in-situ to minimize additional costs.

Description of drawings

1 is a process cross-sectional view of a conventional integrated circuit structure including PMOS devices, wherein SiGe stressors in different device regions have different heights due to pattern loading effects.

2 to 9 are process cross-sectional views of a method for forming a semiconductor structure according to an embodiment of the present invention, in which a selective etch-back step is performed to reduce the pattern loading effect.

FIG. 10 shows the growth rate of silicon germanium as a function of the ratio of the gas partial pressure of the etching gas to the partial pressure of the growth gas.

Wherein, the reference signs are explained as follows:

1 ~ chip;

2 ~ substrate;

2a～top surface;

4～Shallow trench isolation area;

36～etching stop layer;

100, 200～component area;

101, 201～active area;

102, 202～gate stack structure;

104, 204～gate dielectric;

106, 206 ~ gate;

110, 210～lightly doped source/drain regions;

116, 216～gate spacer;

118, 218 ~ depression;

120, 220 ~ epitaxial area;

130, 230～Silicone-containing coverings;

134, 234～silicide area;

140, 240 ~ contact hole plug;

300～logic element area;

400～Static access storage element area;

310, 410 ~ silicon germanium area;

320～substrate;

502～dummy gate stack structure;

504～dummy gate dielectric;

506～dummy grid;

516～dummy grid spacer;

W1, W2～width;

D ~ depth;

H1, H1', H2, H2'～height;

A, B, C, D ~ range.

detailed description

Hereinafter, each embodiment is described in detail and examples accompanied by accompanying drawings are used as a reference basis of the present invention. In the drawings or descriptions in the specification, the same reference numerals are used for similar or identical parts. And in the drawings, the shapes or thicknesses of the embodiments may be enlarged, and marked for simplicity or convenience. Furthermore, parts of the components in the drawings will be described separately. It should be noted that the components not shown or described in the drawings are forms known to those skilled in the art.

FIG. 2 shows the substrate 2 , which is a part of the wafer 1 . The substrate 2 may include a first portion located in the device area 100 and a second portion located in the device area 200 . In an embodiment of the present invention, the device area 100 may be a logic device area, which may be, for example, a core circuit area, an input/output (I/O) circuit area, and/or similar device areas. And the device area 200 may be a memory circuit area, which may include memory cells such as static access memory (hereinafter referred to as SRAM) cells. Therefore, the device area 200 can be a SRAM area. In other embodiments of the present invention, the device region 100 may be a region whose device (eg, transistor) density is lower than that of the device region 200 . The size of the active region 101 in the device region 100 may be larger than the size of the active region 201 in the device region 200 . For example, the length of the active region 101 (which is the dimension of the active region perpendicular to the direction of the width W1 ) may be 5 to 30 times the respective length of the device region 200 . If viewed from a top view, the active region 101 may be close to a strip, and its width W1 is smaller than the size of the strip. On the other hand, the active region 201 can be a square or a rectangle with a similar width (W2) and length. A shallow trench isolation region (STI region) 4 is formed to isolate the device regions 100 and 200 . The substrate 2 may comprise a bulk semiconductor material such as silicon, or a composite structure such as a silicon-on-insulator (SOI) structure.

A gate stack structure 102 including a gate dielectric 104 and a gate 106 is formed over the device region 100 and the substrate 2 . A gate stack structure 202 including a gate dielectric 204 and a gate 206 is formed over the device region 200 and the substrate 2 . Gate dielectrics 104 and 204 may comprise silicon oxide or a high-k material such as a dielectric constant greater than 7. Gates 106 and 206 may comprise common conductive materials such as doped polysilicon, metal, metal suicide, or combinations thereof. In addition, the dummy gate stack structure 502 includes a dummy gate dielectric 504 and a dummy gate 506 , wherein the dummy gate 506 can be electrically floating.

Referring to FIG. 3 , lightly doped source/drain (LDD) regions 110 and 210 may be formed by, for example, implanting p-type dopants. The gates 106 and 206 may be considered as masks such that the inner sidewalls of the lightly doped source/drain (LDD) regions 110 and 210 are substantially aligned with the edges of the gates 106 and 206, respectively.

Referring to FIG. 4 , gate spacers 116 , 216 and dummy gate spacers 516 are formed. In an embodiment of the present invention, each of the gate spacers 116 and 216 may include a nitride layer with a pad oxide layer above the pad oxide layer. In other embodiments of the present invention, each gate spacer 116 and 216 may include one or more layers, and each gate spacer 116 and 216 may include oxide, silicon nitride, silicon oxynitride/or other dielectric materials. Electrical material, each gate gap can be formed by conventional methods of plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), or other similar methods Walls 116,216. The formation of the gate spacers 116 and 216 may include forming the gate spacer layer over the entire surface, and then performing an etching step to remove the horizontal portion of the gate spacer layer, so that the remaining portion of the gate spacer layer Vertical portions of the gate spacers 116 and 216 are formed.

Referring to FIG. 5 , the recesses 118 and 218 can be formed by etching the substrate 2 isotropically or anisotropically. Depth D of depressions 118 and 218 may be between to However, other thicknesses may also be used. However, those skilled in the art can understand that the dimensions mentioned in the description are only examples, and the above dimensions can be changed if different processes are used. In an embodiment of the invention, the cross-sectional view of the recess 118 may be a spare shape. In a perspective view, the bottom of each of the recesses 118 and 218 has an upside-down pyramid shape. However, other shapes of the recesses are also possible depending on the method and process parameters used in the etching process.

Figure 6 shows how the epitaxial region is formed. Epitaxial regions 120 and 220 may be formed by growing a semiconductor material such as SiGe in recesses 118 and 218 using a selective epitaxial growth step. The aforementioned semiconductor material may have a larger lattice constant than that of the substrate 2 . When performing the epitaxial growth step, desired dopants may or may not be doped. After an annealing process, SiGe tries to recover its lattice constant, thereby introducing compressive stress to the channel region of the final PMOS device. In the description, the SiGe epitaxial regions 120 and 220 can be regarded as SiGe stressors 120 and 220 respectively.

Precursor gases for growing SiGe may include growth gases such as germane ( _GeH4 , which provides germanium) and dichlorosilane (DCS, which provides silicon). In addition, a carbon-containing silicon source gas (such as methylsilyl methane ((CH ₃ )SiH ₃ ) or SiC _x H _4-x ) and/or a carbon-containing germanium source gas (such as GeCH ₃ or GeC _x H ₄ -x ) can be added. _x ). An etchant gas selected from hydrogen chloride gas (HCl), hydrofluoric acid gas (HF), chlorine gas (Cl ₂ ), or a combination thereof may be introduced to remove growth on, for example, gate spacers 116 and 216 and STIs. Unwanted silicon germanium portion on region (STIregion) 4. In other embodiments of the present invention, the above-mentioned _etching gas may be selected from the _{group consisting} of _{CxFyHz , CxClyHz , SixFyHz and SixClyHz} , _{wherein x} , The values of y and z indicate the proportions of the respective elements. The above-mentioned etching gas may also have the effect of reducing pattern loading effect (local loading effect). Thus, during the epitaxial growth step, both growth and etching occur simultaneously. However, the growth rate will be greater than the etch rate, so the net effect is growth. In one embodiment of the present invention, the selective growth step can be performed in a chamber using a low-pressure chemical vapor deposition (LPCVD) method, and the total pressure of the gas in the chamber can be between about 1 torr (torr) to 200 Between torr (torr), or between about 3 torr (torr) to 50 torr (torr). During the selective growth step, the temperature of the wafer 1 may for example be between 500°C and 800°C.

As shown in FIG. 5 , W3 is greater than W4 because pattern loading effects will result in different widths W3 and W4 of recesses 118 and 218 , respectively. The (111) facets of the SiGe stressor 220 are pinned in the epitaxial region 218 (as shown in FIG. 6 ). Therefore, the SiGe stressor 220 will have a (111)-oriented plane. In addition, the growth rate of the SiGe stressor 220 is lower than that of the SiGe stressor 120 . Therefore, as shown in FIG. 6 , the height H1' of the SiGe stressor 120 above the top surface 2a of the substrate 2 is smaller than the height H2' of the SiGe stressor 220 above the top surface 2a of the substrate 2 . The silicon germanium stressor 220 located on the top surface 2 a of the substrate 2 may be in a pyramid shape or close to a pyramid shape, and the above-mentioned slope has a surface of (111) lattice. The height difference between the height H1', the height H2' and the non-planar top surface profile, especially the SiGe stressor 220, will lead to the complexity of the subsequent device process, and will be detrimental to the performance of the device.

As shown in FIG. 7 , in one embodiment of the present invention, after the top of the SiGe stressor 220 is higher than the top surface 2 a of the substrate 2 , a selective etch back step may be performed to etch back the SiGe stressor 220 . In other embodiments of the present invention, when the selective etch back step starts, the top of the SiGe stressor 220 (refer to FIG. 6 ) can be aligned with or below the top surface 2 a of the substrate 2 . In one embodiment of the present invention, when the top of the SiGe stressor 220 is approximately pyramid-shaped, and wherein the top of the SiGe stressor 220 is higher than the top surface 2a of the substrate 2, the above selective etch back is started. step.

The selective growth step and the selective etch-back step of the SiGe stressors 120 and 220 can be performed in-situ, ie without breaking the vacuum between the selective growth process and the selective etch-back process. Furthermore, the wafer 1 in the cavity will not be taken out of the cavity when the selective growth step is completed. Furthermore, switching from performing the selective growth step to performing the selective etch-back step can be performed by adjusting process conditions such as the composition and pressure of the process gas, the temperature of the wafer 1, or the like.

In an embodiment of the present invention, in order to switch from the selective growth step to the selective etch-back step, the partial pressure or flow rate of the etching gas such as hydrogen chloride gas (HCl) can be increased to increase the etching effect. At the same time, a growth gas such as germane (GeH ₄ ) or dichlorosilane (DCS) for becoming silicon germanium is continuously introduced. Additionally, during the selective etch-back step, both growth and etch occur simultaneously. However, the etch rate will be greater than the growth rate, so at least for SiGe stressor 220 the net effect is etching. Furthermore, due to the pattern loading effect, etching of the SiGe stressor 120 will be weaker than etching of the SiGe stressor 220, and thus the net effect on the SiGe stressor 120 may be continued growth, etch back, or no growth. Without etch back, the net effect of the SiGe stressor 120 described above depends on the process conditions in the selective etch back step.

In order to determine the optimal conditions for the above selective etch-back step, the process conditions can be judged by an etch-back/growth ratio (E/Gratio). The above etch back/growth ratio (E/Gratio) is the partial pressure of the etch back gas (such as hydrogen chloride gas (HCl)) to the growth gas (such as germane (GeH ₄ ) and dichlorosilane (DCS)) The ratio of weighted partial pressure. In one embodiment of the present invention, the above etch back/growth ratio can be expressed as: etch back/growth ratio (E/Gratio)=P _HCl /(P _DCS +100xP _GeH4 ), wherein, P _HCl , P _DCS and P _GeH4 are the partial pressures of hydrogen chloride gas (HCl), germane (GeH ₄ ) and dichlorosilane (DCS), respectively. The value 100 represents the weight of germane (GeH ₄ ). It can be understood that the growth effect of germane (GeH ₄ ) is much higher than that of dichlorosilane (DCS). In other words, introducing more germane (GeH ₄ ) is more effective than introducing more dichlorosilane (DCS) in order to increase the growth rate. While there may be different optimal weights, a value of 100 indicates that germane (GeH ₄ ) is more effective than dichlorosilane (DCS). In one embodiment of the present invention, the etch-back/growth ratio (E/Gratio) may be between about 0.4 and 2.0. The optimal etch-back/growth ratio (E/Gratio) of the above selective etch-back step can be obtained through experiments.

Figure 10 shows the effect of the etch back/growth ratio (E/Gratio) on the growth/etch rate (growth/etchrate) of silicon germanium, where the X-axis represents the etch back/growth ratio (E/Gratio), and the Y-axis represents the silicon germanium Growth/etch rate (growth/etchrate). A positive value (Y-axis) indicates that the net effect is growth, which may include epigrowth with defect in range A, normal epigrowth in range B, and balanced epigrowth in range C, A negative value (Y-axis) indicates that the net effect is etch back, which may include the range D of Selective Epigrowth. It is understood that when increasing HCl gas to lower the etch back/growth ratio (E/Gratio), conversely, an increase rather than a decrease in the growth rate of SiGe may occur. When the etch back/growth ratio (E/Gratio) is increased even more, the growth rate of SiGe will decrease although the net effect is still growth. As the etch back/growth ratio (E/Gratio) increases further, the effect of etch back outweighs the effect of growth, and the net effect becomes etch back.

Switching from performing the selective growth step to performing the selective reversion step can be performed by increasing the partial pressure of dichlorosilane (DCS) and/or decreasing the germane (GeH ₄ ), increasing the total pressure of the process gas, or increasing the temperature of the wafer 1 . Etching steps, and achieve the most ideal etch-back conditions. In one embodiment of the present invention, during the selective etch back step, the temperature of the wafer 1 may be between 500°C and 800°C, or may be between 600°C and 700°C. The duration of the selective etch back step may be between 3 seconds and 600 seconds, or may be between 3 seconds and 50 seconds. The total pressure of the process gas may be between 1 torr and 200 torr.

During the selective etch back step, a desired reverse pattern loading effect occurs, wherein the etch rate of the SiGe stressor 120 is at least lower than the etch rate of the SiGe stressor 220 . Therefore, the unwanted pyramid-shaped SiGe stressor 220 can be eliminated. The resulting silicon germanium stressor 220 may have a preferred profile, which may include a substantially flat top surface as shown in FIG. 7 . Therefore, the lattice facets of the SiGe stressor 120 and/or the SiGe stressor 220 can be at least reduced or even eliminated. In one embodiment of the present invention, the etch-back/growth ratio (E/Gratio) may be between about 0.4 and 2.0. The optimal etch-back/growth ratio (E/Gratio) of the above selective etch-back step can be obtained through experiments.

In an embodiment of the present invention, the silicon germanium stressors 120 and 220 can be overgrown and then etched back to a desired thickness in a growth-etch cycle, or a gradual change ( gradientchanging) gas composition to achieve the desired reaction gas concentration. In other embodiments of the present invention, the formation of the SiGe stressors 120 and 220 may include multiple growth-etch cycles to achieve a better SiGe surface profile. The additional growth-etch cycle described above may be substantially similar to the growth-etch cycle shown in FIGS. 6 and 7 and thus is not shown here.

Figure 8 shows the formation of silicon caps or silicon germanium caps 130 and 230 (hereinafter also referred to as silicon/silicon germanium caps or silicon-containing caps), which can be formed using a selective epitaxial growth step. and 230. When germanium is included in the silicon-containing caps, the atomic percentages of germanium in the silicon-containing caps 130 and 230 are lower than the germanium atoms in the silicon-germanium stressors 120 and 220 located below the silicon-containing caps 130 and 230, respectively. percentage. Additionally, the atomic percent germanium in the silicon-containing caps 130 and 230 may be less than 20 percent. The silicon-containing caps 130 and 230 benefit the subsequently formed source and drain silicide regions because low-resistance silicides are formed on silicon and not on silicon germanium. The process gas used for formation may include silane (SiH ₄ ) or hydrogen chloride gas (HCl). Furthermore, in the selective epitaxial growth of silicon-containing caps 130 and 230, both growth and etching occur simultaneously, with the net effect being growth. Facets are also formed on the silicon-containing caps 130 and 230 . Therefore, similar to the formation of SiGe stressors 120 and 220, after the selective epitaxial growth of silicon-containing caps 130 and 230, a selective etch-back can be selectively performed to reduce the pattern loading effect and improve the silicon-containing caps. The outlines of objects 130 and 230. The outlines of the silicon-containing caps 130 and 230 at the beginning of the selective etch-back step are shown in dotted lines and the profiles of the silicon-containing caps 130 and 230 after the selective etch-back step are shown in solid lines. Furthermore, the selective growth and selective etching back of the silicon-containing caps 130 and 230 can be performed in-situ. In selective etch back of silicon-containing caps 130 and 230, both growth and etch back occur simultaneously with the net effect being etch back. The selective growth step can be switched to the selective etch-back step by adjusting process conditions such as increasing the partial pressure of hydrogen chloride gas (HCl) and/or reducing the partial pressure of silane (SiH ₄ ).

FIG. 9 shows how the silicide regions 134, 234, etch stop layer (ESL) 36 and contact hole plugs 140, 240 are formed. Thin metal layers such as titanium, cobalt, nickel or similar materials are deposited over the exposed surfaces of the components and include silicon-containing caps 130, and 230 and gates 106, 206. The wafer 1 is then heated, which causes a silicidation reaction of the metal in contact with the silicon. After the silicidation reaction occurs, a metal silicide layer is formed between the silicon and the metal. Unreacted metal is selectively removed by using an etchant that attacks the metal but not the silicide. In addition, contact hole plugs connected to the dummy gate stack structure 502 are not formed.

An etch stop layer (ESL) 36 may be blanket deposited. The etch stop layer (ESL) 36 may be formed using a plasma enhanced chemical vapor deposition (PECVD) method. However, the etch stop layer (ESL) 36 may also be formed using other chemical vapor deposition (CVD) methods such as a low pressure chemical vapor deposition (LPCVD) method or a thermal chemical vapor deposition (thermalCVD) method. Next, an interlayer dielectric (ILD) 38 is deposited. The interlayer dielectric (ILD) 38 may include borophosphosilicate glass (BPSG) or other suitable materials. The above-mentioned interlayer dielectric layer (ILD) 38 provides isolation between the MOS device and the metal wires above it. Thereafter, contact hole plugs 140, 240 are formed which provide channels through the silicide regions 134, 234 to the source/drain regions and the gate.

The foregoing embodiments show the growth of SiGe stressors for planar devices. However, the teachings of the above embodiments are also applicable to the growth of SiGe stressors for fin field effect transistors (FinFETs). The process may include forming a gate stack structure on a semiconductor fin (not shown), etching exposed portions of the semiconductor fin not covered by the gate stack structure, and performing a selective growth step, followed by A selective etch back step to form SiGe stressors. The detailed content of the process can be understood from the teaching of the embodiment, so it will not be described here. In addition, the teachings of the above embodiments can also be applied to the growth method of stressors (such as silicon carbide stressors) for MOS devices. The selective etch-back step discussed in the embodiments, in addition to the formation of CMOS devices, can also be used in the formation of other devices such as solar cells and micro-electromechanical systems (MEMS) devices.

In the embodiment of the present invention, the pattern loading effect can be reduced by the selective etch back step, so as to form a more uniform epitaxial region (such as SiGe stressor) and improve the profile of the epitaxial region. Facets in the epitaxial region can be reduced or even eliminated. In addition, the selective growth step and the selective etch-back step can be performed in-situ to minimize additional cost.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be determined by the scope defined by the appended claims.

Claims (14)

1. a formation method for semiconductor structure, comprises the following steps:

Semiconductor substrate is provided, and it comprises one first element region and one second element region;

Top in this semiconductor substrate of this first element region and this second element region forms a first gridStacks structure and a second grid stacked structure;

In this semiconductor substrate respectively at this first element region and this second element region, form one first recessedFall into and one second depression, and this first depression and this second depression Lin Jie Fen Do are in the stacking knot of this first gridStructure and this second grid stacked structure;

Carry out a selective growth step, with the semiconductor of growing up in this first depression and this second depressionMaterial, with simultaneously and form respectively one first epitaxial region and one second epitaxial region, and this second epitaxial regionGrowth rate is greater than the growth rate of this first epitaxial region; And

After carrying out this selective growth step, this first epitaxial region and this second epitaxial region are carried out to a choosingSelecting property etch-back step, wherein use comprise growing up one first gas of this semi-conducting material and in order toThe process gas of one second gas of this first epitaxial region of etching and this second epitaxial region carries out that this is selectiveEtch-back step.

2. the formation method of semiconductor structure as claimed in claim 1, wherein this first gas comprises firstGermane GeH₄With dichlorosilane DCS, and this second gas comprises hydrogen chloride gas HCl, hydrofluoric acid gasBody HF, chlorine Cl₂、C_xF_yH_z、C_xCl_yH_z、Si_xF_yH_zOr Si_xCl_yH_z。

3. the formation method of semiconductor structure as claimed in claim 2, wherein this first gas more comprisesOne carbon containing silicon source gas or a carbon containing germanium source gas wherein this carbon containing silicon source gas comprise methyl silicomethane(CH₃)SiH₃Or SiC_xH_4-x, and this carbon containing germanium source gas comprises GeCH₃Or GeC_xH_4-x。

4. the formation method of semiconductor structure as claimed in claim 1, is wherein somebody's turn to do in original position modeSelective growth step and carry out this selective etch-back step.

5. the formation method of semiconductor structure as claimed in claim 1, carries out this selective etch-back stepAfter rapid, more comprise respectively at this first epitaxial region and top, this second epitaxial region and form a siliceous covering,And this siliceous covering has different compositions from this first epitaxial region and this second epitaxial region, wherein formsThis siliceous covering comprises:

Carry out an extra selective growth step, with this siliceous covering of growing up; And

After carrying out this extra selective growth step, carry out an extra selective etch-back step, to returnThis siliceous covering of etching.

6. the formation method of semiconductor structure as claimed in claim 1, carries out this selective etch-back stepAfter rapid, carry out a process cycles, comprise the following steps:

Carry out an extra selective growth step, to increase one of this first epitaxial region and this second epitaxial regionThickness; And

After carrying out this extra selective growth step, carry out an extra selective etch-back step, to enterOne step reduces this thickness of this first epitaxial region and this second epitaxial region.

7. a formation method for semiconductor structure, comprises the following steps:

Semiconductor substrate is provided, and it comprises and is positioned at a Part I of one first element region and is positioned at one theOne Part II in two element district;

In this first element region and the top of this semiconductor substrate form a first grid stacked structure;

In this second element region and the top of this semiconductor substrate form a second grid stacked structure;

In this semiconductor substrate, form one first depression that is adjacent to this first grid stacked structure, and inIn this semiconductor substrate, form one second depression that is adjacent to this second grid stacked structure;

Carry out a selective growth step, with one first epitaxial region of growing up in this first depression simultaneously, andOne second epitaxial region of growing up in this second depression, and the growth rate of this second epitaxial region be greater than this firstThe growth rate of epitaxial region; And

Carry out a selective etch-back step, with this first epitaxial region of while etch-back and this second extensionDistrict, and the etch-rate of this second epitaxial region is greater than the etch-rate of this first epitaxial region, wherein with original positionMode is carried out this selective growth step and is carried out this selective etch-back step.

8. the formation method of semiconductor structure as claimed in claim 7, wherein carries out this and selectively grows upStep comprises first germane GeH with each use of carrying out this selective etch-back step₄And dichlorosilaneA growth gas of DCS, and comprise hydrogen chloride gas HCl, hydrofluoric acid gas HF or chlorine Cl₂'sOne etching gas, and carry out the dividing potential drop of this growth gas in this selective growth step and this etching gasBe different from respectively the dividing potential drop of this growth gas of carrying out in this selective etch-back step and this etching gas.

9. the formation method of semiconductor structure as claimed in claim 8, wherein selectively becomes from carrying out thisLong step conversion comprises increase hydrogen chloride gas HCl, hydrofluoric acid gas to carrying out this selective etch-back stepBody HF or chlorine Cl₂A dividing potential drop.

10. the formation method of semiconductor structure as claimed in claim 8, wherein selective from carrying out thisGrowth step conversion comprises reduction dichlorosilane DCS or first germane to carrying out this selective etch-back step GeH₄One point be depressed into a nonzero value.

The formation method of 11. semiconductor structures as claimed in claim 7, wherein this is selective carrying outDuring etch-back step, increase a thickness of this first epitaxial region.

The formation method of 12. semiconductor structures as claimed in claim 7, wherein this is selective carrying outDuring etch-back step, do not change a thickness of this first epitaxial region.

The formation method of 13. semiconductor structures as claimed in claim 7, wherein this is selective carrying outDuring etch-back step, reduce a thickness of this first epitaxial region.

The formation method of 14. 1 kinds of semiconductor structures, comprises the following steps:

One substrate is provided, and it comprises one first semiconductor region and one the second half on a surface that is positioned at this substrateConductor region; And

This first semiconductor region and this second semiconductor region are carried out to a selective etch-back step, and this is second years oldThe etch-rate of semiconductor region is greater than the etch-rate of this first semiconductor region, and carries out this and selectively eat-backCarve to use in step and comprise that the half that is used to grow up on this first semiconductor region and this second semiconductor region leadsOne first gas of body material and entering in order to the process gas of one second gas of this semi-conducting material of etchingThis selective etch-back step of row, wherein this first gas and this second gas select free first germane GeH4,The group that hydrogen chloride gas HCl, dichlorosilane DCS and combinations thereof form.