JP2006243753A - Substrate device, electro-optical device and electronic apparatus - Google Patents

Abstract

In an electro-optical device such as a liquid crystal device, light resistance is improved and bright and high-quality image display can be performed.
An electro-optical device includes a pixel array (9a) on a TFT array substrate (10), a TFT (30) connected to the pixel electrode, a scanning line (3a) and a data line (30) connected thereto. 6a). Further, the relay layer (71) connected to the pixel electrode and constituting the storage capacitor (70), and the fixed potential side capacitance electrode constituting the storage capacitor disposed opposite to this via the dielectric film (75). And a capacitor line (300) including Each of the relay layer and the capacitor line contains a metal and functions as a light shielding film.
[Selection] Figure 3

Description

  The present invention belongs to a technical field of a substrate device suitably used for an electro-optical device such as an active matrix driving type liquid crystal device, the electro-optical device, and an electronic apparatus including the electro-optical device, and particularly for pixel switching. The thin film transistor (hereinafter referred to as “TFT” as appropriate) belongs to the technical field of a substrate device of a type provided with a laminated structure on a substrate.

  In an electro-optical device of the TFT active matrix driving type, when incident light is irradiated to a channel region of a pixel switching TFT provided in each pixel, a light leakage current is generated by light excitation and the characteristics of the TFT change. In particular, in the case of an electro-optical device for a projector light valve, since the intensity of incident light is high, it is important to shield incident light from the TFT channel region and its peripheral region. Therefore, conventionally, the light-shielding film that defines the opening area of each pixel provided on the counter substrate, or the data line made of a metal film such as Al (aluminum) while passing over the TFT on the TFT array substrate The channel region and its peripheral region are shielded from light. Furthermore, a light shielding film made of, for example, a refractory metal may be provided at a position facing the lower side of the TFT on the TFT array substrate. If a light-shielding film is also provided on the lower side of the TFT in this way, the back-surface reflected light from the TFT array substrate side or a combination of a plurality of electro-optical devices via a prism or the like may be used. Return light such as projection light that penetrates the prism or the like from the electro-optical device can be prevented from entering the TFT of the electro-optical device.

  On the other hand, in this type of electro-optical device, when the TFT is turned on, the voltage of the image signal applied to the pixel electrode through the TFT is much longer than the time when the TFT is turned on. For example, a storage capacitor composed of a pixel potential side capacitor electrode connected to a drain electrode or a pixel electrode of a TFT and a fixed potential side capacitor electrode arranged to face this through a dielectric film is provided. The technology built into each pixel is also common.

  However, when a storage capacitor is built in a stacked structure on a substrate, there is generally a need to connect the pixel potential side capacitor electrode and the pixel electrode or TFT through a contact hole opened in the stacked structure. Arise. Therefore, since the light shielding film or the data line between the TFT connected to the contact hole and the pixel electrode is formed avoiding the contact hole, the light shielding performance is deteriorated in the contact hole and the periphery thereof. A point is created. That is, incident light incident on the contact hole and its periphery reaches the TFT channel region and its peripheral region without being shielded by the light-shielding film or the data line, and the TFT characteristics change or deteriorate. There is a problem of causing flicker and the like.

  The present invention has been made in view of the above-described problems, and has a substrate device that has excellent light resistance and enables high-quality image display, an electro-optical device including the substrate device, and the electro-optical device. It is an object to provide an electronic device.

  In order to solve the above problems, a substrate device of the present invention is connected to a pixel electrode, a thin film transistor connected to the pixel electrode, a scanning line and a data line connected to the thin film transistor, and the pixel electrode on the substrate. A pixel potential side capacitor electrode that constitutes a storage capacitor, and a capacitor line that includes the fixed potential side capacitor electrode that is disposed opposite to the pixel potential side capacitor electrode via a dielectric film and that constitutes the storage capacitor. The pixel potential side capacitance electrode and the fixed potential side capacitance electrode each include a metal.

  According to the substrate device of the present invention, the pixel electrode can be driven in an active matrix by supplying the scanning signal and the image signal to the thin film transistor through the scanning line and the data line. Here, since the pixel electrode is connected with a storage capacitor in which the pixel potential side capacitor electrode and the fixed potential side capacitor electrode are arranged to face each other, the voltage of the image signal written to the pixel electrode is applied over a long period of time. Can hold. In particular, since the pixel potential side capacitance electrode and the fixed potential side capacitance electrode each contain a metal, both or one of them is a low resistance capacitance electrode, and further a dielectric interposed between them. By increasing the dielectric constant of the film, a relatively large storage capacity can be constructed in a limited area on the substrate. At the same time, since the pixel potential side capacitance electrode and the fixed potential side capacitance electrode each contain a metal, it is possible to improve the light shielding performance of shielding the thin film transistor by providing a light shielding function to both or one of the capacitance electrodes. It becomes. By using the two capacitor electrodes constituting the storage capacitor in this way as a light-shielding film containing a metal, incident light can be prevented from reaching the channel region of the thin film transistor and its peripheral region. A situation that causes flicker or the like due to a change in characteristics can be effectively prevented.

  As a result, according to the substrate device of the present invention, high-quality image display is possible.

  In one aspect of the substrate device of the present invention, the pixel potential side capacitor electrode is connected to the pixel electrode through a contact hole, and the capacitor line is arranged so as to avoid the contact hole in plan view. A notch is provided, and each of the pixel potential side capacitance electrode and the fixed potential side capacitance electrode includes a light-shielding metal film.

  According to this aspect, the capacitor line is provided with the notch so as to avoid the contact hole for connecting the pixel potential side capacitor electrode and the pixel electrode. Therefore, the light shielding performance of the capacitor line or the fixed potential side capacitor electrode included in the capacitor line inevitably deteriorates at the contact hole and its periphery. However, the pixel potential side capacitor electrode disposed opposite thereto includes a light-shielding metal film. For this reason, the pixel potential side capacitor electrode portion to which the contact hole is connected also functions as a light shielding film, so that the light shielding performance is not inferior even if the contact hole or its periphery is used.

  In another aspect of the substrate device of the present invention, the pixel potential side capacitor electrode is connected to the thin film transistor through a contact hole, and the capacitor line is cut so as to avoid the contact hole in plan view. A notch is provided, and each of the pixel potential side capacitor electrode and the fixed potential side capacitor electrode includes a light-shielding metal film.

  According to this aspect, the capacitor line is provided with the notch so as to avoid the contact hole for connecting the pixel potential side capacitor electrode and the thin film transistor. Therefore, the light shielding performance of the capacitor line or the fixed potential side capacitor electrode included in the capacitor line inevitably deteriorates at the contact hole and its periphery. However, the pixel potential side capacitor electrode disposed opposite thereto includes a light-shielding metal film. For this reason, the pixel potential side capacitor electrode portion to which the contact hole is connected also functions as a light shielding film, so that the light shielding performance is not inferior even if the contact hole or its periphery is used.

  In another aspect of the substrate device of the present invention, the fixed potential side capacitance electrode is formed on the pixel potential side capacitance electrode on the substrate via the dielectric film.

  According to this aspect, the pixel potential side capacitance electrode, the dielectric film, and the fixed potential side capacitance electrode are laminated in this order on the substrate, and by making these two capacitance electrodes function as a light shielding film, High shading performance for the channel region and its peripheral region can be obtained and the storage capacity can be increased. In particular, in the contact hole for connecting the pixel potential side capacitor electrode to the pixel electrode and its periphery, a structure that improves the light shielding performance by using the fixed potential side capacitor electrode as the light shielding film is obtained.

  In another aspect of the substrate device of the present invention, the fixed potential side capacitor electrode is formed on the substrate below the pixel potential side capacitor electrode via the dielectric film.

  According to this aspect, the fixed potential side capacitor electrode, the dielectric film, and the pixel potential side capacitor electrode are laminated in this order on the substrate, and by functioning these two capacitor electrodes as a light shielding film, High shading performance for the channel region and its peripheral region can be obtained and the storage capacity can be increased. In particular, in the contact hole for connecting the pixel potential side capacitor electrode to the thin film transistor and in the vicinity thereof, a structure that improves the light shielding performance by using the fixed potential side capacitor electrode as the light shielding film is obtained.

In another aspect of the substrate device of the present invention, the dielectric film includes TaOx, BST ((Ba, Sr) TiO ₃ ), PZT (Pb (Zr, Ti) O ₃ ), TiO ₂ , ZrO ₂ , HfO _2. , SiO ₂ , SiON, and SiN.

According to this aspect, by using a high dielectric constant material such as TaOx, BST, PZT, TiO ₂ , ZrO ₂ , and HfO ₂ as the dielectric film, a large storage capacity can be constructed in a limited region on the substrate. Furthermore, by using a material containing silicon, such as SiO ₂ , SiON, or SiN, as a dielectric film, the storage capacitance is reduced while reducing the occurrence of stress in the same stacked structure as the conductive film, semiconductor film, and insulating film containing silicon. Can be constructed.

In another aspect of the substrate device of the present invention, the pixel potential side capacitor electrode and the fixed potential side capacitor electrode each include at least one of Pt, Ru, TiN, TaN, SRO (SrRuO ₃ ), and Al.

  According to this aspect, the light shielding performance can be improved by the metal film containing at least one of Pt, Ru, TiN, TaN, SRO, and Al.

  In another aspect of the substrate device of the present invention, the pixel potential side capacitor electrode includes Pt, and the fixed potential side capacitor electrode includes Al.

  According to this aspect, the pixel potential side capacitor electrode including Pt and the fixed potential side capacitor electrode including Al can reliably improve the light shielding performance and can stably increase the storage capacitor.

  Alternatively, in another aspect of the substrate device of the present invention, the pixel potential side capacitor electrode includes TiN, and the fixed potential side capacitor electrode includes Al.

  According to this aspect, the pixel potential side capacitor electrode including TiN and the fixed potential side capacitor electrode including Al can surely improve the light shielding performance and can stably increase the storage capacitor.

  In another aspect of the substrate device of the present invention, at least one of the pixel potential side capacitor electrode and the fixed potential side capacitor electrode is formed of a laminate.

  According to this aspect, for example, by forming both or one of the two capacitor electrodes from a laminate including a normal metal, a refractory metal, a silicide, a Si film, a SiGe (silicon germanium) film, etc., the light shielding performance In addition, the storage capacity can be increased while increasing the degree of freedom in manufacturing the device.

  In another aspect of the substrate device of the present invention, the pixel potential side capacitor electrode is composed of the multilayer body, the multilayer body includes an Al film and an AlN film, and the pixel electrode is composed of an ITO film, When the AlN film and the pixel electrode are in electrical contact, the pixel potential side capacitor electrode and the pixel electrode are connected.

  According to this aspect, a very good ohmic contact can be obtained between the portion made of the AlN film of the pixel potential side capacitor electrode and the pixel electrode made of ITO. Even if the Al film and the ITO film are brought into contact with each other, a potential barrier is generated and no ohmic contact can be obtained.

  In another aspect of the substrate device of the present invention, the stacked body includes a light absorption layer containing silicon and a light shielding layer containing metal.

  According to this aspect, by reflecting or absorbing light by the light-shielding layer containing metal, the basic light-shielding performance of the capacitor electrode made of the laminate is improved, and light is absorbed by the light-absorbing layer containing silicon. Thus, it is possible to suppress the generation of internally reflected light or multiple reflected light due to reflection of incident light and return light on the surface of the laminate.

  In this aspect, the light absorption layer may be formed of the same layer as the semiconductor layer constituting the thin film transistor.

  According to this aspect, since the light absorption layer is formed of the same layer as the semiconductor layer constituting the thin film transistor, the manufacturing process and the laminated structure on the substrate can be simplified. Such a light absorption layer is made of, for example, a conductive polysilicon film, amorphous silicon, single crystal silicon, or a SiGe material layer.

  In another aspect of the substrate device of the present invention, a non-opening region in each pixel is defined by at least one of the pixel potential side capacitor electrode and the capacitor line and the data line.

  According to this aspect, the non-opening region in each pixel is defined by both or one of the pixel potential side capacitor electrode and the capacitor line existing in the stacked structure on the substrate and the data line, and therefore, compared with the thin film transistor. The channel region can be shielded from light at a position close to the target.

  In this aspect, the substrate further includes a lower light-shielding film that covers at least the channel region of the thin film transistor from the lower side, and the lower light-shielding film has a smaller outline than the non-opening region in plan view. You may comprise as follows.

  If comprised in this way, return light can be light-shielded by a lower side light shielding film. In particular, since the lower light-shielding film has a smaller contour than the non-opening region, oblique incident light from the upper side passes through the pixel potential side capacitor electrode, the capacitor line, or the data line, and the upper surface of the lower light-shielding film. Can reduce the possibility of reflection. As a result, it is possible to effectively prevent the reflected light from the upper surface of the lower light-shielding film from reaching the channel region as internally reflected light or multiple reflected light.

  In order to solve the above-described problems, the electro-optical device of the present invention includes an electro-optical material sandwiched between the above-described substrate device of the present invention (including various aspects thereof) and another substrate.

  According to the electro-optical device of the present invention, since the above-described substrate device is provided, flicker and the like are reduced by the stable operation of the thin film transistor even in a use environment where strong incident light is incident. A relatively large storage capacity enables high-quality image display.

  According to the electronic apparatus of the present invention, since it includes the above-described electro-optical device of the present invention, a projection display device, a liquid crystal television, a mobile phone, an electronic notebook, a word processor, and a viewfinder capable of displaying a bright and high-quality image. Various electronic devices such as a video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized.

  Such an operation and other advantages of the present invention will become apparent from the embodiments described below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the electro-optical device of the invention is applied to a liquid crystal device.

(First embodiment)
First, the configuration of the pixel portion of the electro-optical device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix that forms an image display region of an electro-optical device. FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed. 3 is a cross-sectional view taken along line AA ′ of FIG. Further, FIG. 4 is a schematic partial perspective view showing a state of light shielding in and around the contact hole connecting the pixel potential side capacitor electrode to the pixel electrode in this embodiment, and FIG. 5 is a pixel potential side in the comparative example. FIG. 6 is a schematic partial perspective view showing a state of light shielding in and around a contact hole connecting a capacitor electrode to a pixel electrode, and FIG. 6 is a schematic view showing a MIM (Metal Insulator Metal) structure of a storage capacitor in the present embodiment. FIG. In FIGS. 3 and 6, the scale of each layer and each member is different in order to make each layer and each member recognizable on the drawing.

  In FIG. 1, a pixel electrode 9a and a TFT 30 for switching control of the pixel electrode 9a are formed in each of a plurality of pixels formed in a matrix that constitutes an image display region of the electro-optical device according to the present embodiment. The data line 6 a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. good. Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulse-sequential manner in this order at a predetermined timing. It is configured. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,..., Sn supplied from the data line 6a is obtained by closing the switch of the TFT 30 as a switching element for a certain period. Write at a predetermined timing. Image signals S1, S2,..., Sn written in a liquid crystal as an example of an electro-optical material via the pixel electrode 9a are held for a certain period with a counter electrode formed on a counter substrate described later. The The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gradation display. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to the image signal is emitted from the electro-optical device as a whole. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode.

  In FIG. 2, a plurality of transparent pixel electrodes 9a (outlined by dotted line portions 9a ′) are provided in a matrix on the TFT array substrate of the electro-optical device. A data line 6a and a scanning line 3a are provided along each boundary.

  In addition, the scanning line 3a is disposed so as to face the channel region 1a 'indicated by the hatched region rising to the right in the drawing in the semiconductor layer 1a, and the scanning line 3a functions as a gate electrode. That is, the pixel switching TFT 30 in which the main line portion of the scanning line 3a is opposed to the channel region 1a 'as the gate electrode is provided at each intersection of the scanning line 3a and the data line 6a.

  As shown in FIGS. 2 and 3, the storage capacitor 70 includes a high-concentration drain region 1e of the TFT 30 and a relay layer 71 as a pixel potential side capacitor electrode connected to the pixel electrode 9a, and a capacitor as a fixed potential side capacitor electrode. A part of the line 300 is formed so as to be opposed to each other through the dielectric film 75.

  In particular, in the present embodiment, the storage capacitor 70 has an MIM structure. The configuration and operation and effect of the MIM structure related to the storage capacitor will be described in detail with reference to FIGS. 4 to 6 in addition to FIGS.

  As shown in FIGS. 3, 4, and 6, in the present embodiment, the relay layer 71 constituting an example of the pixel potential side capacitor electrode is made of a conductive film containing a metal, and is formed of a fixed potential side capacitor electrode. The capacitor line 300 that constitutes an example is made of a conductive film containing metal, and an MIM structure is constructed on the first interlayer insulating film 41 in such a manner that the dielectric film 75 is sandwiched therebetween.

  Each of the relay layer 71 and the capacitor line 300 constituting the MIM structure has a film thickness of about several tens to several thousand nm including at least one of Pt, Ru, TiN, TaN, SRO, and Al as a metal. It consists of a conductive film. Accordingly, the relay layer 71 and the capacitor line 300 each function as a light shielding film having excellent light shielding performance, and the planar shape of the electro-optical device has a data line 6a made of an Al film or the like shown in FIGS. An upper light shielding film having a lattice shape is constructed. More specifically, for example, the relay layer 71 includes Pt, and the capacitor line 300 includes Al. Alternatively, the relay layer 71 includes TiN, and the capacitor line 300 includes Al. With such a combination, it is possible to reliably increase the light shielding performance and at the same time stably increase the storage capacity. At this time, the film thickness of each metal film may be set to a value sufficient to obtain a specific and sufficient light-shielding performance in consideration of incident light intensity, apparatus specifications, and the like. In addition, the capacitor line 300 located on the upper side of the TFT array substrate 10 is formed of an Al film having a very high reflectance, and the relay layer 71 located on the lower side is formed with a reflectance of several minutes compared to the Al film. By forming the Pt film or TiN film, which is about one of the above, incident light incident from the upper side is reflected by the upper capacitive line 300, thereby reducing the generation of internally reflected light and multiple reflected light.

Further, at least one of the dielectric film 75 of the storage capacitor 70, for example a relatively thin thickness of about 5~200nm, TaOx, BST, PZT, TiO 2, ZrO 2, HfO 2, SiO 2, SiON and SiN It consists of an insulating film containing. In particular, by using a high dielectric constant material such as TaOx, BST, PZT, TiO ₂ , ZrO ₂ , and HfO ₂ as the dielectric film 75, the capacitance value can be increased in a limited region on the substrate. Alternatively, by using a material containing silicon such as SiO ₂ , SiON, or SiN for the dielectric film 75, stress is generated between the semiconductor layer 1 a containing silicon and the interlayer insulating film such as the first interlayer insulating film 41. Can be reduced. The dielectric film 75 may be formed of a silicon oxide film such as an HTO (High Temperature Oxide) film, an LTO (Low Temperature Oxide) film, or a silicon nitride film. In any case, from the viewpoint of increasing the storage capacity 70, the thinner the dielectric film 75 and the higher the dielectric constant, the better as long as the reliability of the film is sufficiently obtained.

  Therefore, according to the present embodiment, a relatively large capacitance value can be realized by the MIM structure storage capacitor 70 in which the high-dielectric-constant dielectric film is sandwiched between the two low-resistance capacitor electrodes, and at the same time, the light shielding of the TFT 30 is achieved. Performance can be improved.

  That is, as shown in FIG. 4, the incident light L 0 perpendicular to the substrate surface and the incident light L 1 oblique to the substrate surface are substantially shielded by the capacitance line 300. Even if the incident light L2 is incident on the notch of the capacitor line 300 provided so as to avoid the contact hole 85 connecting the pixel electrode 9a and the relay layer 71, it is connected to the contact hole 85. The light is shielded by the relay layer 71 made of a light shielding film.

  As shown in FIG. 5 (comparative example), if the relay layer 71 ′ is formed of a transparent or translucent, for example, conductive polysilicon film, a capacitor line provided so as to avoid the contact hole 85. When the incident light L2 enters the notch 300, it passes through the relay layer 71 and finally reaches the channel region 1a ′ of the TFT 30 or its adjacent region. As a result, the transistor characteristics of the TFT 30 change or deteriorate, and image quality deterioration such as flicker occurs.

  As can be seen from FIGS. 4 and 5, the MIM structure of this embodiment exhibits excellent light shielding performance particularly when the contact hole 85 is provided.

  In the present embodiment, the capacitor line 300 is on the upper side of the relay layer 71. However, even when the capacitor line is on the lower side of the relay layer, a contact hole connecting the relay layer and the high concentration drain region should be avoided. In addition, the capacitor line needs to be provided with a notch. Therefore, in this case as well, by using the MIM structure, the light shielding performance in the contact hole and its surroundings can be similarly enhanced.

  In addition, the capacitor line 300 extends in a stripe shape along the scanning line 3a as viewed in a plan view (see FIG. 2), and a portion overlapping the TFT 30 protrudes up and down in FIG. The data lines 6a extending in the vertical direction in FIG. 2 and the capacitor lines 300 extending in the horizontal direction in FIG. A lattice-like upper light-shielding film (built-in light-shielding film) is formed, and defines an opening area of each pixel.

  Further, the capacitor line 300 extends from the image display area in which the pixel electrode 9a is disposed to the periphery thereof, and is electrically connected to a constant potential source to be a fixed potential. As such a constant potential source, a later-described scanning line driving circuit for supplying a scanning signal for driving the TFT 30 to the scanning line 3a and a later-described data line driving for controlling a sampling circuit for supplying an image signal to the data line 6a. A constant potential source such as a positive power source or a negative power source supplied to the circuit may be used, or a constant potential supplied to the counter electrode 21 of the counter substrate 20 may be used.

  On the other hand, the relay layer 71 relays the pixel electrode 9a and the high-concentration drain region 1e through the contact holes 83 and 85 in addition to the function as the pixel potential side capacitor electrode and the light shielding function of the storage capacitor 70 as described above. It also has a function to connect. By relay connection by the relay layer 71, even if the interlayer distance is long, for example, about 2000 nm, two or more series contacts having a relatively small diameter are avoided while avoiding the technical difficulty of connecting the two with a single contact hole. Both holes can be connected well with each other, the pixel aperture ratio can be increased, and it is useful for preventing etching through when a contact hole is opened.

  2 and 3 again, the lower light-shielding film 11a is provided in a lattice shape below the TFT 30 on the TFT array substrate 10. FIG. The lower light-shielding film 11 a is made of various conductive light-shielding films containing metal, like the capacitor line 300 or the relay layer 71 described above. Preferably, it is a film that can withstand a high-temperature process when forming the TFT 30 after the formation of the lower light-shielding film 11a, for example, Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), Mo ( Molybdenum), Pb (lead), and the like including at least one of refractory metals such as a simple metal, an alloy, a metal silicide, a polysilicide, and a laminate of these.

  Therefore, in this embodiment, the semiconductor layer 1a is sandwiched between the lower light-shielding film 11a having a relatively small interlayer distance and the lattice-shaped upper light-shielding film including the capacitor line 300, the relay layer 71, and the data line 6a as described above. Therefore, basically a very high light shielding performance can be obtained with respect to the incident light and the return light. Further, as shown in FIGS. 4 and 5, the contact hole 85 and its periphery are also high. Shading performance can be obtained.

  Note that the lower light-shielding film 11a is also extended from the image display area to the periphery thereof in order to prevent the potential fluctuation from adversely affecting the TFT 30, as in the case of the capacitance line 300 described above. It may be connected to a potential source.

  2 and 3, the electro-optical device includes a transparent TFT array substrate 10 and a transparent counter substrate 20 disposed to face the TFT array substrate 10. The TFT array substrate 10 is made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate.

  As shown in FIG. 3, the TFT array substrate 10 is provided with a pixel electrode 9a, and an alignment film 16 subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive film such as an ITO (Indium Tin Oxide) film. The alignment film 16 is made of an organic film such as a polyimide film.

  On the other hand, a counter electrode 21 is provided over the entire surface of the counter substrate 20, and an alignment film 22 subjected to a predetermined alignment process such as a rubbing process is provided below the counter electrode 21. The counter electrode 21 is made of a transparent conductive film such as an ITO film. The alignment film 22 is made of an organic film such as a polyimide film.

  The counter substrate 20 may be provided with a lattice-shaped or striped light-shielding film. By adopting such a configuration, the light incident on the counter substrate 20 side by the light shielding film on the counter substrate 20 together with the capacitor line 300, the relay layer 71, and the data line 6a constituting the lattice-shaped upper light shielding film as described above. It is possible to more reliably prevent light from entering the channel region 1a ′, the low concentration source region 1b, and the low concentration drain region 1c. Further, such a light shielding film on the counter substrate 20 functions to prevent a temperature increase of the electro-optical device by forming at least a surface irradiated with incident light with a highly reflective film. In this way, the light shielding film on the counter substrate 20 is preferably formed so as to be positioned inside the light shielding layer composed of the capacitor line 300 and the data line 6a in plan view. As a result, the light shielding film on the counter substrate 20 can provide such light shielding and temperature rise prevention effects without reducing the aperture ratio of each pixel.

  Between the TFT array substrate 10 and the counter substrate 20, which are arranged in such a manner so that the pixel electrode 9 a and the counter electrode 21 face each other, an electro-optical material is placed in a space surrounded by a seal material described later. A liquid crystal layer 50 is formed by encapsulating liquid crystal as an example. The liquid crystal layer 50 takes a predetermined alignment state by the alignment films 16 and 22 in a state where an electric field from the pixel electrode 9a is not applied. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed. The sealing material is an adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the TFT array substrate 10 and the counter substrate 20 around them, and the distance between the two substrates is set to a predetermined value. Gap materials such as glass fibers or glass beads are mixed.

  Further, a base insulating film 12 is provided under the pixel switching TFT 30. The base insulating film 12 is formed on the entire surface of the TFT array substrate 10 in addition to the function of interlayer insulating the TFT 30 from the lower light-shielding film 11a, and thus remains rough after polishing the surface of the TFT array substrate 10 and after cleaning. It has a function of preventing deterioration of the characteristics of the pixel switching TFT 30 due to dirt or the like.

  In FIG. 3, the pixel switching TFT 30 has an LDD (Lightly Doped Drain) structure, and includes a scanning line 3a, a channel region 1a ′ of the semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, and scanning. Insulating film 2 including a gate insulating film that insulates line 3a from semiconductor layer 1a, low concentration source region 1b and low concentration drain region 1c of semiconductor layer 1a, high concentration source region 1d and high concentration drain region 1e of semiconductor layer 1a It has.

  On the scanning line 3a, a first interlayer insulating film 41 is formed in which a contact hole 81 leading to the high concentration source region 1d and a contact hole 83 leading to the high concentration drain region 1e are respectively opened.

  A relay layer 71 and a capacitor line 300 are formed on the first interlayer insulating film 41, and a contact hole 81 and a contact hole 85 leading to the high-concentration source region 1d and the relay layer 71, respectively, are opened thereon. A holed second interlayer insulating film 42 is formed.

  In this embodiment, the first interlayer insulating film 41 is baked at about 1000 ° C. to activate ions implanted into the polysilicon film constituting the semiconductor layer 1a and the scanning line 3a. May be. On the other hand, the stress generated in the vicinity of the interface of the capacitor line 300 may be reduced by not performing such firing on the second interlayer insulating film 42.

  A data line 6 a is formed on the second interlayer insulating film 42, and a third interlayer insulating film 43 in which a contact hole 85 leading to the relay layer 71 is formed is formed thereon. The pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 43 thus configured.

  In the present embodiment, as shown in FIG. 3, by laminating a plurality of conductive layers having a predetermined pattern, the data lines 6a and scanning lines on the lower ground of the pixel electrode 9a (that is, the surface of the third interlayer insulating film 43). The level difference in the region along 3a is alleviated by planarizing the surface of the third interlayer insulating film 43. For example, it is mitigated by polishing by CMP (Chemical Mechanical Polishing) or the like, or by forming it flat using organic SOG (Spin On Glass). As described above, by reducing the step between the region where the wiring, the element, etc. are present and the region where the wiring, element, etc. are not present, it is possible to ultimately reduce image defects such as liquid crystal alignment failure due to the step. However, instead of or in addition to performing the planarization process on the third interlayer insulating film 43 in this way, of the TFT array substrate 10, the base insulating film 12, the first interlayer insulating film 41, and the second interlayer insulating film 42. The flattening process may be performed by digging a groove in at least one and embedding the wiring such as the data line 6a or the TFT 30 or the like.

  As described above with reference to FIGS. 1 to 6, according to the electro-optical device of this embodiment, a relatively large capacitance can be obtained in a limited region on the substrate by constructing the storage capacitor 70 having the MIM structure. As a result, high shading performance can be realized, and finally, high-quality image display becomes possible by an active matrix driving method using TFT 30 having excellent transistor characteristics while using strong incident light.

  In the embodiment described above, the pixel switching TFT 30 preferably has an LDD structure as shown in FIG. 3, but does not implant impurities into the low concentration source region 1b and the low concentration drain region 1c. Alternatively, the TFT may be a self-aligned TFT in which a high concentration source and drain regions are formed in a self-aligned manner by implanting impurities at a high concentration using a gate electrode formed of a part of the scanning line 3a as a mask. In this embodiment, only one gate electrode of the pixel switching TFT 30 is arranged between the high concentration source region 1d and the high concentration drain region 1e. However, two or more gate electrodes are provided between these gate electrodes. You may arrange. If the TFT is configured with dual gates or triple gates or more in this way, leakage current at the junction between the channel and the source and drain regions can be prevented, and the off-time current can be reduced.

(Second Embodiment)
Next, an electro-optical device according to a second embodiment of the invention will be described with reference to FIG. FIG. 7 is a schematic partial cross-sectional view showing a stacked structure of storage capacitors in the second embodiment.

  As shown in FIG. 7, in the second embodiment, the capacitor line 300 including the fixed potential side capacitor electrode is formed of a laminate in which an Al film 300b is sandwiched between TiN films 300a and 300c from both sides. About another structure, it is the same as that of the case of 1st Embodiment mentioned above.

  Therefore, according to the second embodiment, the light shielding performance can be enhanced by the TiN films 300a and 300c while the resistance of the capacitor line 300 is reduced by the Al film 300b. In particular, the TiN film has a reflectivity that is a fraction of that of the Al film. Therefore, by adopting the configuration of the present embodiment, it is possible to generate internally reflected light and multiple reflected light due to incident light and return light. Can be prevented.

  In the second embodiment, the capacitor line 300 is composed of a laminated body in which an Al film is sandwiched between TiN films, but from a laminated body including a normal metal, a refractory metal, a silicide, a Si film, a SiGe film, and the like. The capacitor line 300 may be configured, or the relay layer 71 may be configured from such a laminated body instead of or in addition to the capacitor line 300. Among these, in particular, when a laminated body including a SiGe film having a small band gap is used, a relatively strong light absorbing action can be obtained by the SiGe film.

(Third embodiment)
Next, an electro-optical device according to a third embodiment of the invention will be described with reference to FIG. FIG. 8 is a schematic partial cross-sectional view showing a stacked structure of storage capacitors in the third embodiment.

  As shown in FIG. 8, in the third embodiment, the capacitor line 300 including the fixed potential side capacitor electrode is formed of a stacked body in which an Al film 300e is stacked on a TiN film 300d. The relay layer 71 is a laminate in which a Pt film 71b is laminated on a conductive polysilicon film 71a. About another structure, it is the same as that of the case of 1st Embodiment mentioned above.

  Therefore, according to the third embodiment, the light shielding performance of the capacitor line 300 can be improved by the TiN film 300d while the resistance of the capacitor line 300 is reduced by the Al film 300e. In particular, the TiN film has a reflectivity that is a fraction of that of the Al film. Therefore, by adopting the configuration of the present embodiment, it is particularly possible to reflect the inner surface of the return light and the light traveling upward in the figure. Generation of light and multiple reflected light can be somewhat prevented. On the other hand, the resistance of the relay layer 71 can be reduced by the Pt film 71b, and the light shielding performance can be improved. Further, while the resistance of the relay layer 71 is reduced by the conductive polysilicon film 71a, the internal reflection of the return light and the light traveling upward in the figure by the light absorption action in the polysilicon film 71a. Generation of light and multiple reflected light can be remarkably prevented. If such a polysilicon film 71a is formed of the same film as the semiconductor layer 1a, the manufacturing process and the laminated structure on the substrate can be simplified.

  In the third embodiment, the polysilicon film 71a is used as the light absorption layer constituting the laminate of the relay layer 71. Instead, the relay layer 71 is made of amorphous silicon, single crystal silicon, SiGe material layer, or the like. A laminated body may be configured, and further, the light absorption layer may be arranged on the upper side in FIG.

(Fourth embodiment)
Next, an electro-optical device according to a fourth embodiment of the invention will be described with reference to FIG. FIG. 9 is a schematic partial cross-sectional view showing a stacked structure of storage capacitors in the third embodiment. FIG. 9 shows a stacked structure of the storage capacitor particularly in the vicinity of the contact hole 85.

  As shown in FIG. 9, in the fourth embodiment, the relay layer 71 is formed of a stacked body in which an AlN film 71d is stacked on an Al film 71c. About another structure, it is the same as that of the case of 1st Embodiment mentioned above.

  Therefore, according to the fourth embodiment, a good ohmic contact can be obtained between the pixel electrode 9a made of an ITO film and the relay layer 71 made of an AlN film, which are in phase contact via the contact hole 85. In addition, a good light shielding performance can be obtained by the relay layer 71 formed of the laminate including the Al film 71c and the AlN film 71d.

  In the fourth embodiment, the pixel electrode 9a is formed of an ITO film, and the pixel potential side capacitor electrode 71 is formed of an AlN film that can be in ohmic contact with the ITO film. However, the pixel electrode is formed of an IZO (Indium Zinc Oxide) film. Then, ohmic contact with the Al film can be obtained.

  Particularly in the first to fourth embodiments described above, the non-opening region in each pixel is defined by the upper light shielding film including the capacitor line 300, the relay layer 71, and the data line 6a. Accordingly, the channel region 1a ′ can be shielded from light at a position relatively close to the TF 30, and the light shielding performance can be improved as compared with the case where light shielding is performed by the light shielding film formed on the counter substrate 20, for example. Therefore, it is almost unnecessary to widen the non-opening region in view of the positional deviation and the dimensional deviation.

  In the first to fourth embodiments described above, as shown in FIG. 10A, when viewed in plan, the lattice-shaped upper light-shielding film including the data line 6a, the capacitor line 300, and the relay layer 71 is used. Is preferably larger in outline than the lattice-shaped lower light-shielding film 11a, and the lower light-shielding film 11a has a larger outline than the scanning line 3a including the gate electrode. With this configuration, it is possible to reduce components reflected from the upper surface of the lower light-shielding film 11a through the side of the upper light-shielding film among the light incident from the upper side. The reflected light can be reduced as much as possible. On the other hand, since the lower light-shielding film 11a has a larger contour than the scanning line 3a, the component incident on the scanning line 3a through the side of the lower light-shielding film 11a can be reduced as much as possible.

  As a modification, in the first to fourth embodiments described above, as shown in FIG. 10B, instead of the lattice-shaped lower light-shielding film 11a, the stripe-shaped lower portion along the scanning line 3a is used. The side light shielding film 11b may be formed. Also in this case, the lattice-shaped upper light shielding film composed of the data line 6a, the capacitor line 300, and the relay layer 71 has a larger contour than the lower light shielding film 11b, and the lower light shielding film 11b has the scanning line 3a including the gate electrode. It is preferable that the contour is larger than that. If comprised in this way, the component which passes along the side of an upper side light shielding film and reflects on the upper surface of the lower side light shielding film 11a among the light incident from the upper part can be reduced, and among the light incident from the lower side, a lower light shielding film The component that passes through the side of 11a and enters the scanning line 3a can be reduced as much as possible.

(Manufacturing process)
Next, a manufacturing process of the above-described electro-optical device according to the first embodiment will be described with reference to FIGS. FIG. 11 and FIG. 12 are process drawings sequentially showing the laminated structure of the electro-optical device in each step of the manufacturing process in the portion related to the vicinity of the semiconductor layer 1a in the cross-sectional view of FIG.

First, as shown in step (1) of FIG. 11, a TFT array substrate 10 such as a quartz substrate, hard glass, or silicon substrate is prepared. Here, annealing is preferably performed in an inert gas atmosphere such as N ₂ (nitrogen) and at a high temperature of about 900 to 1300 ° C., and pretreatment is performed so as to reduce distortion generated in the TFT array substrate 10 in a high-temperature process to be performed later. Keep it.

  Subsequently, a metal alloy film such as a metal such as Ti, Cr, W, Ta, Mo, and Pd or a metal silicide is formed on the entire surface of the TFT array substrate 10 thus processed by sputtering to a film having a thickness of about 100 to 500 nm. A light shielding film having a thickness, preferably about 200 nm, is formed. Then, the lower light-shielding film 11a having a planar lattice shape is formed by photolithography and etching.

  Next, in step (2), TEOS (tetraethyl orthosilicate) gas, TEB (tetraethyl boatrate) gas, TMOP is formed on the lower light-shielding film 11a by, for example, atmospheric pressure or low pressure CVD. A base insulating film 12 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed using (tetra-methyl-oxy-phosphate) gas or the like. The thickness of the base insulating film 12 is, for example, about 500 to 2000 nm.

  Subsequently, low pressure CVD (for example, pressure) using monosilane gas, disilane gas or the like at a flow rate of about 400 to 600 cc / min on the base insulating film 12 in a relatively low temperature environment of about 450 to 550 ° C., preferably about 500 ° C. An amorphous silicon film is formed by CVD of about 20 to 40 Pa. Thereafter, annealing is performed in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours, preferably 4 to 6 hours, so that the polysilicon film has a grain size of about 50 to 200 nm, preferably Solid phase growth is performed until the particle size becomes about 100 nm. As a method for solid phase growth, annealing using RTA (Rapid Thermal Anneal) may be used, or laser annealing using an excimer laser or the like may be used. At this time, depending on whether the TFT 30 for pixel switching is an n-channel type or a p-channel type, a dopant of a group V element or a group III element may be slightly doped by ion implantation or the like. Then, a semiconductor layer 1a having a predetermined pattern is formed by photolithography and etching.

  Subsequently, the semiconductor layer 1a constituting the TFT 30 is thermally oxidized at a temperature of about 900 to 1300 ° C., preferably at a temperature of about 1000 ° C., to form a lower gate insulating film. Subsequently, an upper gate insulating film is formed, whereby the insulating film 2 (including the gate insulating film) made of a multilayer high-temperature silicon oxide film (HTO film) or silicon nitride film is formed. As a result, the semiconductor layer 1a has a thickness of about 30 to 150 nm, preferably about 35 to 50 nm, and the insulating film 2 has a thickness of about 20 to 150 nm, preferably about 30 to 100 nm. It becomes thickness.

  Subsequently, in order to control the threshold voltage Vth of the TFT 30 for pixel switching, the N channel region or the P channel region of the semiconductor layer 1a is doped with a predetermined amount of dopant such as boron by ion implantation or the like. To do.

  Next, in step (3), a polysilicon film is deposited by a low pressure CVD method or the like, and phosphorus (P) is further thermally diffused to make the polysilicon film conductive. Alternatively, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film may be used. The thickness of this polysilicon film is about 100 to 500 nm, preferably about 350 nm. Then, a scanning line 3a having a predetermined pattern including the gate electrode portion of the TFT 30 is formed by photolithography and etching.

For example, when the TFT 30 is an n-channel TFT having an LDD structure, the scanning line 3a (gate electrode) is used as a mask to form the low concentration source region 1b and the low concentration drain region 1c in the semiconductor layer 1a. A dopant of a group V element such as P is doped at a low concentration (for example, P ions are doped at a dose of 1 to 3 × 10 ¹³ / cm ² ). As a result, the semiconductor layer 1a under the scanning line 3a becomes a channel region 1a ′. Further, in order to form the high concentration source region 1d and the high concentration drain region 1e constituting the pixel switching TFT 30, a resist layer having a planar pattern wider than the scanning line 3a is formed on the scanning line 3a. Thereafter, a dopant of a group V element such as P is doped at a high concentration (for example, P ions at a dose of 1 to 3 × 10 ¹⁵ / cm ² ). For example, an TFT having an offset structure may be used without doping at a low concentration, or a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, or the like using the scanning line 3a as a mask. The scanning line 3a is further reduced in resistance by doping of the impurities.

  Next, in step (4) of FIG. 12, silicate such as NSG, PSG, BSG, BPSG is used on the scanning line 3a by using, for example, TEOS gas, TEB gas, TMOP gas, etc. by atmospheric pressure or low pressure CVD method. A first interlayer insulating film 41 made of a glass film, a silicon nitride film, a silicon oxide film, or the like is formed. The film thickness of the first interlayer insulating film 41 is, for example, about 500 to 2000 nm. Here, preferably, annealing is performed at a high temperature of about 800 ° C. to improve the film quality of the first interlayer insulating film 41.

  Subsequently, the contact holes 83 are simultaneously opened by dry etching such as reactive ion etching and reactive ion beam etching for the first interlayer insulating film 41.

  Subsequently, a metal film such as Pt is formed on the first interlayer insulating film 41 to a thickness of about 100 to 500 nm by sputtering. Then, a relay layer 71 having a predetermined pattern is formed by photolithography and etching.

  Subsequently, a dielectric film 75 made of an insulating film such as a TaOx film is formed on the relay layer 71 by plasma CVD or the like. The dielectric film 75 may be composed of either a single layer film or a multilayer film as in the case of the insulating film 2 and is generally formed by various known techniques used for forming a gate insulating film of a TFT. Is possible. As the dielectric film 75 is made thinner, the storage capacitor 70 becomes larger. Consequently, the dielectric film is formed so as to be an extremely thin insulating film having a thickness of 50 nm or less on the condition that defects such as film breakage do not occur. It is advantageous to form 75.

  Subsequently, a metal film such as Al is formed on the dielectric film 75 to a thickness of about 100 to 500 nm by sputtering. Then, the capacitor line 300 having a predetermined pattern is formed by photolithography and etching. That is, the storage capacitor 70 is completed.

  Next, in the step (5), for example, a second interlayer made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like using atmospheric pressure or reduced pressure CVD method, TEOS gas, or the like. An insulating film 42 is formed. The film thickness of the first interlayer insulating film 42 is, for example, about 500 to 1500 nm.

  Subsequently, the contact hole 81 is opened by dry etching such as reactive ion etching or reactive ion beam etching for the second interlayer insulating film 42.

  Subsequently, the entire surface of the second interlayer insulating film 42 is deposited to a thickness of about 100 to 500 nm, preferably about 300 nm, as a metal film by using a low-resistance metal such as light-shielding Al or metal silicide by sputtering or the like. To do. Then, the data line 6a having a predetermined pattern is formed by photolithography and etching.

  Next, in step (6), a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, or the like is used so as to cover the data line 6a using, for example, atmospheric pressure or reduced pressure CVD or TEOS gas. A third interlayer insulating film 43 made of a silicon oxide film or the like is formed. The film thickness of the third interlayer insulating film 43 is, for example, about 500 to 1500 nm.

  Subsequently, a contact hole 85 (see FIG. 2 to FIG. 4) (not shown) is opened by dry etching such as reactive ion etching and reactive ion beam etching for the third interlayer insulating film 43.

  Subsequently, a transparent conductive film such as an ITO film is deposited on the third interlayer insulating film 43 to a thickness of about 50 to 200 nm by sputtering or the like. Then, the pixel electrode 9a is formed by photolithography and etching. When the liquid crystal device is used for a reflective liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.

  Subsequently, after applying a polyimide alignment film coating solution on the pixel electrode 9a, the alignment film 16 (see FIG. 3) is subjected to a rubbing process so as to have a predetermined pretilt angle and in a predetermined direction. Is formed.

  On the other hand, with respect to the counter substrate 20 shown in FIG. 3, a glass substrate or the like is first prepared, and a light shielding film as a frame is formed, for example, by sputtering metal chromium and then performing photolithography and etching. These light shielding films do not need to be conductive, and may be formed of a material such as resin black in which carbon or Ti is dispersed in a photoresist in addition to a metal material such as Cr, Ni, or Al.

  Thereafter, a transparent conductive film such as ITO is deposited on the entire surface of the counter substrate 20 by sputtering or the like to a thickness of about 50 to 200 nm, thereby forming the counter electrode 21. Further, after applying a polyimide-based alignment film coating solution over the entire surface of the counter electrode 21, the alignment film 22 (see FIG. 3) is formed by performing a rubbing process in a predetermined direction so as to have a predetermined pretilt angle. It is formed.

  Finally, the TFT array substrate 10 on which the respective layers are formed as described above and the counter substrate 20 are bonded together by a sealing material (see FIGS. 13 and 14) so that the alignment films 16 and 22 face each other, and vacuum suction or the like is performed. Thus, for example, liquid crystal formed by mixing a plurality of types of nematic liquid crystal is sucked into the space between the two substrates to form the liquid crystal layer 50 having a predetermined layer thickness.

  The electro-optical device according to the first embodiment described above can be manufactured by the manufacturing process described above.

  On the other hand, when the electro-optical device according to the second embodiment shown in FIG. 7 is manufactured, in the step (4) of FIG. 12, the capacitor line 300 is repeatedly performed by sputtering, vacuum deposition, CVD, or the like. A stacked layer may be formed. When the electro-optical device according to the third embodiment shown in FIG. 8 is manufactured, in the step (4) of FIG. 12, the relay layer 71 and the capacitor line 300 are repeated by sputtering, vacuum deposition, CVD, etc., respectively. What is necessary is just to carry out lamination | stacking by doing. When the electro-optical device of the fourth embodiment shown in FIG. 9 is manufactured, in step (4) of FIG. 12, the relay layer 71 is formed by repeatedly performing sputtering, vacuum evaporation, CVD, or the like. Further, in the step (6) of FIG. 12, an IZO film may be formed instead of the ITO film.

(Overall configuration of electro-optical device)
The overall configuration of the electro-optical device according to each embodiment configured as described above will be described with reference to FIGS. 13 and 14. FIG. 13 is a plan view of the TFT array substrate 10 as viewed from the counter substrate 20 side together with the components formed thereon, and FIG. 14 is a cross-sectional view taken along the line HH ′ of FIG.

  In FIG. 13, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof, and a light shielding film 53 serving as a frame defining the periphery of the image display region 10a is provided in parallel to the inside thereof. Is provided. In a region outside the sealing material 52, a data line driving circuit 101 and an external circuit connection terminal 102 for driving the data line 6a by supplying an image signal to the data line 6a at a predetermined timing along one side of the TFT array substrate 10. A scanning line driving circuit 104 that drives the scanning line 3a by supplying a scanning signal to the scanning line 3a at a predetermined timing is provided along two sides adjacent to the one side. Needless to say, if the delay of the scanning signal supplied to the scanning line 3a is not a problem, the scanning line driving circuit 104 may be provided on only one side. The data line driving circuit 101 may be arranged on both sides along the side of the image display area 10a. Further, on the remaining side of the TFT array substrate 10, a plurality of wirings 105 are provided for connecting between the scanning line driving circuits 104 provided on both sides of the image display region 10a. In addition, at least one corner of the counter substrate 20 is provided with a conductive material 106 for electrical connection between the TFT array substrate 10 and the counter substrate 20. As shown in FIG. 14, the counter substrate 20 having substantially the same outline as the sealing material 52 shown in FIG. 13 is fixed to the TFT array substrate 10 by the sealing material 52.

  On the TFT array substrate 10, in addition to the data line driving circuit 101, the scanning line driving circuit 104 and the like, a sampling circuit for applying an image signal to the plurality of data lines 6a at a predetermined timing, and a plurality of data lines A precharge circuit for supplying a precharge signal of a predetermined voltage level in advance to the image signal to 6a, an inspection circuit for inspecting quality, defects, etc. of the electro-optical device during manufacture or at the time of shipment are formed. Also good.

  In the embodiment described above with reference to FIGS. 1 to 14, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, they are mounted on a TAB (Tape Automated Bonding) substrate. The drive LSI may be electrically and mechanically connected via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. Further, for example, a TN (Twisted Nematic) mode, a VA (Vertically Aligned) mode, and a PDLC (Polymer Dispersed Liquid Crystal) are respectively provided on the side on which the projection light of the counter substrate 20 enters and the side on which the emission light of the TFT array substrate 10 exits. ) Mode or the like, or a normally white mode / normally black mode, a polarizing film, a retardation film, a polarizing plate, etc. are arranged in a predetermined direction.

  Since the electro-optical device in the embodiment described above is applied to a projector, three electro-optical devices are respectively used as RGB light valves, and each light valve is connected to a dichroic mirror for RGB color separation. The light of each color that has been decomposed is incident as projection light. Therefore, in each embodiment, the counter substrate 20 is not provided with a color filter. However, an RGB color filter may be formed on the counter substrate 20 together with its protective film in a predetermined region facing the pixel electrode 9a. In this way, the electro-optical device in each embodiment can be applied to a direct-view type or reflective type color electro-optical device other than the projector. Further, micro lenses may be formed on the counter substrate 20 so as to correspond to one pixel. Alternatively, it is also possible to form a color filter layer with a color resist or the like under the pixel electrodes 9 a facing RGB on the TFT array substrate 10. In this way, a bright electro-optical device can be realized by improving the collection efficiency of incident light. Furthermore, a dichroic filter that produces RGB colors by using interference of light may be formed by depositing several layers of interference layers having different refractive indexes on the counter substrate 20. According to this counter substrate with a dichroic filter, a brighter color electro-optical device can be realized.

(Embodiment of electronic device)
Next, an overall configuration, particularly an optical configuration, of an embodiment of a projection color display device as an example of an electronic apparatus using the electro-optical device described in detail as a light valve will be described. FIG. 15 is a schematic sectional view of the projection type color display device.

  In FIG. 15, a liquid crystal projector 1100, which is an example of a projection type color display device according to the present embodiment, prepares three liquid crystal modules including a liquid crystal device 100 in which a drive circuit is mounted on a TFT array substrate. It is configured as a projector used as the valves 100R, 100G, and 100B. In the liquid crystal projector 1100, when projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, light components R, G, and R corresponding to the three primary colors of RGB are obtained by three mirrors 1106 and two dichroic mirrors 1108. B is divided into the light valves 100R, 100G and 100B corresponding to the respective colors. At this time, in particular, the B light is guided through a relay lens system 1121 including an incident lens 1122, a relay lens 1123, and an exit lens 1124 in order to prevent light loss due to a long optical path. The light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are synthesized again by the dichroic prism 1112 and then projected as a color image on the screen 1120 via the projection lens 1114.

  The present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the gist or concept of the invention that can be read from the claims and the entire specification. In addition, electro-optical devices are also included in the technical scope of the present invention.

3 is an equivalent circuit of various elements, wirings, and the like provided in a plurality of pixels in a matrix form constituting an image display region in the electro-optical device according to the first embodiment of the present invention. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed in the electro-optical device of the first embodiment. FIG. It is A-A 'sectional drawing of FIG. 2 in 1st Embodiment. FIG. 3 is a schematic partial perspective view showing a contact hole connecting a pixel potential side capacitor electrode to a pixel electrode and light shielding in the vicinity thereof in the first embodiment. FIG. 6 is a schematic partial perspective view showing a state of light shielding in and around a contact hole connecting a pixel potential side capacitor electrode to a pixel electrode in a comparative example. FIG. 3 is a schematic partial cross-sectional view showing an MIM structure having a storage capacitor in the first embodiment. FIG. 5 is a schematic partial cross-sectional view showing an MIM structure having a storage capacitor in a second embodiment. It is a schematic fragmentary sectional view showing the MIM structure which storage capacity in a 3rd embodiment has. It is a typical fragmentary sectional view showing the MIM structure which storage capacity in a 4th embodiment has. It is a top view which shows the preferable magnitude relationship between the upper side light shielding film, scanning line, and lower side light shielding film in each embodiment. FIG. 5 is a process diagram (part 1) illustrating the stacked structure of the electro-optical device in each step of the manufacturing process according to the first embodiment in order in a portion related to the vicinity of a semiconductor layer. FIG. 10 is a process diagram (part 2) illustrating the stacked structure of the electro-optical device in each step of the manufacturing process according to the first embodiment in order in a portion related to the vicinity of a semiconductor layer. FIG. 5 is a plan view of the TFT array substrate in the electro-optical device according to the embodiment as viewed from the side of the counter substrate together with each component formed thereon. It is H-H 'sectional drawing of FIG. 1 is a schematic cross-sectional view showing a color liquid crystal projector as an example of a projection type color display device which is an embodiment of an electronic apparatus of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a ... Semiconductor layer, 1a '... Channel region, 1b ... Low concentration source region, 1c ... Low concentration source region, 1d ... High concentration source region, 1e ... High concentration drain region, 2 ... Insulating film, 3a ... Scan line, 6a Data line, 9a ... Pixel electrode, 10 ... TFT array substrate, 11a ... Lower light shielding film, 12 ... Underlying insulating film, 16 ... Alignment film, 20 ... Counter substrate, 21 ... Counter electrode, 22 ... Alignment film, 30 ... TFT, 50 ... Liquid crystal layer, 70 ... Storage capacitor, 71 ... Relay layer, 75 ... Dielectric film, 81, 83, 85 ... Contact hole, 300 ... Capacitor line.

Claims (17)

On the board
A pixel electrode;
A thin film transistor connected to the pixel electrode;
A scan line and a data line connected to the thin film transistor;
A pixel potential side capacitor electrode connected to the pixel electrode and constituting a storage capacitor;
A capacitor line including a fixed potential side capacitor electrode that is disposed opposite to the pixel potential side capacitor electrode via a dielectric film and constitutes the storage capacitor, and
Each of the pixel potential side capacitor electrode and the fixed potential side capacitor electrode includes a metal. The pixel potential side capacitor electrode is connected to the pixel electrode through a contact hole,
The capacitor line is provided with a notch so as to avoid the contact hole in plan view,
2. The substrate device according to claim 1, wherein each of the pixel potential side capacitor electrode and the fixed potential side capacitor electrode includes a light-shielding metal film. The pixel potential side capacitor electrode is connected to the thin film transistor through a contact hole,
The capacitor line is provided with a notch so as to avoid the contact hole in plan view,
2. The substrate device according to claim 1, wherein each of the pixel potential side capacitor electrode and the fixed potential side capacitor electrode includes a light-shielding metal film.   4. The fixed potential side capacitive electrode on the substrate is formed on the pixel potential side capacitive electrode with the dielectric film interposed therebetween. Board equipment.   4. The device according to claim 1, wherein the fixed potential side capacitive electrode is formed on the substrate below the pixel potential side capacitive electrode via the dielectric film. 5. Board equipment. The dielectric film includes TaOx (tantalum oxide), BST (barium strontium titanate), PZT (lead zirconate titanate), TiO ₂ (titanium oxide), ZrO ₂ (zirconium oxide), HfO ₂ (hafnium oxide), 6. The substrate device according to claim 1, comprising at least one of SiO ₂ (silicon oxide), SiON (silicon oxynitride), and SiN (silicon nitride). 7.   The pixel potential side capacitor electrode and the fixed potential side capacitor electrode are made of Pt (platinum), Ru (ruthenium), TiN (titanium nitride), TaN (tantalum nitride), SRO (strontium ruthenate) and Al (aluminum), respectively. The substrate apparatus according to claim 1, wherein at least one of them is included.   The substrate device according to claim 7, wherein the pixel potential side capacitance electrode includes Pt, and the fixed potential side capacitance electrode includes Al.   8. The substrate device according to claim 7, wherein the pixel potential side capacitor electrode includes TiN, and the fixed potential side capacitor electrode includes Al.   10. The substrate device according to claim 1, wherein at least one of the pixel potential side capacitor electrode and the fixed potential side capacitor electrode is formed of a stacked body. 11. The pixel potential side capacitor electrode is made of the laminate,
The laminate includes an Al film and an AlN film,
The pixel electrode is made of an ITO (Indium Tin Oxide) film,
11. The substrate device according to claim 10, wherein the pixel potential side capacitor electrode and the pixel electrode are connected by the AlN film and the pixel electrode being in electrical contact with each other.   The substrate device according to claim 10, wherein the stacked body includes a light absorption layer containing silicon and a light shielding layer containing metal.   The electro-optical device according to claim 12, wherein the light absorption layer is formed of the same layer as a semiconductor layer constituting the thin film transistor.   14. The non-opening region in each pixel is defined by at least one of the pixel potential side capacitor electrode and the capacitor line and the data line. 14. Board equipment. On the substrate, further comprises a lower light-shielding film covering at least the channel region of the thin film transistor from the lower side,
The substrate apparatus according to claim 14, wherein the lower light-shielding film has a smaller outline than the non-opening region when seen in a plan view.   An electro-optical device, wherein an electro-optical material is sandwiched between the substrate device according to claim 1 and another substrate. An electronic apparatus comprising the electro-optical device according to claim 16.

Images