JP2000299468A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Problem] To provide a semiconductor device having a high performance and a bright image by arranging a TFT having an appropriate structure according to circuit performance and reducing an area occupied by a storage capacitor. SOLUTION: The thickness of a gate insulating film is made different between a circuit which emphasizes an operation speed and a circuit which emphasizes a gate withstand voltage, and an LDD region is used for a TFT which emphasizes hot carrier measures and a TFT which emphasizes off current measures. Are formed at different positions. Thereby, a high-performance semiconductor device is realized. Further, by forming a storage capacitor using a light-shielding film and its oxide, the area of the storage capacitor is minimized, and a semiconductor device capable of displaying a bright image is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter, referred to as TFTs). For example, the present invention relates to an electronic device represented by a liquid crystal display and a configuration of an electric appliance using such an electronic device as a display unit. Note that in this specification, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics, and an electronic device, a semiconductor circuit, and an electric appliance are all semiconductor devices.

[0002]

2. Description of the Related Art Since thin film transistors (TFTs) can be formed on a transparent substrate, application development to an active matrix type liquid crystal display (hereinafter, referred to as AM-LCD) has been actively promoted. Since a TFT using a crystalline semiconductor film (typically, a polysilicon film) has high mobility, it is possible to realize a high-definition image display by integrating functional circuits on the same substrate. I have.

Basically, an AM-LCD has a pixel portion for displaying an image, a gate drive circuit for driving a TFT of each pixel arranged in the pixel portion, and a source drive circuit (or data drive circuit) for sending an image signal to each TFT. ) Are formed on the same substrate. In this specification, the gate drive circuit and the source drive circuit are collectively referred to as a drive circuit portion.

In recent years, a system-on-panel has been proposed in which a signal processing circuit such as a signal dividing circuit and a gamma correction circuit is provided on the same substrate in addition to the pixel section and the driving circuit section.

However, since the performance required by the circuit is different between the pixel portion and the drive circuit portion, it is difficult to satisfy all the circuit specifications with the TFT having the same structure. That is,
At present, a TFT structure that satisfies a drive circuit unit such as a shift register circuit that emphasizes high-speed operation and a TFT that constitutes a pixel unit that emphasizes high withstand voltage characteristics (hereinafter referred to as pixel TFT) has not been established at present. is there.

Therefore, the applicant of the present invention has proposed a T
A configuration has been filed in which the thickness of the gate insulating film is made different between an FT (hereinafter, referred to as a driving TFT) and a pixel TFT (see Japanese Patent Application Laid-Open No. 10-056184). Specifically, the gate insulating film of the driving TFT is made thinner than the gate insulating film of the pixel TFT.

[0007]

Recently, in order to realize a high-definition screen of XGA (1024.times.768 pixels) on a liquid crystal panel having a diagonal width of 0.9 inches, one pixel of a pixel portion is 18 .mu.m.times.18 .mu.m. The area is extremely small. Such reduction in pixel size is expected to continue in the future.

The biggest problem caused by such a reduction in pixel size is a reduction in aperture ratio in a transmission type liquid crystal display. That is, the effective area of the image display is reduced, and the brightness is reduced. Furthermore, in order to increase the aperture ratio, it is necessary to take measures such as reducing the area occupied by the TFT or the area occupied by the storage capacitor.

As described above, with the reduction in the pixel size, the requirements for the performance and the occupied area required for the TFT become extremely strict, and in addition, the area requirement for the storage capacitor becomes strict. It becomes very difficult.

[0010] The present invention has been made in view of the above problems, and a highly reliable TFT is formed in a small area.
In addition, a pixel structure in which the area occupied by the storage capacitor is minimized is provided. An object of the present invention is to realize a bright and high-definition image even in an electronic device having a very small pixel size of several tens of μm square.

It is another object of the present invention to improve the operation performance and reliability of an electronic device by making the structure of a TFT disposed in each circuit appropriate according to the function of the circuit.

A semiconductor device (electric appliance) using such an electronic device (typically, a liquid crystal display, an electroluminescence display, an electrochromic display, or a field emission display) as a display section (display for display). It is an object to improve operation performance and reliability.

[0013]

According to an embodiment of the present invention disclosed in this specification, a semiconductor device including a pixel portion and a drive circuit portion on the same substrate includes a drive TF for forming the drive circuit portion.
The LDD region of T is disposed so as to overlap the gate wiring of the driving TFT with the gate insulating film of the driving TFT interposed therebetween, and the LDD region of the pixel TFT forming the pixel portion is
The pixel TFT sandwiching the gate insulating film of the pixel TFT
And the storage capacitor of the pixel portion is formed of a light-shielding film provided above the pixel TFT, an oxide of the light-shielding film, and a pixel electrode. .

Further, according to the structure of the invention relating to a manufacturing method, in a method of manufacturing a semiconductor device including a pixel portion and a driver circuit portion over the same substrate, a channel formation region, a source, Forming a region, a drain region, and an LDD region sandwiched between the drain region and the channel formation region; and forming a channel formation region, a source region, and a drain region in an active layer of a PTFT that forms the drive circuit unit. Forming a channel forming region, a source region, a drain region, and an LDD region sandwiched between the drain region and the channel forming region in an active layer of a pixel TFT forming the pixel portion;
And forming an LDD region of an NTFT forming the drive circuit portion so as to overlap a gate wiring of the NTFT forming the drive circuit portion with a gate insulating film interposed therebetween, and
The LDD region of the FT is formed so as not to overlap the gate wiring of the pixel TFT with a gate insulating film interposed therebetween, and
A light-blocking film provided above the FT, an oxide of the light-blocking film, and a pixel electrode form a storage capacitor of the pixel portion.

More specifically, in a method of manufacturing a semiconductor device including a pixel portion and a drive circuit portion on the same substrate, a first step of forming an active layer on the substrate, and a gate insulating film on the active layer A second step of forming a conductive film on the gate insulating film, and a fourth step of patterning the conductive film to form a gate wiring of an NTFT for forming the drive circuit portion. An NTFT forming the drive circuit section on an active layer of the NTFT forming the drive circuit section
A fifth step of adding an element belonging to Group 15 of the periodic table using the gate wiring as a mask to form an n region, and diffusing the n region by heat treatment to form an NTFT gate wiring for forming the drive circuit portion. A sixth step of forming an n ⁻ region below; a seventh step of patterning the conductive film to form a gate wiring of a pixel TFT forming the pixel portion; and forming an active layer of the pixel TFT on the active layer of the pixel TFT. Using a gate wiring as a mask, an element belonging to Group 15 of the periodic table is added, and n ⁻
An eighth step of forming a region, a ninth step of adding an element belonging to Group 15 of the periodic table to the active layer of the NTFT and the active layer of the pixel TFT forming the drive circuit section, and forming an n ⁺ region. Forming a gate wiring of a PTFT forming the drive circuit portion by patterning the conductive film;
And an eleventh step of adding an element belonging to Group 13 of the periodic table to the active layer of the PTFT forming the drive circuit unit using the gate wiring of the PTFT forming the drive circuit unit as a mask, and forming ap ⁺ region. And N which forms the drive circuit section
Forming an interlayer insulating film made of a resin film above the TFT, the PTFT and the pixel TFT forming the pixel portion;
A first step of forming a light-shielding film on the interlayer insulating film;
Three steps, a fourteenth step of forming an oxide of the light-shielding film on the surface of the light-shielding film, and a fifteenth step of forming a pixel electrode in contact with the oxide of the light-shielding film and overlapping the light-shielding film. , Is characterized by having.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view of an AM-LCD in which a drive circuit portion and a pixel portion are integrally formed on the same substrate. Here, a CMOS circuit is shown as a typical basic circuit constituting the drive circuit portion, and a TFT having a double gate structure is shown as a pixel TFT. Of course, not only the double gate structure but also a triple gate structure or a single gate structure may be used.

In FIG. 1, reference numeral 101 denotes a substrate having heat resistance, which may be a quartz substrate, a silicon substrate, a ceramic substrate, or a metal substrate (typically, a stainless steel substrate). Whichever substrate is used, a base film (preferably, an insulating film containing silicon as a main component) may be provided as necessary.

Reference numeral 102 denotes a silicon oxide film provided as a base film, on which an active layer of a driving TFT, an active layer of a pixel TFT, and a semiconductor layer serving as a lower electrode of a storage capacitor are formed. In this specification, “electrode” means “wiring”
And a portion where an electrical connection with another wiring is made or a portion that intersects with a semiconductor layer. Therefore, for convenience of explanation, “wiring” and “electrode” are used properly, but “wiring”
"Electrode" is always included in the wording.

In FIG. 1, the active layer of the driving TFT is composed of N
Source region 103, drain region 104, LDD (lightly doped drain) region 105, and channel forming region 10 of a channel type TFT (hereinafter referred to as NTFT).
6, and a source region 107, a drain region 108, and a channel formation region 109 of a P-channel TFT (hereinafter referred to as PTFT).

The active layer of the pixel TFT (here, NTFT is used) is formed of a source region 110, a drain region 111, LDD regions 112a to 112d, and channel forming regions 113a and 113b. A high-concentration impurity region 114 exists between the channel formation regions 113a and 113b, and has the same composition (contains the same impurity at the same concentration) as the source region 110 and the drain region 111. This region functions as a stopper region that prevents the movement of minority carriers generated at the drain end to the source region, which causes off current.

Then, a gate insulating film is formed to cover the active layer. In the present invention, the gate insulating film 1 of the driving TFT is formed.
15 is formed thinner than the gate insulating film 116 of the pixel TFT. Typically, the thickness of the gate insulating film 115 is 5
To 50 nm (preferably 10 to 30 nm), and the thickness of the gate insulating film 116 is 50 to 200 nm (preferably 100 to
150 nm).

The gate insulating film of the driving TFT does not need to have one kind of film thickness. That is, a driving TFT having a different insulating film may exist in the driving circuit portion.
In that case, the T substrate having different gate insulating films on the same substrate
There will be at least three or more FTs.

Next, on the gate insulating films 115 and 116, the gate wirings 117 and 118 of the driving TFT and the pixels TF
T gate electrodes 119a and 119b are formed. In addition,
The material for forming the gate wirings 117 to 119 is 800
A conductive film having heat resistance that withstands a temperature of 1 to 1150 ° C (preferably 900 to 1100 ° C) is used.

Typically, a conductive silicon film (for example, a phosphorus-doped silicon film, a boron-doped silicon film, etc.)
Or a metal film (for example, a tungsten film, a tantalum film, a molybdenum film, a titanium film, or the like), a silicide film obtained by silicidizing the metal film, or a nitrided film (a tantalum nitride film, a tungsten nitride film, a titanium nitride film, or the like). But it is good. Further, these may be freely combined and laminated.

When the metal film is used, it is preferable that the metal film has a laminated structure with a silicon film in order to prevent oxidation of the metal film (which causes an increase in wiring resistance). In terms of preventing oxidation, a structure in which a metal film is covered with an insulating film containing silicon is effective.

As the insulating film containing silicon, a silicon oxide film, a silicon nitride film, a silicon oxynitride film (also referred to as a silicon oxynitride film) can be used. Note that a silicon oxynitride film is an insulating film containing oxygen, nitrogen, and silicon at a predetermined ratio.

When a gate wiring is formed from the above material, an insulating film containing silicon is provided as the uppermost layer during film formation, and the insulating film containing silicon and the above material are etched at a time to form a gate wiring pattern. You can also. In this case, only the upper surface of the gate wiring is protected by the insulating film containing silicon.

Although the resistance is slightly higher than when a metal film is used, the laminated structure of a metal silicide film and a silicon film is effective because it has high heat resistance and is resistant to oxidation. In this case, a protective film for preventing oxidation is not particularly required, and even if oxidized as it is, only a silicon oxide film is formed on the surface, and there is no problem that the wiring resistance increases.

Next, 120 is a first interlayer insulating film (lower layer),
Reference numeral 121 denotes a first interlayer insulating film (upper layer), which is formed of an insulating film containing silicon. The source wirings 122 and 123 and the drain wiring 124 of the driving TFT and the pixel T
An FT source wiring 125 and a drain wiring 126 are formed.

A passivation film 127 is formed thereon. In the passivation film 127, an opening 128 is provided on the drain wiring 126, and a second interlayer insulating film 129 is formed so as to cover the opening 128. As the second interlayer insulating film 129, a resin film having a small relative dielectric constant is preferable. As the resin film, a polyimide film, an acrylic film, a polyamide film, BCB (benzocyclobutene)
A film, MSSQ (methylsilsesquioxane), or the like can be used.

On the second interlayer insulating film 129, a light-shielding film 130 made of an aluminum film or a film containing aluminum as a main component (a film obtained by adding another element as an impurity to the aluminum film) is formed. An oxide (alumina film) 131 obtained by oxidizing the light-shielding film 130 is formed. When patterning the light shielding film 130, 60 to 85
It is preferable to provide a taper of about °. Also,
The oxide 131 may be formed by an anodic oxidation method, a thermal oxidation method, or a plasma oxidation method. Note that as other elements used as impurities, titanium, scandium, neodymium, or silicon can be given.

Then, a contact hole is formed in the second interlayer insulating film 129, and thereafter, a pixel electrode 132 is formed. The pixel electrode 132 is electrically connected to the drain wiring 126 via a contact hole. At this time, a transparent conductive film may be used as a pixel electrode if a transmissive AM-LCD is manufactured, and a metal film with high reflectivity may be used if a reflective AM-LCD is manufactured.

In a region where the light-shielding film 130 and the pixel electrode 132 overlap, a storage capacitor having the oxide 131 as a dielectric is formed. Since the oxide 131 is an alumina film, its relative dielectric constant is as large as 8 to 10 and its thickness is 30 to 100.
nm (preferably 50 to 70 nm), a large capacitance can be formed even with a small area.

The pixel electrode 132 and the drain wiring 12
The contact hole electrically connected to 6 passes through light because it is a gap between the light-shielding films, but has a structure in which light leakage is completely prevented by the drain wiring 126 thereunder.

Further, the pixel electrode 132 is covered with the alignment film 133. A liquid crystal 134 is held on the alignment film 133. The liquid crystal 134 is held on the pixel portion by a sealing material (not shown) also serving as a spacer for the opposing substrate.

On the liquid crystal 134, the alignment film 1 on the opposite substrate side
35, a counter electrode (also referred to as a common electrode) 136 made of a transparent conductive film, and a glass substrate 137 are provided. The alignment film 135, the counter electrode 136, and the glass substrate 137
Are collectively called a counter substrate. In a single-panel liquid crystal display, a color filter is further provided on the counter substrate side.

The semiconductor device of the present invention having the above structure has the following features.

First, among the driving TFTs forming the driving circuit section, the NTD has a structure in which the LDD region 105 completely overlaps the gate wiring 117.
This is a hot carrier countermeasure aiming at the same effect as the known GOLD structure. On the other hand, the conventional structure of the PTFT is sufficient because the deterioration of the hot carrier is small.

The driving TFT is a gate insulating film 115.
Is 1/5 to the gate insulating film 116 of the pixel TFT.
Another feature is that the film thickness is about 1/10. This is a measure for improving the operation speed. Since the operation voltage is low, there is no problem even if the film thickness is 5 to 50 nm.

On the other hand, the pixel TFT differs from the driving TFT in basic circuit specifications. First, the off-current (T
Since suppression of the drain current flowing when the FT is in the off state is a priority, a normal LDD structure is employed. Therefore, the LDD regions 112a to 112d are different from the driving TFTs in that they have a structure that does not overlap the gate lines 119a and 119b.

The gate insulating film 116 has a maximum of 16
Since a high voltage of about V is applied, the film thickness is 50 to 200 nm.
(Preferably 100 to 150 nm).

Further, the light shielding film 130 is used to increase the aperture ratio.
Is characterized in that a storage capacitor is formed with the oxide 131 formed as a dielectric. The storage capacity is the light shielding film 130,
The oxide 131 and the pixel electrode 132 are formed.

As described above, the semiconductor device of the present invention has various features in the drive circuit portion and the pixel portion, and a bright and high-definition image can be obtained by the synergistic effect of these, and the operation performance and reliability are improved. Get high electronic equipment. Then, a high-performance electric appliance in which such an electronic device is mounted as a component is obtained.

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

[0045]

[Embodiment 1] In this embodiment, a manufacturing process for realizing the structure of FIG. 1 described in "Embodiment of the Invention" will be described. 2 to 5 are used for the description.

First, a quartz substrate 201 is prepared as a substrate, and a 20-nm-thick silicon oxide film 202 and an amorphous silicon film 203 are continuously formed thereon without exposing to the atmosphere. This prevents impurities such as boron contained in the air from adsorbing to the lower surface of the amorphous silicon film.
(Fig. 2 (A))

Although an amorphous silicon (amorphous silicon) film is used in this embodiment, another semiconductor film may be used. A microcrystalline silicon (microcrystalline silicon) film or an amorphous silicon germanium film may be used. Further, the film thickness is finally formed to be 25 to 40 nm in consideration of the subsequent thermal oxidation step.

Next, the amorphous silicon film is crystallized. In this embodiment, a technique described in Japanese Patent Application Laid-Open No. 9-313260 is used as a crystallization means. The technology described in the publication, nickel, cobalt, palladium, germanium, platinum, iron, copper, tin, as a catalyst element for promoting crystallization,
Uses elements selected from lead.

In this embodiment, nickel is selected as a catalyst element, a layer containing nickel (not shown) is formed on the amorphous silicon film 203, and heat treatment is performed at 550 ° C. for 4 hours for crystallization. Then, the crystalline silicon (polysilicon) film 20
Get 4. (FIG. 2 (B))

Here, an impurity element (phosphorus or boron) for controlling the threshold voltage of the TFT may be added to the crystalline silicon film 204. Phosphorus or boron may be separated, or only one of them may be added. In this case, it is preferable to add phosphorus in advance to a region which will eventually become the first capacitance electrode of the storage capacitor, since it is easier to use the electrode later.

Next, a mask film 205 made of a silicon oxide film having a thickness of 100 nm is formed on the crystalline silicon film 204, and a resist mask 206 is formed thereon. Further, the mask film 205 is etched using the resist mask 206 as a mask to form openings 207 and 208.

In this state, an element belonging to Group 15 of the periodic table (phosphorus in this embodiment) is added to form phosphorus-doped regions (phosphorus-added regions) 209 and 210. Note that the concentration of phosphorus to be added is preferably 5 × 10 ¹⁸ to 1 × 10 ²⁰ atoms / cm ³ (preferably 1 × 10 ^{19 to} 5 × 10 ¹⁹ atoms / cm ³ ). However, the concentration of phosphorus to be added varies depending on the temperature and time of the later gettering step and the area of the phosphorus-doped region, and is not limited to this concentration range. (Fig. 2 (C))

Next, the resist mask 206 is removed and 4
A heat treatment at 50 to 650 ° C. (preferably 500 to 600 ° C.) is applied for 2 to 16 hours to getter nickel remaining in the crystalline silicon film. In order to obtain the gettering action, a temperature of about ± 50 ° C. from the highest temperature of the heat history is required. However, since the heat treatment for crystallization is performed at 550 to 600 ° C., the heat treatment at 500 to 650 ° C. is sufficient. The gettering effect can be obtained.

In this embodiment, the heat treatment at 600 ° C. for 8 hours causes the nickel to turn into an arrow (see FIG. 2D).
, And gettered in the phosphorus-doped regions 209 and 210. Thus, the concentration of nickel remaining in the crystalline silicon films 211a and 211b is 2 × 10 ¹⁷ at.
oms / cm ³ or less (preferably 1 × 10 ¹⁶ atoms / cm ³ or less). However, this concentration is a result of measurement by mass secondary ion analysis (SIMS), and no concentration below this level has been confirmed at present because of the measurement limit. (Figure 2
(D))

After the nickel gettering step is completed, the crystalline silicon films 211a and 211b are patterned to form an active layer (semiconductor layer) 212 of a CMOS circuit and an active layer 213 of a pixel TFT. At this time, it is desirable to completely remove the phosphorus-added region that has captured nickel.

Then, an insulating film (not shown) is formed by a plasma CVD method or a sputtering method, and is patterned to form a gate insulating film 214. This gate insulating film functions as a gate insulating film of the pixel TFT, and has a thickness of 50 to 200 nm. In this embodiment, a silicon oxide film having a thickness of 80 nm is used. Further, another insulating film containing silicon may be used as a single layer or a stacked layer. (FIG. 3
(A))

At this time, the gate insulating film 214 is formed so as to remain on the pixel TFT, and is removed above the region where the CMOS circuit is to be formed. In this embodiment, only the CMOS circuit is described. However, actually, it is removed on a region which is a part of the drive circuit section (particularly, a circuit group required to operate at high speed). Therefore, it is desirable to leave an insulating film having the same thickness as the gate insulating film 214 only in a circuit such as a buffer circuit in which a high voltage is applied to the gate insulating film.

Next, at 800-1150 ° C. (preferably 9 ° C.)
A heat treatment step of 15 minutes to 8 hours (preferably 30 minutes to 2 hours) at a temperature of (00 to 1100 ° C.) is performed in an oxidizing atmosphere (thermal oxidation step). In this embodiment, 95
A heat treatment process is performed at 0 ° C. for 30 minutes.

The oxidizing atmosphere may be a dry oxygen atmosphere or a wet oxygen atmosphere, but a dry oxygen atmosphere is suitable for reducing crystal defects in the semiconductor layer.
Further, an atmosphere containing a halogen element in an oxygen atmosphere may be used. This thermal oxidation step in an atmosphere containing a halogen element is effective because an effect of removing nickel can be expected.

The portion where the gate insulating film 214 was not formed by performing the thermal oxidation step (the portion where the active layer was exposed) was 5 to 50 nm (preferably 10 to 30 nm).
nm) of a silicon oxide film (thermal oxide film) 215 is formed. In this embodiment, a silicon oxide film having a thickness of 30 nm is formed.
The silicon oxide film 215 functions as a gate insulating film of a CMOS circuit.

The oxidation reaction also proceeds at the interface between the gate insulating film 214 made of the silicon oxide film remaining in the pixel TFT and the semiconductor layer 213 thereunder. Therefore, finally, the thickness of the gate insulating film 216 of the pixel TFT is 50 to 2
00 nm (preferably 100 to 150 nm). In this embodiment, the thickness is 110 nm.

Although the silicon oxide film 215 is formed by the thermal oxidation method in this embodiment, a thin silicon oxide film may be formed by the low pressure thermal CVD method. In that case, the film formation temperature may be around 800 ° C., and silane and oxygen may be used as the film formation gas.

After the thermal oxidation process is completed, a conductive film having a laminated structure of a silicon film / tungsten silicide film is formed, and the NTF of the CMOS circuit is formed by patterning.
The T gate wiring 217 is formed. At this time, the conductive film 218 having the above structure is left in a region to be a PTFT and a pixel TFT of the CMOS circuit. (FIG. 3 (B))

In this structure, the silicon film located under the conductive film may have a thickness of about 20 to 70 nm. However, it is preferable to use a low pressure thermal CVD method for film formation. Because the gate insulating film of the CMOS circuit is very thin,
This is because the use of a sputtering method or a plasma CVD method may cause damage in an insulating film.

Of course, the material of the gate wiring that can be used in this embodiment is not limited to this, and any of the materials described in the “Embodiments of the invention” can be used. In this embodiment, the thickness of the conductive film 218 is set to 300 nm.

When the patterning of the conductive film is completed, an element belonging to Group 15 of the periodic table (phosphorus in this embodiment) is formed by using a resist mask (not shown) used for forming the gate wiring 217 and the conductive film 218 as a mask. And an impurity region (hereinafter, this region is referred to as an n region)
219a and 219b are formed.

In this specification, in the step of adding the impurity element imparting the conductivity type, an ion implantation method for performing mass separation may be used.
A plasma doping method without mass separation may be used.

At this time, 1 × is added to n regions 219a and 219b.
The set dose is adjusted so that phosphorus is contained at a concentration of 10 ¹⁸ to 1 × 10 ¹⁹ atoms / cm ³ (this concentration is represented by n). This concentration has important significance in the subsequent heat treatment step.

Next, the resist mask (not shown) is removed to remove the resist mask from 700 to 1000 ° C. (preferably 800 to 900 ° C.).
The heat treatment is performed within the temperature range described above to activate phosphorus. At the same time, phosphorus is diffused in the lateral direction to form the gate wiring 215.
, Low concentration impurity regions (hereinafter, referred to as n ⁻ regions) 220a and 220b are formed. This n ^- region 2
For 20a and 220b, 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm
Contains phosphorus at a concentration of ³ . (FIG. 3 (C))

The diffusion distance of the impurity can be controlled by the temperature and time of the heat treatment. Therefore, the length (width) of n ⁻ regions 218a and 218b can be freely controlled. In this embodiment, the overlap distance is 0.3 to 1 μm.
m (preferably 0.5 to 0.7 μm).

As described above, the above-described n regions 217a and 217a
The concentration of 7b depends on the activation conditions and n ^-Phosphorus needed for area
It depends on the concentration and the required length.

The heat treatment step oxidizes the active layer of the CMOS circuit again, and increases the thickness of the gate insulating film 213. Under the heat treatment conditions for forming the n ⁻ region as described above, the film thickness typically increases by 20 to 50 nm. However, an increase in the film thickness can be prevented by performing a heat treatment after providing a cap layer to prevent oxidation.

At the same time, the gate wiring 215 and the conductive film 2
16 is oxidized to form thermal oxide films 219 and 220 on the surface. When a laminated film of a silicon film and a metal silicide film is used as in this embodiment, silicon is preferentially oxidized on the surface, and thus a thermal oxide film to be formed is a silicon oxide film.

Next, the conductive film 216 is patterned to form gate wirings 221a and 221b of the pixel TFT. At this time, the PTFT of the CMOS circuit has the conductive film 222 left. (FIG. 3 (D))

Then, the gate wirings 215, 221a, 2
21b and the conductive film 222 as a mask.
A low concentration impurity region containing phosphorus at a concentration of 5 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ (hereinafter, referred to as an n ⁻ region) 223a to 223c are formed. At this time, phosphorus is also added to the above-mentioned n regions 217a and 217b, but the amount of increase does not matter because the concentration of added phosphorus is sufficiently lower than that of phosphorus contained in the n region.

In this embodiment, the n ⁻ region is formed. This is to increase the resistance value as much as possible to enhance the effect of suppressing off current. Accordingly, n in this adding step of phosphorus ^- it is possible to form a region ^- n instead of areas.

Further, this step may be performed separately for the drive circuit section having a thin gate insulating film and for the pixel section having a large thickness, or may be performed simultaneously. However, it is necessary to carefully control the concentration of the LDD region. Therefore, in the present embodiment, the concentration distribution (concentration profile) of the added phosphorus is set as shown in FIG. 6 by using the plasma doping method.

In FIG. 6, the gate insulating film 601 on the driving circuit portion and the gate insulating film 602 on the pixel portion are different in film thickness. Therefore, the concentration distribution of the added phosphorus in the depth direction is different.

In the present embodiment, the phosphorus addition conditions (acceleration voltage, etc.) are adjusted so that the drive circuit section has the concentration distribution indicated by 603 and the pixel section has the concentration distribution indicated by 604. . In this case, although the concentration distribution in the depth direction is different, the low concentration impurity regions 605 and 6 formed as a result are formed.
The phosphorus concentration of 06 is almost equal.

The process shown in FIG. 6 can be used in all the impurity addition processes described in this specification.

Next, the resist masks 224, 225a,
Form 225b and again belong to Group 15 of the periodic table
(In the present embodiment, phosphorus),¹⁹~
1 × 10 ^{twenty one}atoms / cm^ThreeImpurity with high concentration of phosphorus
Regions (hereinafter, this region is referred to as n + region) 226 to 23
0 is formed. (FIG. 4 (A))

According to this process, in the NTFT of the CMOS circuit, the source region 226, the drain region 227, and the LD
D region 231 and channel formation region 232 are defined. In addition, a source region 228, a drain region 229, LDD regions 233a and 233b, and channel forming regions 234a and 234b of the pixel TFT are defined.

The n + region 230 functions as a stopper region that prevents the movement of minority carriers (holes in this embodiment) that cause off current. However, the structure may be such that the LDD regions 233a and 233b are in contact with each other, unless necessary.

When the state shown in FIG. 4A is obtained, the CM
The conductive film 222 left over the region to be the PTFT of the OS circuit is patterned to form the gate wiring 235. Then, the resist mask 236a used at that time is used.
Using 236c as it is, a step of adding an element belonging to Group 13 of the periodic table (boron in this embodiment) was performed, and 5 × 10 ¹⁹
A high-concentration impurity region containing boron at a concentration of 1 × 10 ²¹ atoms / cm ³ (hereinafter, this region is referred to as a p + region) 237 to
239 are formed. (FIG. 4 (B))

By this step, a source region 237, a drain region 238 and a channel forming region 239 are defined in the PTFT of the CMOS circuit.

Thus, the formation of all the impurity regions is completed. Note that the order of the step of adding the impurities is not limited to the order of this embodiment, and they can be formed in any order. The order of addition of impurities can be determined as appropriate by a practitioner in consideration of problems in device performance and the like.

After the formation of the impurity regions is completed, the resist masks 236a to 236c are removed. Then, an insulating film (insulating film containing silicon) 240 having a thickness of 60 to 200 nm (preferably 100 to 150 nm) is formed as a lower layer of the first interlayer insulating film. Since this insulating film functions as a protective film for preventing oxidation of the gate wiring, a silicon oxynitride film is preferably used.

After forming the first interlayer insulating film (lower layer) 240 in this manner, the first interlayer insulating film (lower layer) 240 is formed at a temperature of 550 to 800 ° C.
A heat treatment process for 8 hours is performed. In this embodiment, heat treatment at 600 ° C. for 2 hours is performed in a nitrogen atmosphere. (FIG. 4
(C))

In this step, phosphorus or boron added to each impurity region is activated, and at the same time, damage to the gate insulating film and the active layer caused by the addition of the impurity is recovered.
Here, it is preferable to activate while suppressing diffusion of phosphorus and boron as much as possible. When a high temperature needs to be applied, it is necessary to sufficiently take into account the diffusion of phosphorus and boron of each TFT into the channel formation region.

Then, a hydrogenation treatment is further performed at 350 ° C. for one hour. This hydrogenation treatment is a step of exposing to hydrogen excited by heat or plasma.

When the state shown in FIG. 4C is obtained,
A first interlayer insulating film (upper layer) 241 is formed. As the first interlayer insulating film (upper layer) 241, an insulating film containing silicon (a silicon oxide film in this embodiment) may be used.

Next, contact holes are formed in the first interlayer insulating film (upper layer) 241 and the first interlayer insulating film (lower layer) 240, and an aluminum alloy film (an aluminum film to which 1% by weight of titanium is added) is formed using a titanium film. A conductive film (not shown) having a sandwiched three-layer structure is formed. Then, the conductive film is patterned to form the source wirings 242 and 243 and the drain wiring 244 of the CMOS circuit, and the source wiring 245 and the drain wiring 246 of the pixel TFT. In addition,
As for the pixel TFT, the source wiring and the drain wiring are alternately replaced.

After forming the source wiring and the drain wiring in this manner, a passivation film 247 having a thickness of 300 nm is formed.
A thick silicon nitride film is provided, and a hydrogenation treatment is performed thereon at 300 ° C. for one hour. This hydrogenation treatment is also a step of exposing to hydrogen excited by heat or plasma. In this step, the hydrogen released from the passivation film 247 and the hydrogen contained in the first interlayer insulating film (lower layer) 240 in a large amount by the preceding hydrogenation step are diffused downward (the upward direction is the passivation film). 247 becomes a blocking layer)
The active layer is terminated with hydrogen.

The passivation film 247 may be a silicon oxynitride film, a silicon oxide film,
Alternatively, a stacked film of these insulating films containing silicon can be used. In this embodiment, the passivation film 24 is used.
As a pretreatment for forming 7, it is effective to perform a plasma treatment using a gas containing hydrogen (typically, ammonia gas). Hydrogen activated (excited) by plasma by this pretreatment is confined by the passivation film 247. If hydrogenation is then performed, the hydrogenation efficiency is greatly improved.

Further, when nitrous oxide gas is added in addition to the gas containing hydrogen, the surface of the object to be processed is washed by the generated moisture, and it is possible to effectively prevent the contamination due to boron and the like contained in the air. it can.

When the hydrogenation is completed, the drain wiring 2
The passivation film 247 is removed on 46 to form an opening 248. Next, an acrylic film having a thickness of 1 μm is formed as the second interlayer insulating film 249. Other than acrylic, polyimide, polyamide, polyimide amide, BC
It is possible to use a resin film such as B (benzocyclobutene). Here, it is desirable to ensure sufficient flatness.

Then, a light-shielding film 250 made of an aluminum film is formed on the second interlayer insulating film 249 by a sputtering method. This light-shielding film includes: 1. An oxide can be easily formed on the surface. 2. The oxide has high dielectric constant and insulation resistance. Any material that satisfies the condition of having sufficient light-shielding properties may be used. In that sense, it can be said that an aluminum film or an aluminum alloy film is most suitable.

In this embodiment, a high-purity aluminum film (five nine) is used to form a light-shielding film 250 having a thickness of 135 nm.
To form At this time, the light shielding film 250 is formed so as to hide the source wiring and the gate wiring of the pixel TFT and the TFT main body, and is formed in a matrix in the pixel portion. However, a contact portion where a drain wiring and a pixel electrode are electrically connected later is opened without forming a light shielding film.

Further, in this embodiment, as a pre-process when forming the light-shielding film 250, the surface of the second interlayer insulating film 249 is subjected to a plasma process using CF ₄ gas. By this processing, the adhesion between the light-shielding film 250 made of an aluminum film and the second interlayer insulating film 249 made of a resin film is improved.

Next, anodizing treatment is performed on the light-shielding film 250 to form an anodic oxide 251 on the surface. (FIG. 5
(A))

In this embodiment, as a chemical conversion solution, a 15% ammonium tartrate solution and an ethylene glycol solution were used in two steps:
Use the solution mixed in 8. Then, the substrate was immersed in a solution maintained at 10 ° C. to form a formation current (60 μA in this embodiment).
/ Cm ² ) and anodic oxidation is performed. Formation voltage is 35V
Then, the voltage is switched to the constant voltage and maintained for 15 minutes to complete the anodic oxidation treatment.

Thus, the surface of the light shielding film 250 has a thickness of about 50 nm.
A thick anodic oxide (alumina film in this embodiment) is formed, and the final thickness of the light shielding film 250 is 150 nm.

Next, the second interlayer insulating film 249 is etched inside the gap of the light shielding film provided at the contact portion between the drain wiring and the pixel electrode, and the drain wiring 2
A contact hole 252 reaching 46 is formed. Then, a pixel electrode 253 made of a transparent conductive film (ITO film in this embodiment) is formed thereon with a thickness of 100 nm. (FIG. 5
(B))

At this time, a region 254 where the pixel electrode 253 overlaps the light shielding film 250 is a region functioning as a storage capacitor. In this case, the alumina film serving as a dielectric is as thin as about 50 nm and the relative dielectric constant is as high as 8 to 9, so that a large capacity can be obtained.

The portion where the contact hole 252 is formed is not shielded from light because it is a gap between the light shielding films 250. However, there is no problem since the light can be completely shielded by the drain wiring 246 thereunder. Therefore, the contact hole 252 is at least 0.1 mm from the end of the drain wiring 246.
It is desirable to form it inside with a margin of 5 μm (preferably 1 μm).

Thus, an active matrix substrate having a structure as shown in FIG. 5B is completed. After that, the AM-LCD as shown in FIG.
Can be produced.

The AM-LCD of the present invention has several structural features, and exhibits extremely high operation performance and reliability due to a synergistic effect thereof. One of the structural features is that a gate insulating film has a different thickness between a driver circuit portion and a pixel portion formed over the same substrate. Typically, a part of a driving TFT (a circuit requiring high-speed operation) used in a driving circuit portion has a gate insulating film thinner than a pixel TFT.

As a result, circuits requiring high-speed operation include:
A TFT having extremely high field-effect mobility can be provided, and the circuit requirements can be sufficiently satisfied. A highly reliable circuit can be formed in a circuit (a pixel portion, a buffer circuit, an analog switch circuit, or the like) requiring a high gate withstand voltage by arranging a TFT in which a withstand voltage characteristic is more important than an operation speed.

However, this does not mean that the thickness of the gate insulating film must not be the same in the driving circuit portion and the pixel portion. Since the operating speed and the gate withstand voltage have a trade-off relationship, the above-described structure is desirable in that case.

As another feature, a circuit that emphasizes the reduction of off-current, such as a pixel portion, employs a normal LDD structure, and a circuit, such as a driving circuit portion, that emphasizes hot carrier measures, An LDD region provided so as to overlap with a gate wiring like a so-called GOLD structure is arranged. With this, a TFT with sufficient reliability according to the circuit performance
Can be arranged.

As a further feature, when the storage capacitor is formed by the light shielding film and the pixel electrode, an oxide of the light shielding film is used as a dielectric. It is also characteristic that an aluminum film or a film containing aluminum as a main component is used as the light-shielding film. As a result, a large capacitance can be secured with a very small area, and the effective display area of the pixel can be improved (the aperture ratio can be improved).

According to the fabrication process of this embodiment, the final active layer (semiconductor layer) of the TFT is formed of a crystalline silicon film having a unique crystal structure having continuity in the crystal lattice. The features will be described below.

First, as a first feature, the crystalline silicon film formed in accordance with the manufacturing process of this embodiment has a plurality of needle-like or rod-like crystals (hereinafter abbreviated as rod-like crystals) when viewed microscopically.
Have a crystal structure arranged in a row. This is TEM
(Transmission electron microscopy) can be easily confirmed.

As a second feature, when electron beam diffraction is used, the surface of the crystalline silicon film (portion forming a channel) formed according to the manufacturing process of this embodiment has a slight shift in the crystal axis.配 向 1 as the main orientation plane
You can see the 10 ° plane. This means that when observing an electron beam diffraction photograph with a spot diameter of about 1.35 μm,
This is confirmed by the appearance of diffraction spots having a specific regularity on the 10 ° plane. It has also been confirmed that each spot has a distribution on concentric circles.

As a third feature, when the orientation ratio is calculated using an X-ray diffraction method (strictly, an X-ray diffraction method using the θ-2θ method), the orientation ratio of the {220} plane is found to be It has been confirmed that it is 0.7 or more (typically 0.85 or more). The method of calculating the orientation ratio is described in Japanese Patent Application Laid-Open No. 7-3213.
The technique described in Japanese Patent Publication No. 39 is used.

Further, as a fourth feature, the present applicant has proposed that the crystal grain boundary formed by contacting individual rod-shaped crystals is HR-TEM.
(High-resolution transmission electron microscopy) to confirm that the crystal lattice has continuity at the crystal grain boundaries. This can be easily confirmed from the fact that the observed lattice fringes are continuously connected at the crystal grain boundaries.

The continuity of the crystal lattice at the crystal grain boundaries is caused by the fact that the crystal grain boundaries are grain boundaries called “planar grain boundaries”. The definition of the planar grain boundary in this specification is `` Characterization of High-Efficiency Cast-Si
Solar Cell Wafers by MBICMeasurement; Ryuichi Shi
mokawa and Yutaka Hayashi, Japanese Journal of Appl
ied Physics vol.27, No.5, pp.751-758, 1988 ".

According to the above paper, the planar grain boundaries include twin grain boundaries, special stacking faults, special twist grain boundaries, and the like. This planar grain boundary is characterized by being electrically inactive. In other words, since it is a crystal grain boundary but does not function as a trap that hinders the movement of carriers, it can be considered that it does not substantially exist.

In particular, the crystal axis (the axis perpendicular to the crystal plane) is <11
In the case of the <0> axis, the {211} twin grain boundaries are also called corresponding grain boundaries of {3}. The Σ value is a parameter serving as a guideline indicating the degree of consistency of the corresponding grain boundaries, and it is known that the smaller the Σ value, the better the grain boundaries of consistency. For example, in a crystal grain boundary formed between two crystal grains, when the plane orientation of both crystals is {110}, θ = 70.5 ° where θ is an angle formed by lattice fringes corresponding to the {111} plane. It is known that a corresponding grain boundary of # 3 is obtained at the time of.

In a crystalline silicon film obtained by carrying out this embodiment, when a crystal grain boundary formed between two crystal grains having a crystal axis of <110> is observed by HR-TEM, it is found that adjacent crystal grains are formed. In many cases, each lattice fringe is continuous at an angle of about 70.5 °. Therefore, it can be inferred that the crystal grain boundary is a corresponding grain boundary of {3}, that is, a {211} twin grain boundary.

Such a crystal structure (accurately, a structure of a crystal grain boundary) indicates that two different crystal grains are bonded to each other with extremely high consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and it is very difficult to form a trap level due to a crystal defect or the like. Therefore, it can be considered that the semiconductor thin film having such a crystal structure has substantially no crystal grain boundary.

Further, it was confirmed by TEM observation that the defects existing in the crystal grains were almost completely eliminated by the heat treatment step at a high temperature of 700 to 1150 ° C. (corresponding to the thermal oxidation step or the gettering step in this embodiment). Has been confirmed. This is apparent from the fact that the number of defects is significantly reduced before and after this heat treatment step.

The difference in the number of defects was determined by electron spin resonance analysis (El
ectron Spin Resonance (ESR) appears as a difference in spin density. At present, the spin density of the crystalline silicon film manufactured according to the manufacturing process of this embodiment is at least
5 × 10 ¹⁷ spins / cm ³ or less (preferably 3 × 10 ¹⁷ spins / cm ³
Below). However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be lower.

As described above, since the crystalline silicon film obtained by carrying out this embodiment has substantially no inside of the crystal grains and no crystal grain boundaries, the single-crystal silicon film or the substantially single-crystal silicon Think of it as a membrane.

(Knowledge Regarding Electrical Characteristics of TFT) The TFT fabricated in this example (having the same structure as the CMOS circuit shown in FIG. 1) showed electrical characteristics comparable to those of MOSFET. The TFT prototyped by the present applicant (however, the thickness of the active layer is 35 n
m, and the thickness of the gate insulating film is 80 nm), the following data is obtained.

(1) The sub-threshold coefficient which is an index of the switching performance (the agility of switching on / off operation) is 80 to 150 mV / decade (typically 100 to 120 mV) for both the N-channel TFT and the P-channel TFT. / decade
) And small. (2) The field effect mobility (μ _FE ) which is an index of the operation speed of the TFT is 150 to 650 cm ² / Vs for the N-channel TFT.
(Typically 200-500cm ² / Vs), P-channel TFT
100-300 cm ² / Vs (typically 120-200 cm ² / Vs). (3) The threshold voltage (V
_th ) is as small as -0.5 to 1.5 V for an N-channel TFT and -1.5 to 0.5 V for a P-channel TFT.

As described above, it has been confirmed that extremely excellent switching characteristics and high-speed operation characteristics can be realized.

[Embodiment 2] In Embodiment 1, the light shielding film 2
50 may be maintained at a common potential or set in a floating state. However, there is no problem in the floating state, but when the voltage is lowered to the common potential, a connection terminal for lowering the light shielding film to the common potential is required. In this embodiment, the structure will be described with reference to FIG.

In FIG. 7A, reference numeral 701 denotes a common power supply line, which is a wiring formed simultaneously with a source wiring and a drain wiring. 702 is a second interlayer insulating film;
03 is a light shielding film, and 704 is an anodic oxide.

In this case, before forming the light shielding film 250 in the step of FIG. 5A, the second interlayer insulating film 249 (FIG.
A contact hole 705 (FIG. 7A) is formed with respect to 702 of FIG.
(Corresponding to 703 in FIG. 7A) may be formed.
This makes it possible to easily maintain the light shielding film 703 at the common potential.

FIG. 7B shows this state when viewed from above. FIG. 7A is a cross-sectional view of the top view of FIG. 7B taken along line AA ′. The reference numerals may be referred to FIG. Note that this example is one of the embodiments of Example 1, and thus the conditions of the manufacturing process and the like are referred to Example 1.

[Embodiment 3] This embodiment is another example of the second embodiment. FIG. 8 shows the structure of this embodiment. FIG. 8 (A)
In the figure, reference numeral 801 denotes a common power supply line, which is a wiring formed simultaneously with the source wiring and the drain wiring. 802 is a second interlayer insulating film, 803 is a light shielding film, 804
Is an anodic oxide, and 805 is a transparent conductive film formed simultaneously with the pixel electrode.

In this case, in the step of FIG.
When the contact hole 252 is formed in the interlayer insulating film 249, a part of the second interlayer insulating film 802 is removed at the connection terminal portion to expose the common power supply line 801 as shown in FIG. Then, at the same time as the formation of the pixel electrode 253, a transparent conductive film 805 is formed in the connection terminal portion.

At this time, the light shielding film 803 and the transparent conductive film 805
Between the anodic oxide 804 and the capacitor 80
6 are formed. However, considering that the AC drive is performed, the capacitor 806 can be considered to be substantially short-circuited, and the light-shielding film 803 and the common power supply line 801 can be considered to be electrically connected. .

FIG. 8B shows this state when viewed from above. FIG. 8A is a cross-sectional view of the top view of FIG. 8B taken along the line AA ′. The reference may be made to FIG. Note that this example is one of the embodiments of Example 1, and thus the conditions of the manufacturing process and the like are referred to Example 1.

[Embodiment 4] In FIG.
A liquid crystal 134 is provided between the substrate and the counter electrode 136 on the counter substrate side by a dielectric (strictly speaking, the alignment films 133 and 135 and the oxide 13).
1 (including 1). Therefore, when the capacitive coupling is large, the light shielding film 130 is kept at the common potential by the effect of the coupling.

That is, even if the light-shielding film 130 is not connected to another wiring, the light-shielding film 130 can be maintained at the common potential by capacitive coupling with the counter electrode. The present embodiment is an example in which the light-shielding film 130 is held at a common potential by such a method. Note that this example is one of the embodiments of Example 1, and thus the conditions of the manufacturing process and the like are referred to Example 1.

[Embodiment 5] In this embodiment, a specific structure of a TFT and a structure of a TFT will be described with reference to FIG.

In the AM-LCD, the minimum required operating voltage (power supply voltage) differs depending on the circuit. For example, in a pixel portion, an operation voltage of 14 to 20 V is obtained in consideration of a voltage applied to liquid crystal and a voltage for driving a pixel TFT. Therefore, a TFT that can withstand such a high voltage must be used.

For a shift resist circuit used for a source driver circuit or a gate driver circuit, an operation voltage of about 5 to 10 V is sufficient. There is an advantage that the lower the operating voltage is, the more compatible with the external signal and the more the power consumption can be suppressed. However, the above-mentioned high breakdown voltage type TFT is not suitable for a circuit requiring a high speed operation such as a shift register circuit because the operation speed is sacrificed instead of having a good breakdown voltage characteristic.

As described above, the circuit formed on the substrate is:
Depending on the purpose, there is a circuit for obtaining a TFT that emphasizes the withstand voltage characteristic and a circuit for obtaining a TFT that emphasizes the operation speed.

FIG. 9 specifically shows the configuration of this embodiment. FIG. 9A is a block diagram of the AM-LCD viewed from above. A pixel unit 901 includes a pixel TFT and a storage capacitor in each pixel, and functions as a display unit. 902a is a shift register circuit, 902b
Is a level shifter circuit, and 902c is a buffer circuit.
The circuit composed of these forms a gate drive circuit section as a whole.

In the AM-LCD shown in FIG. 9A, a gate drive circuit is provided so as to sandwich the pixel portion, and each shares the same gate wiring, that is, one of the gate drivers is defective. In this case, the redundancy can be provided such that a voltage can be applied to the gate wiring even if the occurrence of the error occurs.

Reference numeral 903a denotes a shift register circuit;
03b is a level shifter circuit, 903c is a buffer circuit, 9
03d is a sampling circuit, and a circuit composed of these forms a source drive circuit as a whole. A precharge circuit 90 is located on the opposite side of the pixel portion from the source drive circuit.
4 are provided.

In the AM-LCD having such a configuration, the shift register circuits 902a and 903a are circuits for demanding high-speed operation, and the operating voltage is as low as 3.3 to 10 V (typically 3.3 to 5 V). High breakdown voltage characteristics are not particularly required. Therefore, the thickness of the gate insulating film is preferably as thin as 5 to 50 nm (preferably, 10 to 30 nm).

FIG. 9B is a schematic diagram of a CMOS circuit to be mainly used for a circuit requiring a high-speed operation, such as a shift register circuit or a signal dividing circuit. In FIG. 9B, reference numeral 905 denotes a gate insulating film, which is designed to be as thin as 5 to 50 nm (preferably, 10 to 30 nm).

The length of the LDD region 906 is 0.1 to
1 μm (typically 0.3 to 0.5 μm) is preferred. Also, if the operating voltage is sufficiently low, such as 2-3V, L
It is also possible not to provide a DD region. Needless to say, the structure is such that hot carrier deterioration is prevented by completely overlapping the gate wiring.

Next, the CMOS circuit shown in FIG.
It is mainly suitable for the level shifter circuits 902b and 903b, the buffer circuits 902c and 903c, the sampling circuit 903d, and the precharge circuit 904. Since these circuits require a large current to flow, the operating voltage is as high as 14 to 16V. Especially on the gate driver side, sometimes 19V
In some cases, such an operating voltage is required. Therefore, a TFT having very good withstand voltage characteristics (high withstand voltage characteristics) is required.

At this time, in the CMOS circuit shown in FIG. 9C, the gate insulating film 907 has a thickness of 50 to 200.
nm (preferably 100 to 150 nm).
In a circuit requiring such a high gate withstand voltage, it is preferable to make the gate insulating film thicker than a TFT such as a shift register circuit.

The length of the LDD region 908 is 1 to 3 μm.
m (typically 1.5 to 2 μm) is preferred. Note that LD
The length of the portion of the D region overlapping with the gate wiring is 0.5 to
It may be 2 μm (preferably 1 to 1.5 μm). The remaining portion is an LDD region that does not overlap with the gate wiring. However, by arranging such a region, off-state current can be effectively suppressed. Note that since the CMOS circuit illustrated in FIG. 9C applies a high voltage similar to that of a pixel like a buffer circuit or the like, it is preferable that the length of the LDD region be equal to or close to that of the pixel.

Next, FIG. 9D is a schematic view of the pixel portion 901. The pixel TFT requires an operating voltage of 14 to 16 V because the voltage applied to the liquid crystal is also taken into account.
In addition, since the charge stored in the liquid crystal and the storage capacitor must be held for one frame period, the off-current must be as small as possible.

For this reason, in this embodiment, the NTF
The gate insulating film 909 has a double gate structure using T
Film thickness of 50 to 200 nm (preferably 100 to 150 n
m). This film thickness is equivalent to the CMO shown in FIG.
The film thickness may be the same as that of the S circuit, or may be different.

The length of each of the LDD regions 910a and 910b is preferably 2 to 4 μm (typically 2.5 to 3.5 μm). Note that in the pixel TFT illustrated in FIG. 9D, it is necessary to reduce the off-state current as much as possible.
The feature is that a and 910b do not overlap with the gate wiring.

As described above, even in the case of an AM-LCD, various circuits are provided on the same substrate, and the required operating voltage (power supply voltage) may differ depending on the circuit.
In this case, it is necessary to use differently, such as disposing TFTs having different gate insulating films as in the present invention.

It is effective to use the circuit shown in the first embodiment to realize the configuration of the present embodiment.

[Sixth Embodiment] In the first embodiment, in the step of selectively removing the gate insulating film, it is desirable that the removal in the region to be the driving TFT is performed as shown in FIG. In FIG. 10, 11 is an active layer, 12 is an end of a gate insulating film, and 13 and 14 are gate wirings. As shown in FIG. 10, it is desirable that a gate insulating film be left at an end of the active layer 11 in a portion 15 where the gate wiring goes over the active layer.

The edge of the active layer 11 undergoes a phenomenon called edge thinning when a thermal oxidation step is performed later. This is a phenomenon in which the oxidation reaction proceeds so as to sunk under the edge of the active layer, and the edge becomes thinner and simultaneously rises upward. For this reason, when the edge thinning phenomenon occurs, there is a problem that the gate wiring is easily broken when the gate wiring gets over.

However, if the gate insulating film is removed so as to have a structure as shown in FIG. 10, the edge thinning phenomenon can be prevented in the portion 15 over which the gate wiring runs. Therefore, a problem such as disconnection of the gate wiring can be prevented beforehand. It is effective to use the configuration of the present embodiment for the first embodiment.

[Embodiment 7] In this embodiment, a TFT is formed on a substrate by the manufacturing process shown in Embodiment 1 and an AM-
A case where an LCD is manufactured will be described.

After the state shown in FIG. 5B is obtained, an alignment film is formed on the pixel electrode 253 to a thickness of 80 nm. Next, a color filter, a transparent electrode (counter electrode), and an alignment film are formed on a glass substrate as a counter substrate, and a rubbing process is performed on each alignment film to form a sealing material (sealing material). Then, the substrate on which the TFT is formed and the counter substrate are bonded to each other. Then, the liquid crystal is held in the meantime. Since a well-known means may be used for this cell assembling step, a detailed description is omitted.

A spacer for maintaining the cell gap may be provided as needed. Therefore, when the cell gap can be maintained without the spacer as in the case of an AM-LCD having a diagonal of 1 inch or less, it is not necessary to particularly provide the cell gap.

Next, the AM-L manufactured as described above was used.
FIG. 11 shows the appearance of the CD. An active matrix substrate (refers to a substrate on which a TFT is formed) 21 has a pixel portion 2
2. Source drive circuit 23, gate drive circuit 24, signal processing circuit (signal division circuit, D / A converter circuit, gamma correction circuit, differential amplifier circuit, etc.) 25 are formed, and FPC (flexible printed circuit) 26 is attached. Have been. In addition, 27 is a counter substrate.

This embodiment can be freely combined with any of the first to sixth embodiments.

[Embodiment 8] In this embodiment, a case where another means is used for forming a crystalline silicon film in Embodiment 1 will be described.

Specifically, the technique described in Example 2 of JP-A-7-130652 is used for crystallization of an amorphous silicon film. According to the technique described in the publication, a catalyst element (typically, nickel) that promotes crystallization is selectively retained on the surface of an amorphous silicon film, and crystallization is performed using the portion as a seed for nucleus growth. Technology.

According to this technique, a specific directionality can be given to the crystal growth, so that a crystalline silicon film having extremely high crystallinity can be formed.

In addition, the mask insulating film provided for selectively holding the catalyst element can be used as it is as a mask of phosphorus added for gettering. By doing so, the number of steps can be reduced. This technique is described in detail in JP-A-10-247735 by the present applicant.

The structure of this embodiment can be freely combined with any of the structures of the first to seventh embodiments.

[Embodiment 9] Phosphorus was used to getter nickel (the catalyst element used to crystallize a silicon film) described in Embodiment 1, but in this embodiment, other elements were used. The case where nickel is gettered will be described.

First, according to the steps of the first embodiment, FIG.
(B) state is obtained. In FIG. 2B, reference numeral 204 denotes a crystalline silicon film. However, in this embodiment, the concentration of nickel used for crystallization is set as low as possible. Specifically, a layer containing 0.5 to 3 ppm by weight of nickel is formed on the amorphous silicon film, and a heat treatment for crystallization is performed.
The concentration of nickel contained in the crystalline silicon film thus formed is 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ (typically 5 × 10 ¹⁷ to 1 × 10 ¹⁸ atoms / cm ³ ). Become.

After the formation of the crystalline silicon film, heat treatment is performed in an oxidizing atmosphere containing a halogen element. The temperature is 800 to 1150 ° C (preferably 900 to 1000 ° C)
And the processing time is 10 minutes to 4 hours (preferably 30 minutes to
1 hour).

In the present embodiment, three to three atmospheres
In an atmosphere containing 10% by volume of hydrogen chloride, 9
Heat treatment is performed at 50 ° C. for 30 minutes.

In this step, nickel in the crystalline silicon film becomes volatile nickel chloride and is released into the processing atmosphere. That is, nickel can be removed by the gettering action of the halogen element. However, if the concentration of nickel existing in the crystalline silicon film is too high, there is a problem that oxidation proceeds abnormally at the nickel segregation portion. Therefore, it is necessary to minimize the concentration of nickel used in the crystallization stage.

The structure of this embodiment can be freely combined with any of the structures of Embodiments 1 to 8.

[Embodiment 10] In this embodiment, a case where the structures of the CMOS circuit and the pixel portion shown in Embodiment 1 are different will be described. Specifically, an example is shown in which the arrangement of the LDD regions is changed according to the specifications required by the circuit.

Since the basic structures of the CMOS circuit and the pixel portion have already been shown in FIG. 1, in this embodiment, only the necessary portions will be denoted by reference numerals. In addition, T of this embodiment
For the FT structure, basically, the manufacturing method of Embodiment 1 may be referred to.

First, the circuit shown in FIG.
In the OS circuit, the LDD region 31 of the NTFT is provided in contact with only the drain region 33 side of the channel formation region 32. Note that this structure can be realized by hiding the source region side with a resist mask.

Since high-speed operation is required for a CMOS circuit used in a drive circuit portion, it is necessary to eliminate as much as possible a resistance component that may cause a reduction in operation speed. However, LDD required to increase hot carrier resistance
Since the region works as a resistance component, the operation speed is sacrificed.

However, hot carrier injection occurs at the end of the channel formation region on the drain region side, and if there is an LDD region overlapping with the gate wiring at that portion, sufficient hot carrier measures can be taken. Therefore, the LD on the source region side end of the channel formation region
It is not necessary to provide a D region.

The structure shown in FIG. 12A cannot be applied to the case where an operation like a pixel TFT in which a source region and a drain region are exchanged is performed. In the case of a CMOS circuit, the source region and the drain region are usually fixed, so that a structure as shown in FIG. 12A can be realized.

Next, the circuit shown in FIG.
In an OS circuit, NTFT has a double gate structure, PT
This is an example in which the FT has a single gate structure. Such a structure is used for a driving circuit portion (typically, a buffer circuit or a sampling circuit) required to have a high withstand voltage.

In this case, the NTD LDD region 34a,
It is characterized in that 34b is provided only on the drain region 36 side (or on the side close to the drain region 36) of each of the channel forming regions 35a and 35b.

With such a structure, the resistance component due to the LDD region on the source region side is eliminated, and with the double gate structure, the electric field applied between the source and drain is dispersed and relaxed.

The structure of this embodiment can be freely combined with any of the structures of the first to ninth embodiments.

[Eleventh Embodiment] In the first embodiment, providing a light-shielding film under a TFT (specifically, under an active layer) as necessary is effective in suppressing a leak current due to photoexcitation. . In particular, it is effective to provide it below the pixel TFT for which the leakage current (or off current) needs to be suppressed as much as possible.

As the light shielding film, a metal film, a black resin film, or the like can be used. When a metal film is used, a storage capacitor is formed between the light shielding film and the active layer by using the metal film. It is also possible. In this case, since a structure in which two net storage capacitors are connected in parallel, a sufficient storage capacitor can be secured.

The structure of this embodiment can be freely combined with any of the structures of the first to tenth embodiments.

[Embodiment 12] In this embodiment, a technique for improving the adhesion between the light-shielding film and the underlying second interlayer insulating film (resin film) in the pixel portion shown in Embodiment 1 is described. provide. FIG. 13 is used for the description.

In this embodiment, after the second interlayer insulating film 41 made of an acrylic film is formed, 10 to 30 are formed by the sputtering method.
A silicon oxide film having a thickness of nm is formed, and a high-purity aluminum film is further formed continuously. This is collectively etched to form a light shielding film. In FIG. 13, reference numeral 42 denotes a silicon oxide film, and 43 denotes a high-purity aluminum film.

The silicon oxide film functions as a buffer layer for improving the adhesion between the second interlayer insulating film 41 made of an acrylic film and the light shielding film 43 made of a high-purity aluminum film.
By providing this silicon oxide film 42, good adhesion can be ensured even when the oxide 44 is formed by an anodic oxidation method or the like.

The structure of this embodiment is similar to those of the first to eleventh embodiments.
Any configuration can be freely combined.

[Embodiment 13] In this embodiment, an example in which the structure of the storage capacitor is different from that of FIG. 1 will be described. 14A and 14B are used for the description.

In FIG. 14A, the state of FIG. 5A is first obtained according to the steps of the first embodiment. Next, a third interlayer insulating film 51 made of a resin film (an acrylic film in this embodiment) is formed, and openings 52a and 52b are formed. This opening 52
The formation of a and 52b exposes the light-shielding film 250 (strictly speaking, the oxide 251 on the surface). At this time, a contact hole 53 is also formed at the same time.

Thereafter, a pixel electrode 54 made of an ITO film is formed. Thus, in the openings 52a and 52b, the light shielding film 25 is formed.
0, a storage capacitor is formed by the oxide 251 of the light-shielding film and the pixel electrode 54. With such a structure, the light shielding film 25
Since there is no need for the pixel electrode 54 to cross over the zero end, it is possible to prevent a problem such as a short circuit (short) at the end.

In FIG. 14B, first, the steps up to the step of FIG. 5A (but before the oxide 251 is formed) are performed according to the steps of the first embodiment. That is, the second interlayer insulating film 249
The process is performed until a light-shielding film 250 made of an aluminum film is formed thereon.

Next, a third interlayer insulating film 5 made of an acrylic film
5, and openings 56a and 56b are formed. At this time, a contact hole 57 is formed at the same time.

Then, an oxide 58 is formed on the exposed surface of the light-shielding film 250 in this state. In this embodiment, the oxide 5
8 is formed by an anodic oxidation method, but a thermal oxidation method or a plasma oxidation method may be used.

After the oxide 58 is formed on a part of the surface (upper surface) of the light shielding film 250, a pixel electrode 59 made of an ITO film is formed next. Thus, in the openings 56a and 56b, a storage capacitor is formed by the light-shielding film 250, the oxide 58 of the light-shielding film, and the pixel electrode 59. Even in such a structure, short-circuiting (short-circuiting) of the pixel electrode at the edge of the light-shielding film can be prevented as in FIG.

The structure of this embodiment is similar to that of the first to twelfth embodiments.
Any configuration can be freely combined.

[Embodiment 14] In this embodiment, the structure of a pixel portion formed by using the present invention will be described with reference to FIG. Since the basic cross-sectional structure has already been described with reference to FIGS. 1 to 5, here, the description will be given focusing on the positional relationship between the light-shielding film and the pixel electrode (position where the storage capacitor is formed).

First, the state shown in FIG. 15A corresponds to the state shown in FIG.
Are completed. 61 is an active layer,
62 is a gate wiring, 63 is a source wiring, 64 is a contact part between the active layer and the source wiring, 65 is a drain wiring (drain electrode), and 66 is a contact part between the active layer and the drain wiring.

Next, the state shown in FIG. 15B is the same as that shown in FIG.
Are completed. This state shows a state where the light-shielding film 67 and the pixel electrode 68 are overlapped with each other in FIG. Note that the pixel electrode 68 is partially represented by a dotted line in order to clarify the positional relationship with the underlying light-shielding film.

As shown in FIG. 15B, the pixel electrode 68
Are formed so as to overlap with the light shielding film 67 at the outer peripheral portion of the image display area 69. The region 70 where the pixel electrode 68 and the light-shielding film 67 overlap functions as a storage capacitor.

Reference numeral 71 denotes a contact portion between the drain wiring 65 and the pixel electrode 68. Although the light shielding film 67 cannot be provided in the contact portion 71, the drain wiring 65
In this case, the light is completely shielded, so that light does not hit the TFT.

The advantage of the structure of this embodiment is that the aperture ratio of the pixel can be increased because it is not necessary to separately form a wiring for forming a capacitor. The storage capacitor 70 is the source line 6
3 and the gate wiring 62, so that it does not substantially reduce the aperture ratio. Therefore, the image display area 69 can be maximized, and a bright image can be obtained.

The structure of this embodiment is similar to those of the first to thirteenth embodiments.
Any configuration can be freely combined.

[Embodiment 15] In this embodiment, an example in which a crystalline silicon film is formed by means different from that in Embodiment 1 will be described.

In Example 1, a catalyst element (nickel) was used for crystallization of an amorphous semiconductor film (specifically, an amorphous silicon film). In this example, thermal crystallization was performed without using a catalyst element. The case in which it is performed will be described.

In the case of this embodiment, after forming the amorphous silicon film, a heat treatment is performed at a temperature of 580 to 640 ° C. (typically 600 ° C.) for 12 to 30 hours (typically 16 to 24 hours). To obtain a crystalline silicon film. Therefore,
The gettering step as shown in the first embodiment can be omitted.

If the structure of the present invention can be realized as described above, it is easy to combine a process using a crystalline silicon film called so-called high-temperature polysilicon with the present invention.

The structure of this embodiment is similar to those of the first to seventh and ninth embodiments.
To 14 can be freely combined.

[Embodiment 16] In this embodiment, an example in which the first interlayer insulating film is formed by a method different from that of Embodiment 1 will be described. FIG. 16 is used for the description.

First, according to the manufacturing process of the first embodiment, FIG.
The steps up to the activation step shown in FIG. In this embodiment, the silicon oxynitride film 240 has a thickness of 70 nm.
Silicon oxynitride film (here, silicon oxynitride film (A) 16)
01). After the activation step, a silicon oxynitride film (B) 1602 having a thickness of 600 nm to 1 μm (800 nm in this embodiment) is formed thereon. Further, a resist mask 1603 is formed thereon. (FIG. 16
(A))

Note that the silicon oxynitride film (A) 1601 and the silicon oxynitride film (B) 1602 have different composition ratios of nitrogen, oxygen, hydrogen, and silicon. The silicon oxynitride film (A) 1601 contains 7% of nitrogen, 59% of oxygen, 2% of hydrogen, and 32% of silicon.
Is 33% nitrogen, 15% oxygen, 23% hydrogen, and 29% silicon. Of course, it is not limited to this composition ratio.

[0215] Further, since the resist mask 1603 is thick, unevenness of the surface of the silicon oxynitride film (B) 1602 can be completely flattened.

Next, a resist mask 160 is formed by dry etching using a mixed gas of carbon tetrafluoride and oxygen.
3 and the silicon oxynitride film (B) 1602 are etched. In the case of this embodiment, in dry etching using a mixed gas of carbon tetrafluoride and oxygen, the etching rates of the silicon oxynitride film (B) 1602 and the resist mask 1603 are substantially equal.

With this etching step, the resist mask 1603 is completely removed as shown in FIG.
Part of the silicon oxynitride film (B) 1602 (from the surface to a depth of 300 nm in this embodiment) is etched. As a result, the flatness of the surface of the resist mask 1603 is reflected on the flatness of the surface of the silicon oxynitride film (B) etched as it is.

Thus, a first interlayer insulating film 1604 having extremely high flatness is obtained. In the case of the present embodiment, the first interlayer insulating film 1
The film thickness of 604 is 500 nm. Subsequent steps may refer to the manufacturing steps in Embodiment 1.

The structure of this embodiment is similar to that of the first to fifteenth embodiments.
Any embodiment can be freely combined.

[Embodiment 17] Various known liquid crystal materials can be used for the AM-LCD manufactured according to the present invention. Such materials include TN liquid crystal, PDL
C (polymer dispersed liquid crystal), FLC (ferroelectric liquid crystal),
AFLC (Anti-static liquid crystal), or FLC and AFLC
And mixtures thereof.

For example, “H. Furue et al .; Charakteristi
cs and Drivng Scheme of Polymer-Stabilized Monosta
ble FLCD Exhibiting Fast Response Time and High Co
ntrast Ratio with Gray-Scale Capability, SID, 199
8 "," T. Yoshida et al .; A Full-Color Thresholdless "
Antiferroelectric LCD Exhibiting Wide Viewing Ang
le with Fast Response Time, 841, SID97DIGEST, 199
7 ", or the materials disclosed in US Pat. No. 5,594,569.

In particular, a thresholdless antiferroelectric liquid crystal (Th
When using a resholdless antiferroelectric LCD, the operating voltage of the liquid crystal is about ± 2.5V, so the
Only about 8V is required. That is, the driving circuit section and the pixel section can be operated at the same power supply voltage, and the power consumption of the entire AM-LCD can be reduced.

The ferroelectric liquid crystal and the antiferroelectric liquid crystal are T
There is an advantage that the response speed is faster than that of the N liquid crystal. This advantage cannot be exploited by the conventional TFT, but when a TFT having a crystal structure as described in Embodiment 1 is used,
Since a TFT with an extremely fast operation speed is realized, it is possible to realize an AM-LCD with a high image response speed that makes full use of the response speed of ferroelectric liquid crystals and antiferroelectric liquid crystals. .

It is needless to say that it is effective to use the AM-LCD of this embodiment as a display of an electric appliance such as a personal computer.

Further, the structure of this embodiment is similar to those of Embodiments 1 to 16
Any configuration can be freely combined.

[Embodiment 18] The present invention relates to a conventional MOSF
It is also possible to form an interlayer insulating film on the ET and use it when forming a TFT thereon. That is, it is also possible to realize a semiconductor device having a three-dimensional structure in which a reflective AM-LCD is formed on a semiconductor circuit.

The semiconductor circuit is SIMOX, Sm
art-Cut (registered trademark of SOITEC), ELTRAN
(A registered trademark of Canon Inc.) may be formed on an SOI substrate.

In implementing this embodiment, any of the configurations of Embodiments 1 to 17 may be combined.

[Embodiment 19] The present invention can also be applied to an active matrix type EL (electroluminescence) display (also referred to as an EL display device). An example is shown in FIG.

FIG. 17 is a circuit diagram of an active matrix EL display. Reference numeral 81 denotes a display area, around which an X-direction (gate side) drive circuit 82, Y
A direction (source side) drive circuit 83 is provided. Each pixel of the display area 81 is provided with a switching TFT 8.
4, a capacitor 85, a current control TFT 86, and an EL element 87. The switching TFT 84 includes an X-direction signal line (gate signal line) 88a (or 88b) and a Y-direction signal line (source signal line) 89a (or 89b). 89c) is connected. The current control TFT 86 includes a power supply line 90.
a and 90b are connected.

In the active matrix type EL display of this embodiment, the gate insulating films of the TFTs used in the X-direction driving circuit 82 and the Y-direction driving circuit 83 are thinner than the gate insulating films of the switching TFT 84 and the current control TFT 86. Has become. Further, the capacitor 85 is formed with the storage capacitor of the present invention.

It should be noted that any of the structures of the first to sixteenth and eighteenth embodiments may be combined with the active matrix EL display of the present embodiment.

[Embodiment 20] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described. Note that FIG. 18A is a top view of the EL display device of the present invention, and FIG. 18B is a cross-sectional view thereof.

In FIG. 18A, reference numeral 4001 denotes a substrate;
4002 is a pixel portion, 4003 is a source side driver circuit, 40
Reference numeral 04 denotes a gate-side drive circuit. Each drive circuit reaches an FPC (flexible print circuit) 4006 via a wiring 4005 and is connected to an external device.

At this time, a first sealant 4101, a cover 4102, a filler 4103, and a second sealant 4104 are provided so as to surround the pixel portion 4002, the source side drive circuit 4003, and the gate side drive circuit 4004.

FIG. 18 (B) shows FIG.
The driving TFTs included in the source-side driving circuit 4003 on the substrate 4001 (however,
Here, an n-channel TFT and a p-channel TFT are illustrated. ) 4201 and a current controlling TFT (TF controlling the current to the EL element) included in the pixel portion 4002.
T) 4202 is formed.

In the present embodiment, a TFT having the same structure as that of the drive circuit portion of FIG. 1 is used for the drive TFT 4201, and a TF having the same structure as that of the pixel portion of FIG.
T is used. The pixel portion 4002 has a storage capacitor (FIG. 17) connected to the gate of the current controlling TFT 4202.
Is provided, and the storage capacity (not shown) includes the storage capacity 2 shown in FIG.
A storage capacitor having the same structure as 54 is used.

Driving TFT 4201 and Pixel TFT 420
An interlayer insulating film (flattening film) 43 made of a resin material is formed on
01 is formed thereon, and a pixel electrode (anode) 4302 electrically connected to the drain of the pixel TFT 4202 is formed thereon. As the pixel electrode 4302, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used.

[0239] An insulating film 4303 is formed on the pixel electrode 4302, and the insulating film 4303 is formed on the pixel electrode 430.
2, an opening is formed. In this opening, an EL (electroluminescence) layer 4304 is formed on the pixel electrode 4302. For the EL layer 4304, a known organic EL material or inorganic EL material can be used. As the organic EL material, there are a low-molecular (monomer) material and a high-molecular (polymer) material, and either may be used.

As a method for forming the EL layer 4304, a known technique may be used. The EL layer may have a stacked structure or a single-layer structure by freely combining a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, or an electron injection layer.

On the EL layer 4304, a cathode 4305 made of a light-shielding conductive film (typically, a conductive film containing aluminum, copper, or silver as a main component or a laminated film of these and another conductive film) is provided. It is formed. In addition, the cathode 4305
It is desirable that moisture and oxygen existing at the interface between the EL layer and the EL layer 4304 be eliminated as much as possible. Therefore, the two layers are continuously formed in a vacuum or the EL layer 4304 is formed in a nitrogen or rare gas atmosphere, and the cathode 430 is not exposed to oxygen or moisture.
5 is required. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

The cathode 4305 is electrically connected to the wiring 4005 in a region 4306. A wiring 4005 is a wiring for applying a predetermined voltage to the cathode 4305, and the FPC 4006 through the conductive material 4307.
Is electrically connected to

As described above, the pixel electrode (anode) 43
02, an EL element including the EL layer 4304 and the cathode 4305 is formed. This EL element has a first sealing material 410
Are surrounded by a cover material 4102 bonded to the substrate 4001 by the first and first seal materials 4101,
3 enclosed.

As the cover member 4102, a glass plate, a metal plate (typically, a stainless steel plate), a ceramic plate, F
RP (Fiberglass-Reinforced)
Plastics) plate, PVF (polyvinyl fluoride) film, mylar film, polyester film or acrylic film can be used. Further, a sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.

However, when the direction of light emission from the EL element is directed toward the cover material, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.

As the filler 4103, an ultraviolet curable resin or a thermosetting resin can be used. Acetate) can be used. If a hygroscopic substance (preferably barium oxide) is provided inside the filler 4103, deterioration of the EL element can be suppressed.

[0247] A spacer may be contained in the filler 4103. At this time, if the spacer is made of barium oxide, the spacer itself can have hygroscopicity. In the case where a spacer is provided, it is also effective to provide a resin film on the anode 4305 as a buffer layer for relaxing pressure from the spacer.

The wiring 4005 is formed of a conductive material 4305.
Is electrically connected to the FPC 4006 via the. Wiring 4
005 is a signal transmitted to the pixel portion 4002, the source side driver circuit 4003, and the gate side driver circuit 4004,
006 to be electrically connected to an external device by the FPC 4006.

Further, in this embodiment, the first sealing material 4101
A second sealing material 4104 is provided so as to cover the exposed part of the FPC 4006 and a part of the FPC 4006, and the EL element is completely shut off from the outside air. Thus, an EL display device having the cross-sectional structure of FIG. In addition, E of this embodiment
The L display device may be manufactured by combining any of the configurations of Examples 1 to 16 and 18.

[Embodiment 21] In this embodiment, the embodiment 20 will be described.
FIGS. 19A to 19C show an example of a pixel structure that can be used for the pixel portion of the EL display device shown in FIGS. In this embodiment, reference numeral 4401 denotes a switching TFT 440.
Reference numeral 4403 denotes a switching TFT 443.
02, a gate wiring 4404, a current controlling TFT 44,
05 is a capacitor, 4406 and 4408 are current supply lines,
Reference numeral 4407 denotes an EL element.

FIG. 19A shows an example in which the current supply line 4406 is shared between two pixels. That is, the feature is that two pixels are formed so as to be line-symmetric with respect to the current supply line 4406. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 19B shows the current supply line 440.
8 is provided in parallel with the gate wiring 4403. Note that although FIG. 19B illustrates a structure in which the current supply line 4408 and the gate wiring 4403 are provided so as not to overlap with each other, if the wiring is formed in a different layer,
They can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 4408 and the gate wiring 4403 can share an occupied area, the pixel portion can have higher definition.

In FIG. 19C, a current supply line 4408 is provided in parallel with the gate wiring 4403 similarly to the structure of FIG. 19B, and two pixels are connected to the current supply line 4408.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 4408 so as to overlap with one of the gate wirings 4403. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

[Embodiment 22] The electro-optical device and the semiconductor circuit of the present invention can be used as a display portion or a signal processing circuit of an electric appliance. Such appliances include video cameras, digital cameras, projectors, projection TVs, goggle-type displays (head-mounted displays), navigation systems, sound reproducers, notebook personal computers, game machines,
A portable information terminal (a mobile computer, a mobile phone, a portable game machine, an electronic book, or the like), an image reproducing device provided with a recording medium, and the like are included. Specific examples of these electric appliances are shown in FIGS.

FIG. 20A shows a mobile phone,
01, audio output unit 2002, audio input unit 2003, display unit 2004, operation switch 2005, antenna 2006
It consists of. The electro-optical device according to the present invention includes the display unit 200.
Fourth, the semiconductor circuit of the present invention can be used for the audio output unit 2002, the audio input unit 2003, the CPU, the memory, and the like.

FIG. 20B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6. The electro-optical device according to the present invention has a display unit 21.
02, the semiconductor circuit of the present invention can be used for the audio input unit 2103, the CPU, the memory, or the like.

FIG. 20C shows a mobile computer (mobile computer), which comprises a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, and a display section 2205. The electro-optical device of the present invention can be used for the display portion 2205, and the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.

FIG. 20D shows a goggle type display having a main body 2301, a display portion 2302, and an arm portion 230.
3 The electro-optical device according to the present invention has a display unit 23.
02, the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.

FIG. 20E shows a rear projector (projection TV).
2, liquid crystal display device 2403, polarizing beam splitter 24
04, reflectors 2405, 2406, screen 2
407. The present invention can be used for the liquid crystal display device 2403, and the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.

FIG. 20F shows a front projector, which includes a main body 2501, a light source 2502, and a liquid crystal display device 25.
03, an optical system 2504, and a screen 2505. The present invention can be used for the liquid crystal display device 2502, and the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.

FIG. 21A shows a personal computer, which includes a main body 2601, a video input section 2602, and a display section 26.
03, a keyboard 2604, and the like. The electro-optical device of the present invention is provided in the display unit 2603, and the semiconductor circuit of the present invention is provided in C
It can be used for PUs and memories.

FIG. 21B shows an electronic game machine (game machine), which includes a main body 2701, a recording medium 2702, a display portion 2703, and a controller 2704. The audio and video output from the electronic game machine are reproduced on a display including the housing 2705 and the display portion 2706. As communication means between the controller 2704 and the main body 2701 or communication means between the electronic game apparatus and the display, wired communication, wireless communication, or optical communication can be used. In this embodiment, infrared rays are transmitted to the sensor units 2707 and 2708.
It is configured to detect by. The electro-optical device of the present invention can be used for the display portions 2703 and 2706, and the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.

FIG. 21C shows a player (image reproducing apparatus) using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium).
A speaker unit 2803, a recording medium 2804, and operation switches 2805 are included. This image reproducing apparatus uses a DVD (Digital Versatile D) as a recording medium.
isc), music, movies, games, and the Internet using CDs and the like. The electro-optical device of the present invention can be used for the display portion 2802, a CPU, a memory, and the like.

FIG. 21D shows a digital camera, which includes a main body 2901, a display portion 2902, an eyepiece portion 2903, operation switches 2904, and an image receiving portion (not shown). The electro-optical device of the present invention can be used for the display portion 2902, the CPU, the memory, and the like.

FIG. 22 shows a detailed description of an optical engine which can be used for the rear projector shown in FIG. 20E and the front projector shown in FIG. 20F. FIG. 22A shows an optical engine, and FIG.
2B is a light source optical system built in the optical engine.

The optical engine shown in FIG. 22A has a light source optical system 3001, mirrors 3002, 3005 to 300
7, including dichroic mirrors 3003 and 3004, optical lenses 3008a to 3008c, prism 3011, liquid crystal display device 3010, and projection optical system 3012. The projection optical system 3012 is an optical system including a projection lens. In this embodiment, an example of a three-panel type using three liquid crystal display devices 3010 is shown, but a single-panel type may be used. FIG.
In the optical path indicated by the arrow in (A), an optical lens,
A film having a polarizing function, a film for adjusting a phase difference, an IR film, or the like may be provided.

As shown in FIG. 22B, the light source optical system 3001 includes light sources 3013 and 3014, a combining prism 3015, collimator lenses 3016 and 3020, lens arrays 3017 and 3018, and a polarization conversion element 3019.
including. Note that the light source optical system shown in FIG. 22B uses two light sources, but may use one light source or three or more light sources. Also, somewhere in the optical path of the light source optical system, an optical lens,
A film having a polarizing function, a film for adjusting a phase difference, an IR film, or the like may be provided.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electric appliances in all fields. Further, the electric appliance of the present embodiment can be realized by using a configuration composed of any combination of Embodiments 1 to 21.

[0269]

According to the present invention, on the same substrate,
TFTs having gate insulating films with different thicknesses can be formed. Therefore, in a semiconductor device including an electronic device represented by an AM-LCD and an electric appliance having such an electronic device as a display portion (display display),
A circuit having an appropriate performance can be arranged according to a specification required by the circuit, and the performance and reliability of the semiconductor device can be greatly improved.

Further, in a pixel portion of an electronic device represented by an AM-LCD, a storage capacitor having a small area and a large capacity can be formed. Therefore, even in an electronic device having a display unit having a diagonal width of 1 inch or less, a sufficient storage capacity can be secured without reducing the aperture ratio.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross-sectional structure of an AM-LCD.

FIG. 2 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 3 is a view showing a manufacturing process of an AM-LCD.

FIG. 4 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 5 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 6 is a diagram showing a relationship between concentration distributions when an impurity element is added.

FIG. 7 is a diagram showing a structure of a common potential drop terminal portion.

FIG. 8 is a diagram showing a structure of a common potential drop terminal portion.

FIG. 9 is a diagram showing a block configuration and a circuit arrangement of an AM-LCD.

FIG. 10 is a diagram showing a structure of a driving TFT (CMOS circuit).

FIG. 11 is a diagram showing an appearance of an AM-LCD.

FIG. 12 illustrates a cross-sectional structure of a CMOS circuit.

FIG. 13 illustrates a cross-sectional structure of a pixel portion.

FIG. 14 illustrates a cross-sectional structure of a pixel portion.

FIG. 15 illustrates a top structure of a pixel portion.

FIG. 16 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 17 is a diagram showing a circuit configuration of an active matrix EL display.

FIG. 18 illustrates a top structure and a cross-sectional structure of an EL display device.

FIG. 19 illustrates a structure of a pixel portion of an EL display device.

FIG. 20 illustrates an example of an electric appliance.

FIG. 21 illustrates an example of an electric appliance.

FIG. 22 is a diagram showing a structure of an optical engine.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Mitsuaki Nori 398 Hase, Hase, Atsugi-shi, Kanagawa Prefecture Inside Semiconductor Semiconductor Laboratory (72) Inventor Satoshi Murakami 398 Hase, Atsugi-shi, Kanagawa Inside Semiconductor Energy Laboratory ( 72) Inventor Hideto Onuma 398 Hase, Hase, Atsugi-shi, Kanagawa Prefecture (72) Inventor Etsuko Fujimoto 398 Hase, Hase, Atsugi-shi, Kanagawa Inside, Semi-Conductor Energy Research Institute (72) Inventor, Hideto Kitakaku 398 Hase, Atsugi City, Kanagawa Pref.

Claims (11)

[Claims] 1. A semiconductor device including a pixel portion and a drive circuit portion on the same substrate, wherein an LDD region of a drive TFT forming the drive circuit portion is
The driving TFT with the gate insulating film of the driving TFT interposed therebetween;
The LDD region of the pixel TFT forming the pixel portion is disposed so as not to overlap with the gate wiring of the pixel TFT with a gate insulating film of the pixel TFT interposed therebetween. Wherein the storage capacitor is formed of a light-shielding film provided above the pixel TFT, an oxide of the light-shielding film, and a pixel electrode. 2. A semiconductor device including a pixel portion and a drive circuit portion on the same substrate, wherein an LDD region of a drive TFT forming the drive circuit portion is
The driving TFT with the gate insulating film of the driving TFT interposed therebetween;
The LDD region of the pixel TFT forming the pixel portion is disposed so as not to overlap with the gate wiring of the pixel TFT with a gate insulating film of the pixel TFT interposed therebetween. A storage capacitor formed of a light-shielding film provided on a resin film, an oxide of the light-shielding film, and a pixel electrode. 3. The semiconductor device according to claim 1, wherein a gate insulating film of the driving TFT is thinner than a gate insulating film of the pixel TFT. 4. The semiconductor device according to claim 1, wherein the light-shielding film is an aluminum film or a film containing aluminum as a main component. 5. The semiconductor device according to claim 1, wherein the oxide is an alumina film. 6. The semiconductor device according to claim 1, wherein the pixel electrode is an anode or a cathode of an EL element. 7. An electric appliance using the semiconductor device according to claim 1 for a display portion. 8. A method for manufacturing a semiconductor device including a pixel portion and a drive circuit portion on the same substrate, wherein a channel formation region, a source region, a drain region and the drain region are formed in an active layer of an NTFT forming the drive circuit portion. Forming an LDD region sandwiched between the TFT and a channel forming region; forming a channel forming region, a source region and a drain region in an active layer of a PTFT forming the driving circuit portion; and forming the pixel portion. Forming a channel forming region, a source region, a drain region and an LDD region sandwiched between the drain region and the channel forming region in an active layer of the pixel TFT to be formed. Forming an LDD region so as to overlap a gate wiring of an NTFT forming the driving circuit portion with a gate insulating film interposed therebetween; An LDD region of the FT is formed so as not to overlap a gate wiring of the pixel TFT with a gate insulating film interposed therebetween, and a light-shielding film provided above the pixel TFT, an oxide of the light-shielding film and a pixel electrode are used to form the pixel. A method for manufacturing a semiconductor device, comprising forming a storage capacitor in a portion. 9. A method for manufacturing a semiconductor device including a pixel portion and a driving circuit portion on the same substrate, wherein: a first step of forming an active layer on the substrate; and a step of forming a gate insulating film on the active layer. Two steps; a third step of forming a conductive film on the gate insulating film; a fourth step of patterning the conductive film to form a gate wiring of NTFT forming the drive circuit portion; A fifth step of adding an element belonging to Group 15 of the periodic table to the active layer of the NTFT forming the drive circuit unit using the gate wiring of the NTFT forming the drive circuit as a mask to form an n region, and heat treating the n region. shape and sixth step of forming a region, a gate wiring of the pixel TFT that forms the pixel portion by patterning the conductive film ^- is diffused, n under the gate wiring NTFT forming the driver circuit portion by To the seventh step, a gate wiring of the pixel TFT is added an element belonging to group 15 of the periodic table as a mask in the active layer of the pixel TFT, n
^And an ninth step of adding an element belonging to Group 15 of the periodic table to the active layer of the NTFT and the active layer of the pixel TFT forming the drive circuit unit, and forming an n ⁺ region. A tenth step of patterning the conductive film to form a gate wiring of a PTFT forming the drive circuit section; and forming a PTFT forming the drive circuit section on an active layer of the PTFT forming the drive circuit section. An eleventh step of forming ap ⁺ region by adding an element belonging to Group 13 of the periodic table using the gate wiring as a mask, and an NTFT and a PTFT forming the driving circuit section and a pixel TFT forming the pixel section. A twelfth step of forming an interlayer insulating film made of a resin film, a thirteenth step of forming a light shielding film on the interlayer insulating film, and a fourteenth step of forming an oxide of the light shielding film on the surface of the light shielding film
And a fifteenth step of forming a pixel electrode in contact with the oxide of the light-shielding film and overlapping the light-shielding film. 10. The method for manufacturing a semiconductor device according to claim 8, wherein the light-shielding film is an aluminum film or a film containing aluminum as a main component. 11. A semiconductor device according to claim 8, wherein said oxide is an alumina film, and said alumina film is formed by an anodic oxidation method, a plasma oxidation method, or a thermal oxidation method. Method of manufacturing.