JP4372939B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter referred to as TFTs). For example, the present invention relates to an electronic device typified by a liquid crystal display and a configuration of an electric appliance using such an electronic device as a display unit. Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electronic device, a semiconductor circuit, and an electric appliance are all semiconductor devices.
[0002]
[Prior art]
Since a thin film transistor (TFT) can be formed on a transparent substrate, application development to an active matrix liquid crystal display (hereinafter referred to as AM-LCD) has been actively promoted. Since a TFT using a crystalline semiconductor film (typically a polysilicon film) has high mobility, a high-definition image display can be realized by integrating functional circuits on the same substrate. Yes.
[0003]
The AM-LCD basically has a pixel portion for displaying an image, a gate drive circuit for driving TFTs of each pixel arranged in the pixel portion, and a source drive circuit (also referred to as a data drive circuit) for sending an image signal to each TFT. Are formed on the same substrate. In this specification, the gate driving circuit and the source driving circuit are collectively referred to as a driving circuit unit.
[0004]
In recent years, a system on panel has been proposed in which signal processing circuits such as a signal dividing circuit and a γ correction circuit are provided on the same substrate in addition to the pixel portion and the drive circuit portion.
[0005]
However, since the performance required by the circuit differs between the pixel portion and the drive circuit portion, it is difficult to satisfy all circuit specifications with TFTs having the same structure. That is, a TFT structure that satisfies both a drive circuit unit such as a shift register circuit that emphasizes high-speed operation and a TFT that constitutes a pixel unit that emphasizes high breakdown voltage characteristics (hereinafter referred to as a pixel TFT) has not been established. Currently.
[0006]
Therefore, the present applicant has applied for a configuration in which the thickness of the gate insulating film is made different between the TFT forming the drive circuit portion (hereinafter referred to as drive TFT) and the pixel TFT (see Japanese Patent Laid-Open No. 10-056184). . Specifically, the gate insulating film of the driving TFT is made thinner than the gate insulating film of the pixel TFT.
[0007]
[Problems to be solved by the invention]
Recently, in order to realize a high-definition screen of XGA (1024 × 768 pixels) on a 0.9 inch diagonal liquid crystal panel, one pixel of the pixel portion has an extremely small area of about 18 μm × 18 μm. . Such reduction in pixel size is expected to continue.
[0008]
The biggest problem caused by such a reduction in pixel size is a decrease in aperture ratio in a transmissive liquid crystal display. That is, the effective area of image display is reduced and the brightness is lowered. Furthermore, in order to increase the aperture ratio, it is necessary to take measures such as reducing the occupied area of the TFT or reducing the occupied area of the storage capacitor.
[0009]
As described above, the performance and occupied area conditions required for TFTs with the reduction in pixel size become extremely severe, and in addition, the area conditions of the storage capacitor become severe, so the design of the pixel structure is very difficult. Become.
[0010]
The present invention has been made in view of the above problems, and provides a pixel structure in which a highly reliable TFT is formed with a small area and an area occupied by a storage capacitor is minimized. Thus, it is an object to realize a bright high-definition image even in an electronic device having a very small pixel size of several tens of μm square.
[0011]
It is another object of the present invention to improve the operation performance and reliability of an electronic device by making the structure of TFTs arranged in each circuit appropriate in accordance with the function of the circuit.
[0012]
The operation performance of a semiconductor device (electric appliance) using such an electronic device (typically a liquid crystal display, an electroluminescence display, an electrochromic display, or a field emission display) as a display unit (display for display) and The task is to improve reliability.
[0013]
[Means for Solving the Problems]
The configuration of the invention disclosed in this specification is as follows.
In a semiconductor device including a pixel portion and a driver circuit portion on the same substrate,
The LDD region of the driving TFT forming the driving circuit unit is disposed so as to overlap the gate wiring of the driving TFT with the gate insulating film of the driving TFT interposed therebetween,
The LDD region of the pixel TFT forming the pixel portion is arranged so as not to overlap the gate wiring of the pixel TFT with the gate insulating film of the pixel TFT interposed therebetween,
The storage capacitor of the pixel portion is formed of a light shielding film provided above the pixel TFT, an oxide of the light shielding film, and a pixel electrode.
[0014]
Further, the configuration of the invention related to the manufacturing method is as follows:
In a method for manufacturing a semiconductor device including a pixel portion and a driver circuit portion over the same substrate,
Forming a channel formation region, a source region, a drain region, and an LDD region sandwiched between the drain region and the channel formation region in an active layer of the NTFT that forms the drive circuit portion;
Forming a channel formation region, a source region and a drain region in the active layer of the PTFT forming the driving circuit portion;
Forming a channel formation region, a source region, a drain region, and an LDD region sandwiched between the drain region and the channel formation region in the active layer of the pixel TFT forming the pixel portion;
Including
An LDD region of the NTFT forming the drive circuit unit is formed so as to overlap the gate wiring of the NTFT forming the drive circuit unit with a gate insulating film interposed therebetween,
The LDD region of the pixel TFT is formed so as not to overlap the gate wiring of the pixel TFT with a gate insulating film interposed therebetween,
A storage capacitor of the pixel portion is formed by a light shielding film provided above the pixel TFT, an oxide of the light shielding film, and a pixel electrode.
[0015]
More specifically,
In a method for manufacturing a semiconductor device including a pixel portion and a driver circuit portion over the same substrate,
A first step of forming an active layer on a substrate;
A second step of forming a gate insulating film on the active layer;
A third step of forming a conductive film on the gate insulating film;
A fourth step of patterning the conductive film to form a gate wiring of an NTFT that forms the driving circuit portion;
A fifth step of forming an n region by adding an element belonging to Group 15 of the periodic table to the active layer of the NTFT forming the drive circuit portion using the gate wiring of the NTFT forming the drive circuit portion as a mask;
The n region is diffused by heat treatment so that the n region is formed under the gate wiring of the NTFT forming the drive circuit portion. ^- A sixth step of forming a region;
A seventh step of patterning the conductive film to form a gate wiring of a pixel TFT for forming the pixel portion;
An element belonging to Group 15 of the periodic table is added to the active layer of the pixel TFT using the gate wiring of the pixel TFT as a mask, and n ^- An eighth step of forming a region;
An element belonging to Group 15 of the periodic table is added to the active layer of the NTFT and the active layer of the pixel TFT forming the drive circuit portion, and n ⁺ A ninth step of forming a region;
A tenth step of patterning the conductive film to form a gate wiring of a PTFT for forming the driving circuit portion;
An element belonging to Group 13 of the periodic table is added to the active layer of the PTFT forming the drive circuit section using the gate wiring of the PTFT forming the drive circuit section as a mask, and p ⁺ An eleventh step of forming a region;
A twelfth step of forming an interlayer insulating film made of a resin film above the NTFT and PTFT forming the drive circuit section and the pixel TFT forming the pixel section;
A thirteenth step of forming a light shielding film on the interlayer insulating film;
A fourteenth step of forming an oxide of the light shielding film on the surface of the light shielding film;
A fifteenth step of forming a pixel electrode in contact with the oxide of the light shielding film and overlapping the light shielding film;
It is characterized by having.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view of an AM-LCD in which a drive circuit portion and a pixel portion are integrally formed on the same substrate. Here, a CMOS circuit is shown as a typical basic circuit constituting the drive circuit portion, and a TFT having a double gate structure is shown as the pixel TFT. Of course, not only the double gate structure but also a triple gate structure or a single gate structure may be used.
[0017]
In FIG. 1, reference numeral 101 denotes a substrate having heat resistance, and a quartz substrate, a silicon substrate, a ceramic substrate, or a metal substrate (typically a stainless steel substrate) may be used. Regardless of which substrate is used, a base film (preferably an insulating film containing silicon as a main component) may be provided as necessary.
[0018]
Reference numeral 102 denotes a silicon oxide film provided as a base film, on which a driving TFT active layer, a pixel TFT active layer, and a semiconductor layer serving as a lower electrode of a storage capacitor are formed. Note that in this specification, an “electrode” is a part of “wiring” and refers to a portion where electrical connection with another wiring is made or a portion intersecting with a semiconductor layer. Therefore, for convenience of explanation, “wiring” and “electrode” are properly used, but it is assumed that “electrode” is always included in the term “wiring”.
[0019]
In FIG. 1, the active layer of the driving TFT includes a source region 103, a drain region 104, an LDD (light doped drain) region 105, a channel forming region 106, and a P-channel TFT of an N-channel TFT (hereinafter referred to as NTFT). The source region 107 (hereinafter referred to as PTFT), the drain region 108 and the channel formation region 109 are formed.
[0020]
The active layer of the pixel TFT (here, NTFT is used) is formed of a source region 110, a drain region 111, LDD regions 112a to 112d, and channel formation regions 113a and 113b. Reference numeral 114 denotes a high-concentration impurity region existing between the channel formation regions 113a and 113b, and has the same composition as the source region 110 and the drain region 111 (the same impurity is included at the same concentration). This region functions as a stopper region that prevents off-current from moving to the source region of minority carriers generated at the drain end.
[0021]
A gate insulating film is formed to cover the active layer. In the present invention, the gate insulating film 115 of the driving TFT is formed thinner than the gate insulating film 116 of the pixel TFT. Typically, the thickness of the gate insulating film 115 may be 5 to 50 nm (preferably 10 to 30 nm), and the thickness of the gate insulating film 116 may be 50 to 200 nm (preferably 100 to 150 nm).
[0022]
Note that the gate insulating film of the driving TFT does not need to have a single film thickness. That is, drive TFTs having different insulating films may exist in the drive circuit portion. In that case, there are at least three kinds of TFTs having different gate insulating films on the same substrate.
[0023]
Next, on the gate insulating films 115 and 116, gate wirings 117 and 118 of the driving TFT and gate electrodes 119a and 119b of the pixel TFT are formed. Note that as a formation material of the gate wirings 117 to 119, a conductive film having heat resistance that can withstand a temperature of 800 to 1150 ° C. (preferably 900 to 1100 ° C.) is used.
[0024]
Typically, a conductive silicon film (for example, a phosphorus-doped silicon film or a boron-doped silicon film) or a metal film (for example, a tungsten film, a tantalum film, a molybdenum film, or a titanium film) may be used. A silicided silicide film or a nitrided nitride film (such as a tantalum nitride film, a tungsten nitride film, or a titanium nitride film) may be used. Moreover, you may laminate | stack combining these freely.
[0025]
Further, when the metal film is used, it is desirable to have a laminated structure with a silicon film in order to prevent oxidation of the metal film (which causes an increase in wiring resistance). In terms of preventing oxidation, a structure in which a metal film is covered with an insulating film containing silicon is effective.
[0026]
As the insulating film containing silicon, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (also referred to as a silicon oxynitride film) can be used. Note that a silicon oxynitride film is an insulating film containing oxygen, nitrogen, and silicon at a predetermined ratio.
[0027]
When forming the gate wiring with the above material, an insulating film containing silicon may be provided on the uppermost layer during film formation, and the gate wiring pattern may be formed by etching the insulating film containing silicon and the material together. it can. In this case, only the upper surface of the gate wiring is protected by the insulating film containing silicon.
[0028]
Although the resistance is slightly higher than when a metal film is used, the laminated structure of the metal silicide film and the silicon film is effective because it has high heat resistance and resistance to oxidation. In this case, a protective film for preventing oxidation is not particularly required. Even if the film is oxidized as it is, a problem that the wiring resistance increases only by forming a silicon oxide film on the surface does not occur.
[0029]
Next, 120 is a first interlayer insulating film (lower layer), and 121 is a first interlayer insulating film (upper layer), which is formed of an insulating film containing silicon. On top of this, source wirings 122 and 123 and a drain wiring 124 of the driving TFT, and a source wiring 125 and a drain wiring 126 of the pixel TFT are formed.
[0030]
A passivation film 127 is formed thereon. The passivation film 127 is provided with an opening 128 on the drain wiring 126, and a second interlayer insulating film 129 is formed so as to cover the opening 128. The second interlayer insulating film 129 is preferably a resin film having a low relative dielectric constant. As the resin film, polyimide film, acrylic film, polyamide film, BCB (benzocyclobutene) film, MSSQ (methyl)
silsesquioxane) and the like can be used.
[0031]
On the second interlayer insulating film 129, a light shielding film 130 made of an aluminum film or a film containing aluminum as a main component (a film in which another element is added as an impurity to the aluminum film) is formed, and the light shielding film 130 is formed on the surface thereof. An oxide (alumina film) 131 obtained by oxidizing is formed. When patterning the light shielding film 130, it is preferable to taper about 60 to 85 °. The oxide 131 may be formed by an anodic oxidation method, a thermal oxidation method, or a plasma oxidation method. Note that examples of other elements used as impurities include titanium, scandium, neodymium, and silicon.
[0032]
A contact hole is formed in the second interlayer insulating film 129, and then a pixel electrode 132 is formed. The pixel electrode 132 is electrically connected to the drain wiring 126 through a contact hole. At this time, if a transmissive AM-LCD is manufactured, a transparent conductive film may be used as a pixel electrode, and if a reflective AM-LCD is manufactured, a highly reflective metal film may be used.
[0033]
In addition, a storage capacitor using the oxide 131 as a dielectric is formed in a region where the light shielding film 130 and the pixel electrode 132 overlap. Since the oxide 131 is an alumina film, the relative dielectric constant is as large as 8 to 10 and the film thickness is as thin as 30 to 100 nm (preferably 50 to 70 nm), so that a large capacitance can be formed even in a small area. it can.
[0034]
In addition, the contact hole where the pixel electrode 132 and the drain wiring 126 are electrically connected is a gap between the light shielding films, so that light is allowed to pass therethrough. However, the drain wiring 126 under the contact hole completely prevents light leakage. .
[0035]
Further, the pixel electrode 132 is covered with an alignment film 133. A liquid crystal 134 is held on the alignment film 133. The liquid crystal 134 is held on the pixel portion by a sealing material (not shown) that also serves as a spacer with the counter substrate.
[0036]
On the liquid crystal 134, an alignment film 135 on the counter substrate side, a counter electrode (also referred to as a common electrode) 136 made of a transparent conductive film, and a glass substrate 137 are provided. The alignment film 135, the counter electrode 136, and the glass substrate 137 are collectively referred to as a counter substrate. In the single-plate liquid crystal display, a color filter is further provided on the counter substrate side.
[0037]
The semiconductor device of the present invention having the above structure has the following features.
[0038]
First, among the drive TFTs that form the drive circuit section, the NTFT has a structure in which the LDD region 105 completely overlaps with the gate wiring 117. This is a hot carrier countermeasure aiming at the same effect as the known GOLD structure. On the other hand, PTFT is sufficient in the prior art because hot carrier deterioration is small.
[0039]
The driving TFT is also characterized in that the gate insulating film 115 has a thickness of about 1/5 to 1/10 of the gate insulating film 116 of the pixel TFT. This is a measure for improving the operation speed. Since the operation voltage is low, there is no problem even if the film thickness is 5 to 50 nm.
[0040]
On the other hand, pixel TFTs are different in basic circuit specifications from drive TFTs. First, since suppression of off current (drain current that flows when the TFT is in an off state) is a priority issue rather than operating speed, a normal LDD structure is adopted. Therefore, the LDD regions 112a to 112d are different from the driving TFT in that the LDD regions 112a to 112d are structured so as not to overlap the gate wirings 119a and 119b.
[0041]
In addition, since a high voltage of about 16 V is applied to the gate insulating film 116 at the maximum, a measure is taken to increase the withstand voltage by setting the film thickness to 50 to 200 nm (preferably 100 to 150 nm).
[0042]
Further, there is a feature in that a storage capacitor using the oxide 131 formed in the light shielding film 130 as a dielectric is formed in order to increase the aperture ratio. The storage capacitor is formed by the light shielding film 130, the oxide 131 and the pixel electrode 132.
[0043]
As described above, the semiconductor device of the present invention has various characteristics in the driver circuit portion and the pixel portion, and a synergistic effect of these provides a bright and high-definition image, and an electronic device with high operating performance and reliability. Get. And the high performance electric appliance which mounts such an electronic device as a component is obtained.
[0044]
The present invention having the above-described configuration will be described in more detail with the following examples.
[0045]
【Example】
[Example 1]
In this example, a manufacturing process for realizing the structure of FIG. 1 described in the “Embodiment Mode of the Invention” will be described. 2-5 is used for description.
[0046]
First, a quartz substrate 201 is prepared as a substrate, and a 20 nm thick silicon oxide film 202 and an amorphous silicon film 203 are continuously formed thereon without being released to the atmosphere. By doing so, impurities such as boron contained in the atmosphere can be prevented from being adsorbed on the lower surface of the amorphous silicon film. (Fig. 2 (A))
[0047]
In this embodiment, an amorphous silicon film is used, but another semiconductor film may be used. A microcrystalline silicon (microcrystal silicon) film or an amorphous silicon germanium film may be used. In consideration of the later thermal oxidation process, the film thickness is finally set to 25 to 40 nm.
[0048]
Next, the amorphous silicon film is crystallized. In this embodiment, the technique described in JP-A-9-31260 is used as the crystallization means. The technique described in the publication uses an element selected from nickel, cobalt, palladium, germanium, platinum, iron, copper, tin, and lead as a catalyst element for promoting crystallization.
[0049]
In this embodiment, nickel is selected as the catalyst element, a layer containing nickel (not shown) is formed on the amorphous silicon film 203, and crystallization is performed by heat treatment at 550 ° C. for 4 hours. Then, a crystalline silicon (polysilicon) film 204 is obtained. (Fig. 2 (B))
[0050]
Here, an impurity element (phosphorus or boron) for controlling the threshold voltage of the TFT may be added to the crystalline silicon film 204. Phosphorus or boron may be divided, or only one of them may be added. In this case, it is preferable to add phosphorus in advance to a region that will eventually become the first capacitor electrode of the storage capacitor because it becomes easier to use as an electrode later.
[0051]
Next, a mask film 205 made of a 100 nm thick silicon oxide film is formed on the crystalline silicon film 204, and a resist mask 206 is formed thereon. Further, the mask film 205 is etched using the resist mask 206 as a mask to form openings 207 and 208.
[0052]
In this state, an element belonging to Group 15 of the periodic table (phosphorus in this embodiment) is added to form phosphorus doped regions (phosphorus added regions) 209 and 210. The concentration of phosphorus to be added is 5 × 10 ¹⁸ ~ 1x10 ²⁰ atoms / cm ^Three (Preferably 1 × 10 ¹⁹ ~ 5x10 ¹⁹ atoms / cm ^Three ) Is preferred. However, the concentration of phosphorus to be added is not limited to this concentration range because it varies depending on the temperature and time of the subsequent gettering step and the area of the phosphorus-doped region. (Fig. 2 (C))
[0053]
Next, the resist mask 206 is removed, and heat treatment at 450 to 650 ° C. (preferably 500 to 600 ° C.) is applied for 2 to 16 hours to perform gettering of nickel remaining in the crystalline silicon film. In order to obtain the gettering action, a temperature of about ± 50 ° C. from the maximum temperature of the thermal history is necessary. However, since the heat treatment for crystallization is performed at 550 to 600 ° C., the heat treatment at 500 to 650 ° C. is sufficient. A gettering effect can be obtained.
[0054]
In this embodiment, nickel is moved in the direction of an arrow (see FIG. 2D) by applying a heat treatment at 600 ° C. for 8 hours, and gettering is performed on the phosphorus-doped regions 209 and 210. Thus, the concentration of nickel remaining in the crystalline silicon films denoted by 211a and 211b is 2 × 10. ¹⁷ atoms / cm ^Three The following (preferably 1 × 10 ¹⁶ atoms / cm ^Three Or less). However, this concentration is a measurement result by mass secondary ion analysis (SIMS), and a concentration below this cannot be confirmed at present due to the measurement limit. (Fig. 2 (D))
[0055]
When the nickel gettering step is completed, the crystalline silicon films 211a and 211b are patterned to form an active layer (semiconductor layer) 212 of the CMOS circuit and an active layer 213 of the pixel TFT. At this time, it is desirable to completely remove the phosphorus-added region that has captured nickel.
[0056]
Then, an insulating film (not shown) is formed by plasma CVD or sputtering, and patterned to form the gate insulating film 214. This gate insulating film is an insulating film that functions as a gate insulating film of the pixel TFT, and has a thickness of 50 to 200 nm. In this embodiment, a silicon oxide film having a thickness of 80 nm is used. Further, another insulating film containing silicon may be used as a single layer or a stacked layer. (Fig. 3 (A))
[0057]
At this time, the gate insulating film 214 is formed so as to remain on the pixel TFT, and the region that becomes the CMOS circuit is removed. In the present embodiment, only the CMOS circuit is described, but in practice, it is removed on a region that becomes a part of the drive circuit portion (particularly, a circuit group that requires high-speed operation). Therefore, it is desirable to leave an insulating film having the same thickness as the gate insulating film 214 only in the case of a circuit in which a high voltage is applied to the gate insulating film, such as a buffer circuit.
[0058]
Next, a heat treatment step at a temperature of 800 to 1150 ° C. (preferably 900 to 1100 ° C.) for 15 minutes to 8 hours (preferably 30 minutes to 2 hours) is performed in an oxidizing atmosphere (thermal oxidation step). In this embodiment, a heat treatment step at 950 ° C. for 30 minutes is performed in an oxygen atmosphere.
[0059]
Note that the oxidizing atmosphere may be either a dry oxygen atmosphere or a wet oxygen atmosphere, but a dry oxygen atmosphere is suitable for reducing crystal defects in the semiconductor layer. Alternatively, an atmosphere in which a halogen element is included in an oxygen atmosphere may be used. This thermal oxidation process in an atmosphere containing a halogen element is effective because an effect of removing nickel can be expected.
[0060]
By performing the thermal oxidation process in this way, a silicon oxide film (thermal oxide film) of 5 to 50 nm (preferably 10 to 30 nm) is formed on a portion where the gate insulating film 214 is not formed (a portion where the active layer is exposed). 215 is formed. In this embodiment, a 30 nm silicon oxide film is formed, and finally the silicon oxide film 215 functions as a gate insulating film of the CMOS circuit.
[0061]
The oxidation reaction also proceeds at the interface between the gate insulating film 214 made of a silicon oxide film remaining in the pixel TFT and the semiconductor layer 213 below the gate insulating film 214. Therefore, the film thickness of the gate insulating film 216 of the pixel TFT is finally 50 to 200 nm (preferably 100 to 150 nm). In this embodiment, the thickness is 110 nm.
[0062]
In this embodiment, the silicon oxide film 215 is formed by a thermal oxidation method, but a thin silicon oxide film may be formed by a low pressure thermal CVD method. In that case, the film formation temperature is about 800 ° C., and silane and oxygen may be used as the film formation gas.
[0063]
When the thermal oxidation process is completed in this way, a conductive film having a laminated structure of silicon film / tungsten silicide film is formed, and gate wiring 217 of the NTFT of the CMOS circuit is formed by patterning. At this time, the conductive film 218 having the above-described structure is left in the regions to be the PTFT and the pixel TFT of the CMOS circuit. (Fig. 3 (B))
[0064]
In this structure, the silicon film located under the conductive film may have a thickness of about 20 to 70 nm. However, it is preferable to use a low pressure thermal CVD method for film formation. This is because the gate insulating film of the CMOS circuit is very thin, and if the sputtering method or the plasma CVD method is used, damage may be left in the insulating film.
[0065]
Needless to say, the material of the gate wiring that can be used in this embodiment is not limited to this, and any material described in the “Embodiments of the Invention” can be used. In this embodiment, the thickness of the conductive film 218 is 300 nm.
[0066]
When the patterning of the conductive film is completed in this manner, an addition process of an element belonging to Group 15 of the periodic table (phosphorus in this embodiment) using the resist mask (not shown) used for forming the gate wiring 217 and the conductive film 218 as a mask. Then, impurity regions (hereinafter referred to as n regions) 219a and 219b are formed.
[0067]
Note that in this specification, an ion implantation method in which mass separation is performed or a plasma doping method in which mass separation is not performed may be used for the step of adding the impurity element imparting such a conductivity type. Also good.
[0068]
At this time, the n regions 219a and 219b have 1 × 10 ¹⁸ ~ 1x10 ¹⁹ atoms / cm ^Three The set dose is adjusted so that phosphorus is contained at a concentration of (this concentration is represented by n). This concentration has an important meaning in the subsequent heat treatment step.
[0069]
Next, a resist mask (not shown) is removed, and heat treatment is performed in a temperature range of 700 to 1000 ° C. (preferably 800 to 900 ° C.) to activate phosphorus. At the same time, phosphorus is diffused in the lateral direction to overlap the gate wiring 215 (hereinafter referred to as n region). ^- 220a, 220b). This n ^- In the regions 220a and 220b, 5 × 10 ¹⁷ ~ 5x10 ¹⁸ atoms / cm ^Three Contains phosphorus at a concentration of. (Figure 3 (C))
[0070]
The impurity diffusion distance can be controlled by the temperature and time of the heat treatment. Therefore, n ^- The lengths (widths) of the regions 218a and 218b can be freely controlled. In this embodiment, the overlap distance is adjusted to 0.3 to 1 μm (preferably 0.5 to 0.7 μm).
[0071]
Thus, the concentration of the above-described n regions 217a and 217b depends on this activation condition and n ^- It depends on the trade-off between the phosphorus concentration required for the region and the required length.
[0072]
Note that the active layer of the CMOS circuit is oxidized again by this heat treatment process, and the thickness of the gate insulating film 213 increases. N as above ^- Under the heat treatment conditions for forming the region, the film thickness typically increases by 20 to 50 nm. However, an increase in film thickness can be prevented by performing heat treatment after providing a cap layer in order to prevent oxidation.
[0073]
At the same time, the gate wiring 215 and the conductive film 216 are oxidized to form thermal oxide films 219 and 220 on the surface. When a laminated film of a silicon film and a metal silicide film is used as in this embodiment, silicon is preferentially oxidized on the surface, so that the formed thermal oxide film is a silicon oxide film.
[0074]
Next, the conductive film 216 is patterned to form pixel TFT gate wirings 221a and 221b. At this time, the conductive film 222 is left in the PTFT of the CMOS circuit. (Fig. 3 (D))
[0075]
Then, using the gate wirings 215, 221a, 221b and the conductive film 222 as a mask, an addition process of an element belonging to Group 15 of the periodic table (phosphorus in this embodiment) is performed. ¹⁶ ~ 1x10 ¹⁸ atoms / cm ^Three A low-concentration impurity region containing phosphorus at a concentration of ^- 223a to 223c). At this time, phosphorus is also added to the above-described n regions 217a and 217b. However, since the concentration of added phosphorus is sufficiently lower than that of phosphorus contained in the n region, the amount of increase is not a problem.
[0076]
In this embodiment, n ^- The region is formed because the resistance value is increased as much as possible to increase the effect of suppressing the off-current. Therefore, in this phosphorus addition step, n ^- N instead of region ^- It is also possible to form a region.
[0077]
Further, this step may be performed separately for the driver circuit portion where the gate insulating film is thin and the thick pixel portion, or may be performed simultaneously. However, it is necessary to carefully control the concentration of the LDD region. Therefore, in this embodiment, the plasma doping method is used, and the concentration distribution (concentration profile) of the added phosphorus is set as shown in FIG.
[0078]
In FIG. 6, the gate insulating film 601 on the driver circuit portion side and the gate insulating film 602 on the pixel portion side have different film thicknesses. For this reason, the concentration distribution of the added phosphorus in the depth direction is different.
[0079]
In this embodiment, the phosphorus addition conditions (acceleration voltage, etc.) are adjusted so as to have a concentration distribution indicated by 603 on the drive circuit portion side and a concentration distribution indicated by 604 on the pixel portion side. In this case, although the concentration distribution in the depth direction is different, the phosphorus concentrations of the low-concentration impurity regions 605 and 606 formed as a result are substantially equal.
[0080]
The process shown in FIG. 6 can be used in all impurity addition processes described in this specification.
[0081]
Next, resist masks 224, 225a, and 225b are formed, and an addition process of an element belonging to group 15 of the periodic table (phosphorus in this embodiment) is performed again, and 5 × 10 5 ¹⁹ ~ 1x10 ^{twenty one} atoms / cm ^Three High concentration impurity regions (hereinafter referred to as n <+> regions) 226 to 230 containing phosphorus at a concentration of 1 are formed. (Fig. 4 (A))
[0082]
By this step, the source region 226, the drain region 227, the LDD region 231 and the channel formation region 232 are defined in the NTFT of the CMOS circuit. Further, the source region 228, the drain region 229, the LDD regions 233a and 233b, and the channel formation regions 234a and 234b of the pixel TFT are defined.
[0083]
Note that the n + region 230 functions as a stopper region that prevents the movement of minority carriers (in this embodiment, holes) that cause off-current. However, if not particularly required, a structure in which the LDD regions 233a and 233b are in contact with each other may be used.
[0084]
When the state of FIG. 4A is thus obtained, the conductive film 222 left on the region to be the PTFT of the CMOS circuit is patterned to form the gate wiring 235. Then, using the resist masks 236a to 236c used at that time, an addition process of an element belonging to group 13 of the periodic table (boron in this embodiment) is performed, and 5 × 10 5 ¹⁹ ~ 1x10 ^{twenty one} atoms / cm ^Three High-concentration impurity regions containing boron at a concentration of 237 to 239 (hereinafter referred to as p + regions) are formed. (Fig. 4 (B))
[0085]
By this step, a source region 237, a drain region 238, and a channel formation region 239 are defined in the PTFT of the CMOS circuit.
[0086]
Thus, the formation of all impurity regions is completed. Note that the order of the impurity addition step is not limited to the order of this embodiment, and can be formed in any order. The order of addition of impurities can be appropriately determined by the practitioner in consideration of problems in apparatus performance.
[0087]
When the impurity regions are thus formed, the resist masks 236a to 236c are removed. Then, an insulating film (insulating film containing silicon) 240 having a thickness of 60 to 200 nm (preferably 100 to 150 nm) is formed as a lower layer of the first interlayer insulating film. Since this insulating film functions as a protective film for preventing oxidation of the gate wiring, it is preferable to use a silicon oxynitride film.
[0088]
After the first interlayer insulating film (lower layer) 240 is thus formed, a heat treatment step is performed for 1 to 8 hours in a temperature range of 550 to 800 ° C. In this embodiment, heat treatment is performed at 600 ° C. for 2 hours in a nitrogen atmosphere. (Fig. 4 (C))
[0089]
In this step, the phosphorus or boron added to each impurity region is activated, and at the same time, damage caused to the gate insulating film and the active layer due to the impurity addition is recovered. Here, it is preferable to activate while suppressing the diffusion of phosphorus and boron as much as possible. When it is necessary to apply a high temperature, it is necessary to sufficiently take into account that phosphorus and boron of each TFT diffuse into the channel formation region.
[0090]
Then, hydrogenation treatment is further performed at 350 ° C. for 1 hour. This hydrogenation process is a process of exposing to hydrogen excited by heat or plasma.
[0091]
When the state of FIG. 4C is thus obtained, a first interlayer insulating film (upper layer) 241 is formed. As the first interlayer insulating film (upper layer) 241, an insulating film containing silicon (a silicon oxide film in this embodiment) may be used.
[0092]
Next, contact holes are formed in the first interlayer insulating film (upper layer) 241 and the first interlayer insulating film (lower layer) 240, and an aluminum alloy film (aluminum film added with 1 wt% titanium) is sandwiched between the titanium films. A conductive film (not shown) having a layer structure is formed. Then, the conductive film is patterned to form the source wirings 242 and 243 and the drain wiring 244 of the CMOS circuit, and the source wiring 245 and the drain wiring 246 of the pixel TFT. For the pixel TFT, the source wiring and the drain wiring are alternately switched.
[0093]
After the source wiring and the drain wiring are formed in this way, a silicon nitride film having a thickness of 300 nm is provided as the passivation film 247, and a hydrogenation process is performed at 300 ° C. for 1 hour. This hydrogenation process is also a process of exposing to hydrogen excited by heat or plasma. In this process, hydrogen released from the passivation film 247 and hydrogen contained in a large amount in the first interlayer insulating film (lower layer) 240 by the previous hydrogenation process diffuse downward (upward direction is the passivation film). 247 becomes a blocking layer), and the active layer is hydrogen-terminated.
[0094]
Note that as the passivation film 247, a silicon oxynitride film, a silicon oxide film, or a stacked film of insulating films containing these silicon can be used in addition to the silicon nitride film. In this embodiment, it is effective to perform a plasma treatment using a gas containing hydrogen (typically ammonia gas) as a pretreatment for forming the passivation film 247. Hydrogen activated (excited) by plasma by this pretreatment is confined by the passivation film 247. If hydrogenation is performed on that, the hydrogenation efficiency will be greatly improved.
[0095]
Further, when a nitrous oxide gas is added in addition to a gas containing hydrogen, the surface of the object to be processed is cleaned by the generated moisture, and contamination by boron or the like contained in the atmosphere can be effectively prevented.
[0096]
When the hydrogenation process is completed, the passivation film 247 is removed over the drain wiring 246 to form an opening 248. Next, an acrylic film having a thickness of 1 μm is formed as the second interlayer insulating film 249. Besides acrylic, a resin film such as polyimide, polyamide, polyimide amide, BCB (benzocyclobutene) can be used. Here, it is desirable to ensure sufficient flatness.
[0097]
Then, a light shielding film 250 made of an aluminum film is formed on the second interlayer insulating film 249 by sputtering. As this light shielding film, 1. An oxide can be easily formed on the surface. 2. The oxide has high dielectric constant and insulation resistance. Any material may be used as long as it satisfies the condition of having sufficient light shielding properties. In that sense, it can be said that an aluminum film or an aluminum alloy film is most suitable.
[0098]
In this embodiment, a light-shielding film 250 having a thickness of 135 nm is first formed using a high-purity aluminum film (five nine). At this time, the light shielding film 250 is formed so as to hide the source wiring, gate wiring, and TFT body of the pixel TFT, and is formed in a matrix in the pixel portion. However, a contact portion where the drain wiring and the pixel electrode are electrically connected later is opened without forming a light shielding film.
[0099]
In this embodiment, as a pretreatment for forming the light shielding film 250, CF is applied to the surface of the second interlayer insulating film 249. _Four Plasma treatment using gas is performed. This treatment improves the adhesion between the light shielding film 250 made of an aluminum film and the second interlayer insulating film 249 made of a resin film.
[0100]
Next, the light shielding film 250 is anodized to form an anodic oxide 251 on the surface. (Fig. 5 (A))
[0101]
In this embodiment, a solution obtained by mixing a 15% ammonium tartrate solution and an ethylene glycol solution at 2: 8 is used as the chemical conversion solution. Then, a substrate is placed in a solution kept at 10 ° C. to form a conversion current (60 μA / cm in this example). ² ) And anodic oxidation. When the formation voltage reaches 35 V, the voltage is switched to a constant voltage and held for 15 minutes to complete the anodizing process.
[0102]
Thus, an anodic oxide (alumina film in this embodiment) having a thickness of about 50 nm is formed on the surface of the light shielding film 250, and the final thickness of the light shielding film 250 is 150 nm.
[0103]
Next, the second interlayer insulating film 249 is etched inside the gap between the light shielding films provided in the contact portion between the drain wiring and the pixel electrode, thereby forming a contact hole 252 reaching the drain wiring 246. A pixel electrode 253 made of a transparent conductive film (ITO film in this embodiment) is formed thereon with a thickness of 100 nm. (Fig. 5 (B))
[0104]
At this time, a region 254 where the pixel electrode 253 overlaps with the light shielding film 250 is a region functioning as a storage capacitor. In this case, since the alumina film serving as a dielectric is as thin as about 50 nm and the relative dielectric constant is as high as 8 to 9, a large capacity can be obtained.
[0105]
The portion where the contact hole 252 is formed is not shielded because it is a gap between the light shielding films 250, but there is no problem because the light can be completely shielded by the drain wiring 246 therebelow. Therefore, it is desirable that the contact hole 252 be formed on the inner side with a margin of at least 0.5 μm (preferably 1 μm) from the end of the drain wiring 246.
[0106]
Thus, an active matrix substrate having a structure as shown in FIG. 5B is completed. Thereafter, the AM-LCD as shown in FIG. 1 can be manufactured by a known cell assembling process.
[0107]
The AM-LCD of the present invention has several structural features and exhibits very high operation performance and reliability due to their synergistic effects. One structural feature is that the thickness of the gate insulating film differs between the driver circuit portion and the pixel portion formed over the same substrate. Typically, a part of driving TFTs (circuits that require high-speed operation) used in the driving circuit portion has a thinner gate insulating film than the pixel TFTs.
[0108]
As a result, TFTs with very high field-effect mobility can be arranged in a circuit that requires high-speed operation, and the circuit requirements can be sufficiently satisfied. A circuit with high reliability can be formed by disposing a TFT in which a breakdown voltage characteristic is more important than an operation speed in a circuit (a pixel portion, a buffer circuit, an analog switch circuit, etc.) that requires a high gate dielectric breakdown voltage.
[0109]
However, this does not mean that the thickness of the gate insulating film should not be the same between the driver circuit portion and the pixel portion. Since the operation speed and the gate withstand voltage are in a trade-off relationship, the above structure is desirable in that case.
[0110]
Further, as another feature, a normal LDD structure is adopted for a circuit that emphasizes reduction of off-current such as a pixel portion, and a so-called GOLD structure is adopted for a circuit that emphasizes hot carrier countermeasures such as a drive circuit portion. Thus, an LDD region provided so as to overlap the gate wiring is arranged. As a result, TFTs having sufficient reliability can be arranged according to circuit performance.
[0111]
A further feature is that the oxide of the light shielding film is used as a dielectric when the storage capacitor is formed of the light shielding film and the pixel electrode. Another feature is that an aluminum film or a film containing aluminum as a main component is used as the light-shielding film. As a result, a large capacity can be secured with a very small area, and the effective display area of the pixel can be improved (the aperture ratio can be improved).
[0112]
Further, according to the manufacturing process of this embodiment, the final active layer (semiconductor layer) of the TFT is formed of a crystalline silicon film having a unique crystal structure having continuity in the crystal lattice. The features will be described below.
[0113]
First, as a first feature, the crystalline silicon film formed in accordance with the manufacturing process of the present embodiment has a plurality of needle-like or rod-like crystals (hereinafter abbreviated as rod-like crystals) arranged in a microscopic view. It has a crystal structure. This can be easily confirmed by observation with TEM (transmission electron microscopy).
[0114]
In addition, as a second feature, when electron beam diffraction is used, the surface of the crystalline silicon film formed in accordance with the manufacturing process of this embodiment (portion forming portion) includes a slight shift in the crystal axis. The {110} plane can be confirmed as the main orientation plane. This is confirmed by observing diffraction spots having regularity specific to the {110} plane when an electron diffraction photograph having a spot diameter of about 1.35 μm is observed. It has also been confirmed that each spot has a concentric distribution.
[0115]
As a third feature, when the orientation ratio is calculated using an X-ray diffraction method (strictly, an X-ray diffraction method using the θ-2θ method), the orientation ratio of the {220} plane is 0.7. It is confirmed that it is above (typically 0.85 or more). In addition, the method described in Unexamined-Japanese-Patent No. 7-321339 is used for the calculation method of orientation ratio.
[0116]
As a fourth feature, the applicant observes a grain boundary formed by contact of individual rod-like crystals with HR-TEM (High Resolution Transmission Electron Microscopy), and continuity with the crystal lattice at the grain boundary. Make sure that there is. This can be easily confirmed because the observed lattice fringes are continuously connected at the grain boundaries.
[0117]
Note that the continuity of the crystal lattice at the crystal grain boundary results from the fact that the crystal grain boundary is a grain boundary called a “planar grain boundary”. The definition of the planar grain boundary in this specification is “Characterization of High-Efficiency Cast-Si Solar Cell Wafers by MBIC Measurement; Ryuichi Shimokawa and Yutaka Hayashi, Japanese Journal of Applied Physics vol.27, No.5, pp.751”. -758, 1988 ”is the“ Planar boundary ”.
[0118]
According to the above paper, planar grain boundaries include twin grain boundaries, special stacking faults, and special twist grain boundaries. This planar grain boundary is characterized by being electrically inactive. That is, although it is a crystal grain boundary, it does not function as a trap that inhibits the movement of carriers, and thus can be regarded as substantially nonexistent.
[0119]
In particular, when the crystal axis (axis perpendicular to the crystal plane) is the <110> axis, the {211} twin grain boundary is also called a corresponding grain boundary of Σ3. The Σ value is a parameter that serves as a guideline indicating the degree of consistency of the corresponding grain boundary. It is known that the smaller the Σ value, the better the grain boundary. For example, in a crystal grain boundary formed between two crystal grains, if the plane orientation of both crystals is {110}, θ = 70.5 °, where θ is the angle formed by lattice fringes corresponding to the {111} plane. It is known that it becomes a corresponding grain boundary of Σ3.
[0120]
In the crystalline silicon film obtained by carrying out this example, when a crystal grain boundary formed between two crystal grains having a crystal axis <110> is observed by HR-TEM, each of adjacent crystal grains is observed. In many cases, the lattice pattern is continuous at an angle of about 70.5 °. Therefore, it can be inferred that the grain boundary is the corresponding grain boundary of Σ3, that is, the {211} twin boundary.
[0121]
Such a crystal structure (exactly, the structure of the crystal grain boundary) indicates that two different crystal grains are joined with extremely good consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and the trap level caused by crystal defects or the like is very difficult to create. Therefore, it can be considered that the semiconductor thin film having such a crystal structure is substantially free of crystal grain boundaries.
[0122]
Furthermore, it was confirmed by TEM observation that defects existing in the crystal grains were almost disappeared by the heat treatment step (corresponding to the thermal oxidation step or gettering step in this embodiment) at a high temperature of 700 to 1150 ° C. Yes. This is also clear from the fact that the number of defects is greatly reduced before and after this heat treatment step.
[0123]
The difference in the number of defects appears as a difference in spin density by electron spin resonance analysis (Electron Spin Resonance: ESR). At present, the spin density of the crystalline silicon film fabricated according to the fabrication process of this example is at least 5 × 10 ¹⁷ spins / cm ^Three Below (preferably 3 × 10 ¹⁷ spins / cm ^Three The following): However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be even lower.
[0124]
From the above, the crystalline silicon film obtained by carrying out this embodiment is considered to be a single crystal silicon film or a substantially single crystal silicon film because there are substantially no crystal grains and no crystal grain boundaries. Good.
[0125]
(Knowledge about electrical characteristics of TFT)
The TFT fabricated in this example (same structure as the CMOS circuit shown in FIG. 1) exhibited electrical characteristics comparable to a MOSFET. The following data is obtained from the TFT manufactured by the applicant of the present invention (however, the thickness of the active layer is 35 nm and the thickness of the gate insulating film is 80 nm).
[0126]
(1) Sub-threshold coefficient that is an index of switching performance (ON / OFF operation switching agility) is 80 to 150 mV / decade for both N-channel and P-channel TFTs (typically 100 to 120 mV / decade) And small.
(2) Field-effect mobility (μ _FE ) 150-650cm for N-channel TFT ² / Vs (typically 200-500cm ² / Vs), 100-300cm with P-channel TFT ² / Vs (typically 120-200cm ² / Vs).
(3) Threshold voltage (V _th ) Is as low as -0.5 to 1.5 V for N-channel TFTs and -1.5 to 0.5 V for P-channel TFTs.
[0127]
As described above, it has been confirmed that extremely excellent switching characteristics and high-speed operation characteristics can be realized.
[0128]
[Example 2]
In Embodiment 1, the light shielding film 250 may be held at a common potential or in a floating state. However, there is no problem if it is in a floating state, but when dropping to a common potential, a connection terminal for dropping the light shielding film to the common potential is required. In this embodiment, the structure will be described with reference to FIG.
[0129]
In FIG. 7A, reference numeral 701 denotes a common power supply line, which is a wiring formed simultaneously with the source wiring and the drain wiring. 702 is a second interlayer insulating film, 703 is a light shielding film, and 704 is an anodic oxide.
[0130]
In this case, before forming the light shielding film 250 in the step of FIG. 5A, a contact hole 705 (FIG. 7A) is formed in the second interlayer insulating film 249 (corresponding to 702 in FIG. 7A). ), And then a light-shielding film 250 (corresponding to 703 in FIG. 7A) may be formed. As a result, the light shielding film 703 can be easily held at a common potential.
[0131]
When this state is viewed from above, the state is as shown in FIG. FIG. 7A is a cross-sectional view taken along AA ′ of the top view of FIG. Reference numerals may be referred to FIG. Since this example is one of the embodiments of Example 1, Example 1 is referred to for conditions such as a manufacturing process.
[0132]
Example 3
The present embodiment is an example of another form of the second embodiment. The structure of this example is shown in FIG. In FIG. 8A, reference numeral 801 denotes a common power supply line, which is a wiring formed simultaneously with the source wiring and the drain wiring. Reference numeral 802 denotes a second interlayer insulating film, 803 denotes a light shielding film, 804 denotes an anodic oxide, and 805 denotes a transparent conductive film formed simultaneously with the pixel electrode.
[0133]
In this case, when the contact hole 252 is formed in the second interlayer insulating film 249 in the step of FIG. 5B, a part of the second interlayer insulating film 802 is formed at the connection terminal portion as shown in FIG. The common power supply line 801 is exposed to be removed. At the same time as the formation of the pixel electrode 253, a transparent conductive film 805 is formed in the connection terminal portion.
[0134]
At this time, an anodic oxide 804 is present between the light shielding film 803 and the transparent conductive film 805, thereby forming a capacitor 806. However, in consideration of AC driving, the capacitor 806 can be regarded as substantially short-circuited, and the light shielding film 803 and the common power supply line 801 can be regarded as being electrically connected. .
[0135]
When this state is viewed from above, it is as shown in FIG. FIG. 8A is a cross-sectional view taken along AA ′ of the top view of FIG. Reference numerals may be referred to FIG. Since this example is one of the embodiments of Example 1, Example 1 is referred to for conditions such as a manufacturing process.
[0136]
Example 4
In FIG. 1, capacitive coupling using a liquid crystal 134 as a dielectric (strictly including alignment films 133 and 135 and an oxide 131) is generated between the light shielding film 130 and the counter electrode 136 on the counter substrate side. Therefore, when the capacitive coupling is large, the light shielding film 130 is held at the common potential by the effect of the coupling.
[0137]
That is, even if the light shielding film 130 is not connected to another wiring, it can be held at a common potential by capacitive coupling with the counter electrode. The present embodiment is an example in which the light shielding film 130 is held at a common potential by such a method. Since this example is one of the embodiments of Example 1, Example 1 is referred to for conditions such as a manufacturing process.
[0138]
Example 5
In this embodiment, a specific structure of a TFT and a structure of a circuit will be described with reference to FIG.
[0139]
The minimum required operating voltage (power supply voltage) varies depending on the circuit of the AM-LCD. For example, when considering the voltage applied to the liquid crystal and the voltage for driving the pixel TFT in the pixel portion, the operating voltage is 14 to 20V. Therefore, a TFT that can withstand such a high voltage must be used.
[0140]
An operation voltage of about 5 to 10 V is sufficient for a shift resist circuit used for a source driving circuit and a gate driving circuit. The lower the operating voltage, the more compatible with external signals, and the further advantage is that power consumption can be reduced. However, the high breakdown voltage TFT described above is not suitable for a circuit that requires high-speed operation, such as a shift register circuit, because the operation speed is sacrificed instead of good breakdown voltage characteristics.
[0141]
As described above, the circuit formed on the substrate is divided into a circuit for obtaining a TFT with an emphasis on breakdown voltage characteristics and a circuit for obtaining a TFT with an emphasis on operation speed according to the purpose.
[0142]
Here, the configuration of this embodiment is specifically shown in FIG. FIG. 9A shows a top view of the block diagram of the AM-LCD. Reference numeral 901 denotes a pixel portion, and each pixel includes a pixel TFT and a storage capacitor and functions as a display portion. 902a is a shift register circuit, 902b is a level shifter circuit, and 902c is a buffer circuit. These circuits as a whole form a gate drive circuit section.
[0143]
Note that in the AM-LCD shown in FIG. 9A, a gate drive circuit is provided with a pixel portion interposed therebetween and shares the same gate wiring, that is, one of the gate drivers has a defect. However, redundancy is provided such that a voltage can be applied to the gate wiring.
[0144]
Further, reference numeral 903a denotes a shift register circuit, 903b denotes a level shifter circuit, 903c denotes a buffer circuit, and 903d denotes a sampling circuit. These circuits form a source driving circuit as a whole. A precharge circuit 904 is provided on the opposite side of the source driver circuit across the pixel portion.
[0145]
In the AM-LCD configured as described above, the shift register circuits 902a and 903a are circuits that require high-speed operation, and have an operating voltage as low as 3.3 to 10 V (typically 3.3 to 5 V) and a high breakdown voltage. No special properties are required. Therefore, the gate insulating film should be as thin as 5 to 50 nm (preferably 10 to 30 nm).
[0146]
FIG. 9B is a schematic diagram of a CMOS circuit to be used mainly for a circuit that requires high-speed operation, such as a shift register circuit or a signal dividing circuit. In FIG. 9B, reference numeral 905 denotes a gate insulating film, which is designed to have a thin film thickness of 5 to 50 nm (preferably 10 to 30 nm).
[0147]
The length of the LDD region 906 is preferably 0.1 to 1 μm (typically 0.3 to 0.5 μm). If the operating voltage is sufficiently low, such as 2 to 3 V, the LDD region can be omitted. Of course, the structure is such that it completely overlaps with the gate wiring to prevent hot carrier deterioration.
[0148]
Next, the CMOS circuit illustrated in FIG. 9C is suitable mainly for the level shifter circuits 902b and 903b, the buffer circuits 902c and 903c, the sampling circuit 903d, and the precharge circuit 904. Since these circuits require a large current to flow, the operating voltage is as high as 14 to 16V. In particular, on the gate driver side, an operating voltage of 19V may be required depending on circumstances. Therefore, a TFT having a very good breakdown voltage characteristic (high breakdown voltage characteristic) is required.
[0149]
At this time, in the CMOS circuit shown in FIG. 9C, the thickness of the gate insulating film 907 is designed to be 50 to 200 nm (preferably 100 to 150 nm). In such a circuit requiring a high gate withstand voltage, it is preferable to make the gate insulating film thicker than a TFT such as a shift register circuit.
[0150]
The length of the LDD region 908 is preferably 1 to 3 μm (typically 1.5 to 2 μm). Note that the length of the portion overlapping the gate wiring in the LDD region may be 0.5 to 2 μm (preferably 1 to 1.5 μm). In addition, the remainder becomes an LDD region that does not overlap with the gate wiring. By disposing such a region, off current can be effectively suppressed. Note that since the CMOS circuit illustrated in FIG. 9C is applied with a high voltage similar to that of a pixel like a buffer circuit or the like, the length of the LDD region is preferably equal to or close to that of the pixel.
[0151]
Next, FIG. 9D shows a schematic diagram of the pixel portion 901. Since the pixel TFT takes into account the voltage applied to the liquid crystal, an operating voltage of 14 to 16 V is required. In addition, since the charge accumulated in the liquid crystal and the storage capacitor must be held for one frame period, the off current must be as small as possible.
[0152]
For this reason, in this embodiment, a double gate structure using NTFT is used, and the thickness of the gate insulating film 909 is 50 to 200 nm (preferably 100 to 150 nm). This film thickness may be the same film thickness as the CMOS circuit shown in FIG. 9C, or may be a different film thickness.
[0153]
The length of the LDD regions 910a and 910b is preferably 2 to 4 μm (typically 2.5 to 3.5 μm). Note that the pixel TFT illustrated in FIG. 9D has a feature in that the LDD regions 910a and 910b are not overlapped with the gate wiring because the off-state current needs to be reduced as much as possible.
[0154]
As described above, even with an AM-LCD as an example, various circuits are provided on the same substrate, and the required operating voltage (power supply voltage) may differ depending on the circuit. In this case, it is necessary to selectively use TFTs having different gate insulating film thicknesses as in the present invention.
[0155]
In order to realize the configuration of this embodiment, it is effective to use the circuit shown in Embodiment 1.
[0156]
Example 6
In the first embodiment, in the step of selectively removing the gate insulating film, it is desirable that the removal in the region to be the driving TFT is performed as shown in FIG. In FIG. 10, 11 is an active layer, 12 is an end of a gate insulating film, and 13 and 14 are gate wirings. As shown in FIG. 10, it is desirable to leave the gate insulating film at the end of the active layer 11 in the portion 15 where the gate wiring goes over the active layer.
[0157]
A phenomenon called edge thinning occurs at the end of the active layer 11 when a thermal oxidation process is performed later. This is a phenomenon in which the oxidation reaction proceeds so as to sink under the edge of the active layer, and the edge becomes thinner and rises at the same time. Therefore, when the edge thinning phenomenon occurs, there arises a problem that the gate wiring easily breaks when the gate wiring is overcome.
[0158]
However, if the gate insulating film is removed so that the structure shown in FIG. 10 is obtained, the edge thinning phenomenon can be prevented in the portion 15 where the gate wiring crosses over. Therefore, problems such as disconnection of the gate wiring can be prevented in advance. Note that it is effective to use the configuration of this embodiment in the first embodiment.
[0159]
Example 7
In this embodiment, a case will be described in which a TFT is formed on a substrate in the manufacturing process shown in Embodiment 1 and an AM-LCD is actually manufactured.
[0160]
When the state of FIG. 5B is obtained, an alignment film is formed on the pixel electrode 253 to a thickness of 80 nm. Next, a glass substrate with a color filter, a transparent electrode (counter electrode), and an alignment film formed thereon is prepared as a counter substrate, and each alignment film is rubbed and a sealing material (sealing material) is used. The substrate on which the TFT is formed is bonded to the counter substrate. In the meantime, the liquid crystal is held. Since this cell assembling process may use a known means, a detailed description thereof will be omitted.
[0161]
In addition, what is necessary is just to provide the spacer for maintaining a cell gap as needed. Therefore, when the cell gap can be maintained without the spacer as in the AM-LCD having a diagonal of 1 inch or less, it is not particularly necessary.
[0162]
Next, the appearance of the AM-LCD manufactured as described above is shown in FIG. An active matrix substrate (referred to as a substrate on which a TFT is formed) 21 includes a pixel portion 22, a source driving circuit 23, a gate driving circuit 24, a signal processing circuit (signal dividing circuit, D / A converter circuit, γ correction circuit, differential). An amplification circuit 25) is formed, and an FPC (flexible printed circuit) 26 is attached. Reference numeral 27 denotes a counter substrate.
[0163]
In addition, a present Example can be freely combined with any Example of Examples 1-6.
[0164]
Example 8
In this embodiment, a case where another means is used for forming the crystalline silicon film in Embodiment 1 will be described.
[0165]
Specifically, the technique described in Example 2 of Japanese Patent Laid-Open No. 7-130652 is used for crystallization of the amorphous silicon film. In the technique described in the publication, a catalyst element (typically nickel) that promotes crystallization is selectively held on the surface of an amorphous silicon film, and that portion is used as a seed for nucleus growth for crystallization. Technology.
[0166]
According to this technique, since the crystal growth can have a specific direction, it is possible to form a crystalline silicon film having very high crystallinity.
[0167]
It is also possible to use a mask insulating film provided for selectively holding the catalytic element as a phosphorus mask added for gettering. By doing so, the number of steps can be reduced. This technique is described in detail in Japanese Patent Application Laid-Open No. 10-247735 by the present applicant.
[0168]
In addition, the structure of a present Example can be freely combined with any structure of Examples 1-7.
[0169]
Example 9
Phosphorus was used to getter nickel (catalyst element used to crystallize the silicon film) described in the first embodiment. In this embodiment, nickel is gettered using another element. explain.
[0170]
First, according to the process of Example 1, the state of FIG. In FIG. 2B, reference numeral 204 denotes a crystalline silicon film. However, in this embodiment, the concentration of nickel used for crystallization is made as low as possible. Specifically, a layer containing 0.5 to 3 ppm of nickel in terms of weight is formed on the amorphous silicon film, and heat treatment for crystallization is performed. The nickel concentration contained in the crystalline silicon film thus formed is 1 × 10 ¹⁷ ~ 1x10 ¹⁹ atoms / cm ^Three (Typically 5 × 10 ¹⁷ ~ 1x10 ¹⁸ atoms / cm ^Three )
[0171]
After the crystalline silicon film is formed, heat treatment is performed in an oxidizing atmosphere containing a halogen element. The temperature is 800 to 1150 ° C. (preferably 900 to 1000 ° C.), and the treatment time is 10 minutes to 4 hours (preferably 30 minutes to 1 hour).
[0172]
In this embodiment, heat treatment is performed at 950 ° C. for 30 minutes in an atmosphere containing 3 to 10% by volume of hydrogen chloride with respect to the oxygen atmosphere.
[0173]
By this step, nickel in the crystalline silicon film becomes volatile nickel chloride and is released into the processing atmosphere. That is, nickel can be removed by the gettering action of the halogen element. However, if the concentration of nickel present in the crystalline silicon film is too high, there arises a problem that oxidation proceeds abnormally at the segregated portion of nickel. Therefore, it is necessary to reduce the concentration of nickel used in the crystallization stage as much as possible.
[0174]
In addition, the structure of a present Example can be freely combined with any structure of Examples 1-8.
[0175]
Example 10
In this embodiment, a case where the CMOS circuit and the pixel portion shown in Embodiment 1 are different in structure will be described. Specifically, an example is shown in which the arrangement of the LDD regions is varied according to the specifications required by the circuit.
[0176]
Since the basic structure of the CMOS circuit and the pixel portion has already been shown in FIG. 1, in the present embodiment, only necessary portions will be described with reference numerals. The TFT structure of this embodiment can be basically referred to the manufacturing method of Embodiment 1.
[0177]
First, the circuit shown in FIG. 12A is characterized in that the LDD region 31 of the NTFT is provided in contact with only the drain region 33 side of the channel formation region 32 in the CMOS circuit. This structure can be realized by hiding the source region side with a resist mask.
[0178]
Since the CMOS circuit used in the drive circuit portion is required to operate at high speed, it is necessary to eliminate as much as possible the resistance component that can cause the operation speed to decrease. However, since the LDD region necessary for increasing the hot carrier resistance acts as a resistance component, the operation speed is sacrificed.
[0179]
However, hot carrier injection occurs at the end of the channel formation region on the drain region side, and if there is an LDD region overlapping with the gate wiring in that portion, a countermeasure against hot carriers is sufficient. Therefore, it is not always necessary to provide an LDD region more than necessary at the end of the channel formation region on the source region side.
[0180]
Note that the structure of FIG. 12A cannot be applied to the case of operation like a pixel TFT in which a source region and a drain region are interchanged. In the case of a CMOS circuit, since the source region and the drain region are usually fixed, a structure as shown in FIG. 12A can be realized.
[0181]
Next, the circuit shown in FIG. 12B is an example of a CMOS circuit in which the NTFT has a double gate structure and the PTFT has a single gate structure. Such a structure is used for a drive circuit portion (typically a buffer circuit or a sampling circuit) that is required to have a high breakdown voltage.
[0182]
In this case, the LDD regions 34a and 34b of the NTFT are provided only on the drain region 36 side (or the side close to the drain region 36) of each of the channel forming regions 35a and 35b.
[0183]
With such a structure, the resistance component due to the LDD region on the source region side is eliminated, and the double gate structure has an effect of dispersing and relaxing the electric field applied between the source and the drain.
[0184]
In addition, the structure of a present Example can be freely combined with any structure of Examples 1-9.
[0185]
Example 11
In the first embodiment, providing a light shielding film under the TFT (specifically, under the active layer) as necessary is effective in suppressing leakage current due to photoexcitation. In particular, it is effective to provide the pixel TFT under the pixel TFT which needs to suppress the leakage current (or off-current) as much as possible.
[0186]
As the light-shielding film, a metal film, a black resin film, or the like can be used. When a metal film is used, a storage capacitor can be formed between the light-shielding film and the active layer using the metal film. Is possible. In this case, since the net two storage capacitors are connected in parallel, a sufficient storage capacitor can be secured.
[0187]
In addition, the structure of a present Example can be freely combined with any structure of Examples 1-10.
[0188]
Example 12
The present embodiment provides a technique for improving the adhesion between the light shielding film and the second interlayer insulating film (resin film) thereunder in the pixel portion shown in the first embodiment. FIG. 13 is used for the description.
[0189]
In this embodiment, after forming the second interlayer insulating film 41 made of an acrylic film, a silicon oxide film having a thickness of 10 to 30 nm is formed by sputtering, and a high-purity aluminum film is continuously formed. This is collectively etched to form a light shielding film. In FIG. 13, 42 is a silicon oxide film, and 43 is a high-purity aluminum film.
[0190]
The silicon oxide film 42 functions as a buffer layer that enhances adhesion between the second interlayer insulating film 41 made of an acrylic film and the light shielding film 43 made of a high-purity aluminum film. By providing this silicon oxide film 42, good adhesion can be ensured even when the oxide 44 is formed by an anodic oxidation method or the like.
[0191]
In addition, the structure of a present Example can be freely combined with any structure of Examples 1-11.
[0192]
Example 13
In this embodiment, an example in which the structure of the storage capacitor is different from that in FIG. 1 will be described. 14A and 14B are used for the description.
[0193]
In FIG. 14A, first, the state of FIG. 5A is obtained according to the steps of the first embodiment. Next, a third interlayer insulating film 51 made of a resin film (an acrylic film in this embodiment) is formed, and openings 52a and 52b are formed. The formation of the openings 52a and 52b exposes the light shielding film 250 (strictly, the oxide 251 on the surface thereof). At this time, a contact hole 53 is also formed at the same time.
[0194]
Thereafter, a pixel electrode 54 made of an ITO film is formed. Thus, in the openings 52 a and 52 b, a storage capacitor is formed by the light shielding film 250, the light shielding film oxide 251, and the pixel electrode 54. With such a structure, it is not necessary for the pixel electrode 54 to get over the end portion of the light shielding film 250, so that it is possible to prevent the occurrence of problems such as a short circuit at the end portion.
[0195]
In FIG. 14B, first, the steps up to the step of FIG. 5A (however, before the oxide 251 is formed) are performed according to the steps of the first embodiment. That is, the process is performed until the light shielding film 250 made of an aluminum film is formed on the second interlayer insulating film 249.
[0196]
Next, a third interlayer insulating film 55 made of an acrylic film is formed, and openings 56a and 56b are formed. At this time, a contact hole 57 is simultaneously formed.
[0197]
In this state, the oxide 58 is formed on the exposed surface of the light shielding film 250. In this embodiment, the oxide 58 is formed by an anodic oxidation method, but a thermal oxidation method or a plasma oxidation method may be used.
[0198]
After the oxide 58 is formed on a part of the surface (upper surface) of the light shielding film 250, a pixel electrode 59 made of an ITO film is formed next. Thus, in the openings 56 a and 56 b, a storage capacitor is formed by the light shielding film 250, the light shielding film oxide 58, and the pixel electrode 59. Even in such a structure, as in FIG. 14A, a short circuit of the pixel electrode at the end of the light shielding film can be prevented.
[0199]
In addition, the structure of a present Example can be freely combined with any structure of Examples 1-12.
[0200]
Example 14
In this embodiment, a structure of a pixel portion formed using the present invention will be described with reference to FIG. Since the basic cross-sectional structure has already been described with reference to FIGS. 1 to 5, the description will be made by paying attention to the positional relationship between the light-shielding film and the pixel electrode (position where the storage capacitor is formed).
[0201]
First, the state of FIG. 15A is a state in which the steps shown in FIG. Reference numeral 61 denotes an active layer, 62 a gate wiring, 63 a source wiring, 64 a contact portion between the active layer and the source wiring, 65 a drain wiring (drain electrode), and 66 a contact portion between the active layer and the drain wiring.
[0202]
Next, the state of FIG. 15B is a state in which the steps up to the step shown in FIG. Further, this state shows a state in which the light shielding film 67 and the pixel electrode 68 are overlapped in FIG. Note that the pixel electrode 68 is partially represented by a dotted line in order to clarify the positional relationship with the underlying light shielding film.
[0203]
As shown in FIG. 15B, the pixel electrode 68 is formed so as to overlap the light shielding film 67 at the outer peripheral portion of the image display area 69. A region 70 where the pixel electrode 68 and the light shielding film 67 overlap functions as a storage capacitor.
[0204]
Reference numeral 71 denotes a contact portion between the drain wiring 65 and the pixel electrode 68. Although the light shielding film 67 cannot be provided on the contact portion 71, the light is not incident on the TFT because the drain wiring 65 completely shields the light.
[0205]
The advantage of the structure of this embodiment is that the aperture ratio of the pixel can be increased because it is not necessary to separately form a wiring for forming a capacitor. Since the storage capacitor 70 is formed on the source wiring 63 and the gate wiring 62, it does not substantially reduce the aperture ratio. Therefore, the image display area 69 can be maximized and a bright image can be obtained.
[0206]
In addition, the structure of a present Example can be freely combined with any structure of Examples 1-13.
[0207]
Example 15
In this embodiment, an example in which a crystalline silicon film is formed by means different from that in Embodiment 1 will be described.
[0208]
In Example 1, a catalytic element (nickel) was used for crystallization of an amorphous semiconductor film (specifically, an amorphous silicon film). However, in this example, thermal crystallization was performed without using a catalytic element. Will be described.
[0209]
In this embodiment, after the amorphous silicon film is formed, heat treatment is performed at a temperature of 580 to 640 ° C. (typically 600 ° C.) for 12 to 30 hours (typically 16 to 24 hours). Crystallize to obtain a crystalline silicon film. Therefore, the gettering step as shown in the first embodiment can be omitted.
[0210]
Thus, if the structure of the present invention can be realized, it is easy to combine a process using a crystalline silicon film called so-called high-temperature polysilicon with the present invention.
[0211]
In addition, the structure of a present Example can be freely combined with any Example of Examples 1-7, 9-14.
[0212]
Example 16
In this embodiment, an example in which the first interlayer insulating film is formed by a method different from that in Embodiment 1 will be described. FIG. 16 is used for the description.
[0213]
First, the process up to the activation process shown in FIG. Note that in this embodiment, a silicon oxynitride film having a thickness of 70 nm (here, referred to as a silicon oxynitride film (A) 1601) is used as the silicon oxynitride film 240. When the activation step is completed, a silicon oxynitride film (B) 1602 having a thickness of 600 nm to 1 μm (800 nm in this embodiment) is formed thereon. Further, a resist mask 1603 is formed thereon. (FIG. 16 (A))
[0214]
Note that the silicon oxynitride film (A) 1601 and the silicon oxynitride film (B) 1602 have different composition ratios of nitrogen, oxygen, hydrogen, and silicon. The silicon oxynitride film (A) 1601 is 7% nitrogen, 59% oxygen, 2% hydrogen, and 32% silicon. The silicon oxynitride film (B) 1602 is 33% nitrogen, 15% oxygen, 23% hydrogen, Silicon is 29%. Of course, it is not limited to this composition ratio.
[0215]
Further, since the resist mask 1603 is thick, the surface undulation of the silicon oxynitride film (B) 1602 can be completely planarized.
[0216]
Next, the resist mask 1603 and the silicon oxynitride film (B) 1602 are etched by a dry etching method using a mixed gas of carbon tetrafluoride and oxygen. In the case of this embodiment, the etching rates of the silicon oxynitride film (B) 1602 and the resist mask 1603 are substantially equal in dry etching using a mixed gas of carbon tetrafluoride and oxygen.
[0217]
In this etching step, the resist mask 1603 is completely removed as shown in FIG. 16B, and a part of the silicon oxynitride film (B) 1602 (in this embodiment, from the surface to a depth of 300 nm) is etched. As a result, the flatness of the surface of the resist mask 1603 is directly reflected in the flatness of the etched silicon oxynitride film (B).
[0218]
Thus, the first interlayer insulating film 1604 having extremely high flatness is obtained. In this embodiment, the thickness of the first interlayer insulating film 1604 is 500 nm. For the subsequent steps, the manufacturing steps of Embodiment 1 may be referred to.
[0219]
In addition, the structure of a present Example can be freely combined with any Example of Examples 1-15.
[0220]
Example 17
Various known liquid crystal materials can be used for the AM-LCD manufactured according to the present invention. Examples of such a material include TN liquid crystal, PDLC (polymer dispersion type liquid crystal), FLC (ferroelectric liquid crystal), AFLC (anti-ferroelectric liquid crystal), or a mixture of FLC and AFLC.
[0221]
For example, `` H.Furue et al.; Characteristics and Drivng Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability, SID, 1998 '', `` T.Yoshida et al.; A Full- The materials disclosed in “Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time, 841, SID97DIGEST, 1997” or US Pat. No. 5,594,569 can be used.
[0222]
In particular, when a thresholdless antiferroelectric liquid crystal (Thresholdless Antiferroelectric LCD) is used, since the operating voltage of the liquid crystal is about ± 2.5V, the power supply voltage is about 5-8V. That is, the driver circuit portion and the pixel portion can be operated with the same power supply voltage, and the power consumption of the entire AM-LCD can be reduced.
[0223]
Further, the ferroelectric liquid crystal and the antiferroelectric liquid crystal have an advantage that the response speed is faster than that of the TN liquid crystal. The conventional TFT did not make use of this advantage. However, when a TFT having a crystal structure as described in Example 1 is used, a TFT having a very high operating speed is realized. It is possible to realize an AM-LCD having a high image response speed by making full use of the response speed of the liquid crystal.
[0224]
Needless to say, it is effective to use the AM-LCD of this embodiment as a display unit of an electric appliance such as a personal computer.
[0225]
Moreover, the structure of a present Example can be freely combined with any structure of Examples 1-16.
[0226]
Example 18
The present invention can also be used when an interlayer insulating film is formed on a conventional MOSFET and a TFT is formed thereon. That is, it is also possible to realize a three-dimensional semiconductor device in which a reflective AM-LCD is formed on a semiconductor circuit.
[0227]
The semiconductor circuit may be formed on an SOI substrate such as SIMOX, Smart-Cut (registered trademark of SOITEC), ELTRAN (registered trademark of Canon Inc.), or the like.
[0228]
In implementing this embodiment, any of the configurations of Embodiments 1 to 17 may be combined.
[0229]
Example 19
The present invention can also be applied to an active matrix EL (electroluminescence) display (also referred to as an EL display device). An example is shown in FIG.
[0230]
FIG. 17 is a circuit diagram of an active matrix EL display. Reference numeral 81 denotes a display area, and an X direction (gate side) drive circuit 82 and a Y direction (source side) drive circuit 83 are provided around the display area. Each pixel in the display area 81 includes a switching TFT 84, a capacitor 85, a current control TFT 86, and an EL element 87. The switching TFT 84 includes an X-direction signal line (gate signal line) 88a (or 88b) and a Y-direction. A signal line (source signal line) 89a (or 89b, 89c) is connected. Further, power supply lines 90 a and 90 b are connected to the current control TFT 86.
[0231]
In the active matrix EL display of this embodiment, the gate insulating films of TFTs used for the X direction driving circuit 82 and the Y direction driving circuit 83 are thinner than the gate insulating films of the switching TFT 84 and the current control TFT 86. . Further, the capacitor 85 is formed with the holding capacity of the present invention.
[0232]
In addition, you may combine any structure of Examples 1-16, 18 with respect to the active matrix type EL display of a present Example.
[0233]
Example 20
In this example, an example in which an EL (electroluminescence) display device is manufactured using the present invention will be described. 18A is a top view of the EL display device of the present invention, and FIG. 18B is a cross-sectional view thereof.
[0234]
In FIG. 18A, reference numeral 4001 denotes a substrate, 4002 denotes a pixel portion, 4003 denotes a source side driver circuit, 4004 denotes a gate side driver circuit, and each driver circuit reaches an FPC (flexible printed circuit) 4006 through a wiring 4005. Connected to an external device.
[0235]
At this time, a first sealant 4101, a cover material 4102, a filler 4103, and a second sealant 4104 are provided so as to surround the pixel portion 4002, the source side driver circuit 4003, and the gate side driver circuit 4004.
[0236]
FIG. 18B corresponds to a cross-sectional view taken along line AA ′ of FIG. 18A. A driving TFT included in the source side driver circuit 4003 on the substrate 4001 (here, an n-channel type is used here). TFTs and p-channel TFTs are shown.) 4201 and a current control TFT (TFT for controlling current to the EL element) 4202 included in the pixel portion 4002 are formed.
[0237]
In this embodiment, a TFT having the same structure as that of the driving circuit portion in FIG. 1 is used as the driving TFT 4201, and a TFT having the same structure as that of the pixel portion in FIG. 1 is used as the current control TFT 4202. The pixel portion 4002 is provided with a storage capacitor (corresponding to the capacitor 85 in FIG. 17) connected to the gate of the current control TFT 4202, and this storage capacitor (not shown) is shown in FIG. A storage capacitor having the same structure as the storage capacitor 254 shown is used.
[0238]
An interlayer insulating film (planarization film) 4301 made of a resin material is formed on the driving TFT 4201 and the pixel TFT 4202, and a pixel electrode (anode) 4302 electrically connected to the drain of the pixel TFT 4202 is formed thereon. As the pixel electrode 4302, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used.
[0239]
An insulating film 4303 is formed over the pixel electrode 4302, and an opening is formed in the insulating film 4303 over the pixel electrode 4302. In this opening, an EL (electroluminescence) layer 4304 is formed on the pixel electrode 4302. A known organic EL material or inorganic EL material can be used for the EL layer 4304. The organic EL material includes a low molecular (monomer) material and a high molecular (polymer) material, either of which may be used.
[0240]
A known technique may be used for forming the EL layer 4304. The EL layer may have a stacked structure or a single layer structure by freely combining a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer.
[0241]
Over the EL layer 4304, a cathode 4305 made of a light-shielding conductive film (typically a conductive film containing aluminum, copper, or silver as its main component or a stacked film of these with another conductive film) is formed. . In addition, it is preferable to remove moisture and oxygen present at the interface between the cathode 4305 and the EL layer 4304 as much as possible. Therefore, it is necessary to devise such that the both are continuously formed in a vacuum or the EL layer 4304 is formed in a nitrogen or rare gas atmosphere and the cathode 4305 is formed without being exposed to oxygen or moisture. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus.
[0242]
The cathode 4305 is electrically connected to the wiring 4005 in a region indicated by 4306. A wiring 4005 is a wiring for applying a predetermined voltage to the cathode 4305 and is electrically connected to the FPC 4006 through a conductive material 4307.
[0243]
As described above, an EL element including the pixel electrode (anode) 4302, the EL layer 4304, and the cathode 4305 is formed. The EL element is surrounded by a first sealing material 4101 and a cover material 4102 bonded to the substrate 4001 by the first sealing material 4101 and enclosed by a filler 4103.
[0244]
As the cover material 4102, a glass plate, a metal plate (typically a stainless steel plate), a ceramic plate, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film is used. be able to. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.
[0245]
However, when the emission direction of light from the EL element is directed toward the cover material, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.
[0246]
As the filler 4103, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) is used. Can be used. When a hygroscopic substance (preferably barium oxide) is provided inside the filler 4103, deterioration of the EL element can be suppressed.
[0247]
Further, the filler 4103 may contain a spacer. At this time, if the spacer is formed of barium oxide, the spacer itself can be hygroscopic. In the case where a spacer is provided, it is also effective to provide a resin film on the anode 4305 as a buffer layer that relieves pressure from the spacer.
[0248]
The wiring 4005 is electrically connected to the FPC 4006 through a conductive material 4305. The wiring 4005 transmits a signal transmitted to the pixel portion 4002, the source side driver circuit 4003, and the gate side driver circuit 4004 to the FPC 4006, and is electrically connected to an external device by the FPC 4006.
[0249]
In this embodiment, the second sealing material 4104 is provided so as to cover the exposed portion of the first sealing material 4101 and a part of the FPC 4006, and the EL element is thoroughly shielded from the outside air. Thus, an EL display device having the cross-sectional structure of FIG. Note that the EL display device of this embodiment may be manufactured by combining any of the configurations of Embodiments 1 to 16 and 18.
[0250]
Example 21
In this embodiment, examples of a pixel structure that can be used for the pixel portion of the EL display device shown in Embodiment 20 are shown in FIGS. In this embodiment, 4401 is a source wiring of the switching TFT 4402, 4403 is a gate wiring of the switching TFT 4402, 4404 is a current control TFT, 4405 is a capacitor, 4406 and 4408 are current supply lines, and 4407 is an EL element. .
[0251]
FIG. 19A shows an example in which the current supply line 4406 is shared between two pixels. That is, there is a feature in that two pixels are formed so as to be symmetrical with respect to the current supply line 4406. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.
[0252]
FIG. 19B illustrates an example in which the current supply line 4408 is provided in parallel with the gate wiring 4403. Note that in FIG. 19B, the current supply line 4408 and the gate wiring 4403 are provided so as not to overlap with each other. However, if the wirings are formed in different layers, they overlap with each other through an insulating film. It can also be provided. In this case, since the exclusive area can be shared by the power supply line 4408 and the gate wiring 4403, the pixel portion can be further refined.
[0253]
19C, the current supply line 4408 is provided in parallel with the gate wiring 4403 similarly to the structure of FIG. 19B, and two pixels are symmetrical with respect to the current supply line 4408. It is characterized in that it is formed. It is also effective to provide the current supply line 4408 so as to overlap with any one of the gate wirings 4403. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.
[0254]
[Example 22]
The electro-optical device and the semiconductor circuit of the present invention can be used as a display unit or a signal processing circuit of an electric appliance. Such electric appliances include video cameras, digital cameras, projectors, projection TVs, goggles type displays (head mounted displays), navigation systems, sound playback devices, notebook personal computers, game machines, portable information terminals (mobile computers, Mobile phones, portable game machines, electronic books, etc.), image playback devices equipped with recording media, and the like. Specific examples of these electric appliances are shown in FIGS.
[0255]
FIG. 20A illustrates a mobile phone, which includes a main body 2001, an audio output unit 2002, an audio input unit 2003, a display unit 2004, operation switches 2005, and an antenna 2006. The electro-optical device of the present invention can be used for the display portion 2004, and the semiconductor circuit of the present invention can be used for the sound output portion 2002, the sound input portion 2003, or a CPU or memory.
[0256]
FIG. 20B illustrates a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The electro-optical device of the present invention can be used for the display portion 2102, and the semiconductor circuit of the present invention can be used for the audio input portion 2103, CPU, memory, or the like.
[0257]
FIG. 20C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display unit 2205. The electro-optical device of the present invention can be used for the display portion 2205, and the semiconductor circuit of the present invention can be used for a CPU, a memory, or the like.
[0258]
FIG. 20D illustrates a goggle type display which includes a main body 2301, a display portion 2302, and an arm portion 2303. The electro-optical device of the present invention can be used for the display portion 2302, and the semiconductor circuit of the present invention can be used for a CPU, a memory, or the like.
[0259]
FIG. 20E shows a rear projector (projection TV), which includes a main body 2401, a light source 2402, a liquid crystal display device 2403, a polarization beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be used for the liquid crystal display device 2403, and the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.
[0260]
FIG. 20F illustrates a front projector which includes a main body 2501, a light source 2502, a liquid crystal display device 2503, an optical system 2504, and a screen 2505. The present invention can be used for the liquid crystal display device 2502, and the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.
[0261]
FIG. 21A illustrates a personal computer, which includes a main body 2601, a video input portion 2602, a display portion 2603, a keyboard 2604, and the like. The electro-optical device of the present invention can be used for the display portion 2603, and the semiconductor circuit of the present invention can be used for a CPU, a memory, or the like.
[0262]
FIG. 21B illustrates an electronic game machine (game machine), which includes a main body 2701, a recording medium 2702, a display portion 2703, and a controller 2704. Audio and video output from the electronic gaming machine are reproduced on a display including a housing 2705 and a display unit 2706. As a communication means between the controller 2704 and the main body 2701 or a communication means between the electronic gaming machine and the display, wired communication, wireless communication or optical communication can be used. In this embodiment, infrared rays are detected by the sensor units 2707 and 2708. The electro-optical device of the present invention can be used for the display portions 2703 and 2706, and the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.
[0263]
FIG. 21C shows a player (image playback apparatus) that uses a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. Including. Note that this image reproducing apparatus uses a DVD (Digital Versatile Disc), a CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The electro-optical device of the present invention can be used for the display portion 2802, a CPU, a memory, and the like.
[0264]
FIG. 21D shows a digital camera, which includes a main body 2901, a display portion 2902, an eyepiece portion 2903, operation switches 2904, and an image receiving portion (not shown). The electro-optical device of the present invention can be used for the display portion 2902, a CPU, a memory, and the like.
[0265]
A detailed description of an optical engine that can be used in the rear projector of FIG. 20E and the front projector of FIG. 20F is shown in FIG. 22A shows an optical engine, and FIG. 22B shows a light source optical system built in the optical engine.
[0266]
The optical engine shown in FIG. 22A includes a light source optical system 3001, mirrors 3002, 3005 to 3007, dichroic mirrors 3003 and 3004, optical lenses 3008a to 3008c, a prism 3011, a liquid crystal display device 3010, and a projection optical system 3012. The projection optical system 3012 is an optical system that includes a projection lens. In this embodiment, an example of a three-plate type using three liquid crystal display devices 3010 is shown, but a single-plate type may be used. In addition, an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, or the like may be provided in an optical path indicated by an arrow in FIG.
[0267]
As shown in FIG. 22B, the light source optical system 3001 includes light sources 3013 and 3014, a combining prism 3015, collimator lenses 3016 and 3020, lens arrays 3017 and 3018, and a polarization conversion element 3019. Note that the light source optical system illustrated in FIG. 22B uses two light sources, but may be one, or may be three or more. Further, an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, or the like may be provided somewhere in the optical path of the light source optical system.
[0268]
As described above, the application range of the present invention is extremely wide and can be applied to electric appliances in various fields. Moreover, the electric appliance of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-21.
[0269]
【The invention's effect】
By using the present invention, TFTs having gate insulating films with different thicknesses can be formed over the same substrate. Therefore, in a semiconductor device including an electronic device typified by an AM-LCD and an electric appliance having such an electronic device as a display unit (display display), a circuit having an appropriate performance is arranged according to the specifications required by the circuit. Therefore, the performance and reliability of the semiconductor device can be greatly improved.
[0270]
In addition, in a pixel portion of an electronic device typified by AM-LCD, a storage capacitor having a small area and a large capacity can be formed. Therefore, even in an electronic device having a display portion with a diagonal of 1 inch or less, a sufficient storage capacity can be secured without reducing the aperture ratio.
[Brief description of the drawings]
FIG. 1 shows a cross-sectional structure of an AM-LCD.
FIGS. 2A and 2B are diagrams illustrating a manufacturing process of an AM-LCD. FIGS.
3A and 3B are diagrams illustrating a manufacturing process of an AM-LCD.
4A and 4B are diagrams illustrating a manufacturing process of an AM-LCD.
FIGS. 5A and 5B are diagrams illustrating a manufacturing process of an AM-LCD. FIGS.
FIG. 6 is a graph showing the relationship of concentration distribution when an impurity element is added.
FIG. 7 is a diagram showing a structure of a common potential dropping terminal portion.
FIG. 8 is a diagram showing a structure of a common potential dropping terminal portion.
FIG. 9 is a diagram showing a block configuration and circuit arrangement of an AM-LCD.
FIG. 10 is a diagram showing a structure of a driving TFT (CMOS circuit).
FIG. 11 is a diagram showing an external appearance of an AM-LCD.
FIG. 12 is a diagram showing a cross-sectional structure of a CMOS circuit.
FIG. 13 shows a cross-sectional structure of a pixel portion.
FIG 14 illustrates a cross-sectional structure of a pixel portion.
FIG. 15 is a diagram showing a top structure of a pixel portion.
FIGS. 16A and 16B are diagrams illustrating a manufacturing process of an AM-LCD. FIGS.
FIG. 17 is a diagram showing a circuit configuration of an active matrix EL display.
18A and 18B are a top view and a cross-sectional view of an EL display device.
FIG 19 illustrates a structure of a pixel portion of an EL display device.
FIG. 20 is a diagram showing an example of an electric appliance.
FIG. 21 is a diagram showing an example of an electric appliance.
FIG. 22 is a diagram showing the structure of an optical engine.

Claims (6)

A method for manufacturing a semiconductor device including a pixel portion and a driver circuit portion over the same substrate,
Forming a first semiconductor layer for forming a pixel TFT and a second semiconductor layer for forming a driving TFT on the substrate;
Forming a gate insulating film on the first and second semiconductor layers;
Forming a first gate wiring on the second semiconductor layer;
Using the first gate wiring as a mask, an element belonging to Group 15 of the periodic table is added to the second semiconductor layer to form an impurity region,
A first low-concentration impurity region is formed under the first gate wiring by diffusing elements belonging to the group 15 included in the impurity region by heat treatment;
Forming a second gate wiring on the first semiconductor layer;
Using the second gate wiring as a mask, adding an element belonging to Group 15 of the periodic table to the first semiconductor layer to form the second low-concentration impurity region,
Forming a resist mask covering a portion of the second low-concentration impurity region;
Using the resist mask and the first gate wiring as a mask, an element belonging to Group 15 of the periodic table is added to the end of the first semiconductor layer and the second semiconductor layer to form a high concentration impurity region. ,
An interlayer insulating film is formed to cover the driving TFT and the pixel TFT,
Forming a light shielding film on the interlayer insulating film;
Forming an oxide of the light shielding film on the surface of the light shielding film;
A method for manufacturing a semiconductor device, comprising forming a pixel electrode over an oxide of the light-shielding film. A method for manufacturing a semiconductor device including a pixel portion and a driver circuit portion over the same substrate,
On the substrate, a first semiconductor layer for forming a pixel TFT and a second semiconductor layer for forming a driving TFT including NTFT and PTFT are formed.
Forming a first gate insulating film on the first semiconductor layer;
Forming a second gate insulating film having a thickness smaller than that of the first gate insulating film on the second semiconductor layer;
Forming a conductive film covering the first and second semiconductor layers and the first and second gate insulating films;
Patterning the conductive film to form a gate wiring of the NTFT on the second semiconductor layer;
Using the gate wiring of the NTFT as a mask, an element belonging to Group 15 of the periodic table is added to the region of the second semiconductor layer where the NTFT is formed, thereby forming an impurity region,
A first low-concentration impurity region is formed under the gate wiring of the NTFT by diffusing elements belonging to the group 15 included in the impurity region by heat treatment;
Patterning the conductive film to form a gate wiring of the pixel TFT on the first semiconductor layer;
Using the gate wiring of the pixel TFT as a mask, an element belonging to Group 15 of the periodic table is added to the first semiconductor layer to form the second low-concentration impurity region,
Forming a resist mask covering a portion of the second low-concentration impurity region;
Using the resist mask and the gate wiring of the NTFT as a mask, an element belonging to Group 15 of the periodic table is added to an end portion of the first semiconductor layer and a region where the NTFT of the second semiconductor layer is formed. 1 high-concentration impurity region is formed,
Patterning the conductive film to form a gate wiring of the PTFT on the second semiconductor layer;
Using the gate wiring of the PTFT as a mask, an element belonging to Group 13 of the periodic table is added to a region of the second semiconductor layer where the PTFT is formed, thereby forming a second high concentration impurity region,
An interlayer insulating film is formed to cover the driving TFT and the pixel TFT,
Forming a light shielding film on the interlayer insulating film;
Forming an oxide of the light shielding film on the surface of the light shielding film;
A method for manufacturing a semiconductor device, comprising forming a pixel electrode over an oxide of the light-shielding film. In claim 1 or claim 2,
The method for manufacturing a semiconductor device, wherein the interlayer insulating film is a resin film. In any one of Claim 1 thru | or 3,
The method for manufacturing a semiconductor device, wherein the light shielding film is an aluminum film or a film containing aluminum as a main component. In any one of Claims 1 thru | or 4,
The method for manufacturing a semiconductor device, wherein the oxide is an alumina film, and the alumina film is formed by an anodic oxidation method, a plasma oxidation method, or a thermal oxidation method. In any one of Claims 1 thru | or 5,
Forming a second interlayer insulating film covering an end portion of the oxide of the light shielding film on the oxide of the light shielding film;
The method of manufacturing a semiconductor device, wherein the pixel electrode is formed on the oxide of the light shielding film and the second interlayer insulating film.

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