JP2003005672A - Substrate device, electro-optical device and electronic equipment - Google Patents

Abstract

(57) [Problem] To provide an electro-optical device such as a liquid crystal device with improved light resistance so that a bright and high-quality image can be displayed. An electro-optical device includes a TFT array substrate (1).
0), a pixel electrode (9a) and a TF connected to the pixel electrode (9a).
T (30) and a scanning line (3a) and a data line (6a) connected thereto. A relay layer (71) connected to the pixel electrode and forming a storage capacitor (70);
The capacitor line (3) including a fixed-potential-side capacitor electrode which is opposed to the capacitor electrode via a dielectric film (75) and forms a storage capacitor.
00). Each of the relay layer and the capacitance line includes a metal, and also functions as a light shielding film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate device suitable for use in an electro-optical device such as a liquid crystal device of an active matrix driving system, the electro-optical device, and a technical field of an electronic apparatus including the electro-optical device. Thin film transistor for pixel switching (Thin Film Transisto
r: appropriately referred to as TFT hereinafter) belongs to the technical field of a substrate device of the type provided in a laminated structure on a substrate.

[0002]

2. Description of the Related Art In an electro-optical device of a TFT active matrix driving type, when a channel region of a pixel switching TFT provided in each pixel is irradiated with incident light, a light leak current is generated due to excitation by light and the TFT characteristics. Changes. Particularly in the case of an electro-optical device for a light valve of a projector, since the intensity of incident light is high, it is important to shield the incident light from the channel region of the TFT and its peripheral region. Therefore, conventionally, a light-shielding film which defines an opening area of each pixel provided on the counter substrate, or TF is used.
On the T-array substrate, while passing over the TFT,
The data line formed of a metal film such as l (aluminum) is configured to shield the channel region and its peripheral region from light. Further, a light-shielding film made of, for example, a refractory metal may be provided at a position facing the lower side of the TFT on the TFT array substrate. If a light-shielding film is also provided on the lower side of the TFT in this way, it is possible to use the light reflected from the back surface from the TFT array substrate side or to combine a plurality of electro-optical devices via a prism or the like to form one optical system. It is possible to prevent return light such as projection light that passes through the prism from the electro-optical device, from entering the TFT of the electro-optical device.

On the other hand, in this type of electro-optical device, when the TFT is turned on, the voltage of the image signal applied to the pixel electrode via the TFT is much longer than the time during which the TFT is turned on. It is composed of, for example, a pixel potential side capacitance electrode connected to the drain electrode of the TFT or a pixel electrode so as to be held for a long time, and a fixed potential side capacitance electrode which is arranged to face the pixel potential side capacitance electrode via a dielectric film. The technology of creating a storage capacitor in each pixel is also becoming popular.

[0004]

However, when the storage capacitor is formed in the laminated structure on the substrate, the pixel potential side capacitance electrode and the pixel electrode or TFT are opened in the laminated structure. The need generally arises to connect via. Therefore, the light-shielding film or the data line between the TFT and the pixel electrode, which is connected by the contact hole, is formed avoiding the contact hole, so that the light-shielding performance is deteriorated in the contact hole and its periphery. Dots occur. That is, the incident light incident on the contact hole and its periphery reaches the channel region of the TFT and its peripheral region without being shielded by the light shielding film or the data line, and the characteristics of the TFT are changed or deteriorated. However, there is a problem that it causes flicker.

The present invention has been made in view of the above problems, and is a substrate device having excellent light resistance and capable of displaying a high-quality image, an electro-optical device including the substrate device, and the electro-optical device. It is an object to provide an electronic device including a device.

[0006]

In order to solve the above-mentioned problems, a substrate device of the present invention has a pixel electrode, a thin film transistor connected to the pixel electrode, a scanning line connected to the thin film transistor, and a scanning line on the substrate. A data line, a pixel potential side capacitance electrode which is connected to the pixel electrode and constitutes a storage capacitance, and a fixed potential which is arranged to face the pixel potential side capacitance electrode via a dielectric film and constitutes the storage capacitance. And a capacitance line including a side capacitance electrode, wherein the pixel potential side capacitance electrode and the fixed potential side capacitance electrode each include a metal.

According to the substrate device of the present invention, by supplying the scanning signal and the image signal to the thin film transistor through the scanning line and the data line, the pixel electrode can be driven in the active matrix. Here, since the pixel electrode is connected to the storage capacitor in which the pixel potential side capacitance electrode and the fixed potential side capacitance electrode are arranged so as to face each other, the voltage of the image signal written in the pixel electrode is maintained for a long period of time. Can hold And in particular, the pixel potential side capacitance electrode and the fixed potential side capacitance electrode are respectively
Since it contains a metal, both or one of them is used as a low-resistance capacitance electrode, and the dielectric constant of the dielectric film interposed between them is increased, so that the area on the substrate is limited. It becomes possible to construct a relatively large storage capacity. At the same time, the pixel potential side capacitance electrode and the fixed potential side capacitance electrode are respectively
Since metal is included, it is possible to improve the light shielding performance of shielding the thin film transistor by providing both or one of the capacitor electrodes with a light shielding function. By using the two capacitor electrodes that form the storage capacitor as a light-shielding film containing metal in this way, it is possible to prevent incident light from reaching the channel region of the thin film transistor and its peripheral region. It is possible to effectively prevent the occurrence of flicker due to the change in characteristics.

As a result of the above, according to the substrate device of the present invention, it is possible to display a high quality image.

In one aspect of the substrate device of the present invention, the pixel potential side capacitance electrode is connected to the pixel electrode through a contact hole, and the capacitance line is provided with the contact hole in plan view. A notch is provided so as to avoid, and each of the pixel potential side capacitance electrode and the fixed potential side capacitance electrode includes a light-shielding metal film.

According to this aspect, the capacitance line is provided with the cutout portion so as to avoid the contact hole for connecting the pixel potential side capacitance electrode and the pixel electrode. Therefore, the light-shielding performance of the capacitance line or the capacitance electrode on the fixed potential side included in the capacitance line is inevitably deteriorated in the contact hole and its periphery. However, the pixel-potential-side capacitance electrode arranged so as to face this includes a light-shielding metal film. For this reason, the pixel potential side capacitance electrode portion to which the contact hole is connected also functions as a light-shielding film, so that the light-shielding performance is not inferior even if it is in the contact hole or its periphery.

In another aspect of the substrate device of the present invention, the pixel potential side capacitance electrode is connected to the thin film transistor through a contact hole, and the capacitance line avoids the contact hole in plan view. Thus, the pixel potential side capacitance electrode and the fixed potential side capacitance electrode each include a light-shielding metal film.

According to this aspect, the capacitance line is provided with a notch so as to avoid a contact hole for connecting the pixel potential side capacitance electrode and the thin film transistor. Therefore, the light-shielding performance of the capacitance line or the capacitance electrode on the fixed potential side included in the capacitance line is inevitably deteriorated in the contact hole and its periphery. However, the pixel-potential-side capacitance electrode arranged so as to face this includes a light-shielding metal film. For this reason, the pixel potential side capacitance electrode portion to which the contact hole is connected also functions as a light-shielding film, so that the light-shielding performance is not inferior even if it is in the contact hole or its periphery.

In another aspect of the substrate device of the present invention, on the substrate, the fixed potential side capacitance electrode is formed on the pixel potential side capacitance electrode via the dielectric film.

According to this aspect, the pixel potential side capacitance electrode, the dielectric film and the fixed potential side capacitance electrode are laminated in this order on the substrate, and these two capacitance electrodes also function as a light shielding film. As a result, high light-shielding performance for the channel region and its peripheral region can be obtained and the storage capacitance can be increased. In particular, in the contact hole for connecting the pixel potential side capacitance electrode to the pixel electrode and in the vicinity thereof, a structure can be obtained in which the fixed potential side capacitance electrode is used as a light shielding film to enhance the light shielding performance.

In another aspect of the substrate device of the present invention, the fixed potential side capacitance electrode is formed on the substrate below the pixel potential side capacitance electrode via the dielectric film.

According to this aspect, the fixed potential side capacitance electrode, the dielectric film and the pixel potential side capacitance electrode are laminated in this order on the substrate, and these two capacitance electrodes also function as a light shielding film. As a result, high light-shielding performance for the channel region and its peripheral region can be obtained and the storage capacitance can be increased. In particular, in the contact hole for connecting the pixel potential side capacitance electrode to the thin film transistor and its periphery, a structure for enhancing the light shielding performance by using the fixed potential side capacitance electrode as a light shielding film can be obtained.

In another aspect of the substrate device of the present invention,
The electric film is made of TaOx, BST ((Ba, Sr) TiO 3₃), PZT
(Pb (Zr, Ti) O₃), TiO_Two, ZrO_Two, HfO_Two, S
iO _TwoAt least one of SiON, SiON and SiN
It becomes.

According to this aspect, TaOx, BST, P
ZT, TiO_Two, ZrO_Two, HfO _TwoSuch as high dielectric constant
Limited substrate by using material as dielectric film
A large storage capacity can be built in the upper area. Furthermore, Si
O_TwoMaterials such as SiON, SiON and SiN
When used as a dielectric film, it does not contain silicon.
The same conductive film, semiconductor film, and insulating film
It is possible to build a storage capacity while reducing the occurrence of pressure.

In another aspect of the substrate device of the present invention, the pixel potential side capacitance electrode and the fixed potential side capacitance electrode are respectively
Pt, Ru, TiN, TaN, SRO (SrRuO ₃ ) and A
At least one of l is included.

According to this aspect, Pt, Ru, TiN,
The metal film containing at least one of TaN, SRO and Al can improve the light shielding performance.

In another aspect of the substrate device of the present invention, the pixel potential side capacitance electrode contains Pt, and the fixed potential side capacitance electrode contains Al.

According to this aspect, the pixel-potential-side capacitance electrode containing Pt and the fixed-potential-side capacitance electrode containing Al can surely enhance the light-shielding performance and stably increase the storage capacitance. Becomes

Alternatively, in another aspect of the substrate device of the present invention,
The pixel potential side capacitance electrode contains TiN, and the fixed potential side capacitance electrode contains Al.

According to this aspect, the pixel-potential-side capacitance electrode containing TiN and the fixed-potential-side capacitance electrode containing Al can surely enhance the light-shielding performance and stably increase the storage capacitance. Becomes

In another aspect of the substrate device of the present invention, at least one of the pixel potential side capacitance electrode and the fixed potential side capacitance electrode is formed of a laminated body.

According to this aspect, for example, by forming both or one of the two capacitance electrodes from a laminated body including a normal metal, a refractory metal, a silicide, a Si film, a SiGe (silicon germanium) film and the like. In addition, the light-shielding performance can be improved and the storage capacity can be increased, and the degree of freedom in manufacturing the device can be increased.

In another aspect of the substrate device of the present invention, the pixel potential side capacitive electrode is formed of the laminated body, the laminated body includes an Al film and an AlN film, and the pixel electrode is made of ITO.
The pixel electrode on the pixel potential side is connected to the pixel electrode by electrically contacting the AlN film with the pixel electrode.

According to this aspect, a very good ohmic contact can be obtained between the portion of the pixel potential side capacitive electrode made of the AlN film and the pixel electrode made of ITO. If A
Even if the I film and the ITO film are brought into contact with each other, a potential barrier is generated and ohmic contact cannot be obtained.

In another aspect of the substrate device of the present invention, the laminated body includes a light absorbing layer containing silicon and a light shielding layer containing metal.

According to this aspect, the light-shielding layer containing metal reflects or absorbs light to enhance the basic light-shielding performance of the capacitor electrode made of the laminate, and the light-absorbing layer containing silicon absorbs light. By doing so, it is possible to suppress the generation of inner reflected light or multiple reflected light due to reflection of incident light or return light on the surface of the laminate.

In this aspect, the light absorption layer may be the same layer as the semiconductor layer forming the thin film transistor.

According to this aspect, since the light absorption layer is made of the same layer as the semiconductor layer forming the thin film transistor, the manufacturing process on the substrate and the laminated structure can be simplified. Such a light absorption layer is, for example, a conductive polysilicon film, amorphous silicon, single crystal silicon, SiG.
e material layer or the like.

In another aspect of the substrate device of the present invention, a non-opening region in each pixel is defined by at least one of the pixel potential side capacitance electrode and the capacitance line and the data line.

According to this aspect, the non-opening region in each pixel is defined by the data line and / or one or both of the pixel potential side capacitive electrode and the capacitive line existing in the laminated structure on the substrate. The channel region can be shielded at a position relatively close to the thin film transistor.

In this aspect, a lower light-shielding film that covers at least the channel region of the thin film transistor from the lower side is further provided on the substrate, and the lower light-shielding film is planarly viewed as compared with the non-opening region. The contour may be small.

According to this structure, the return light can be shielded by the lower light shielding film. In particular, since the lower light-shielding film has a smaller contour than the non-opening region, oblique incident light from the upper side passes through the pixel potential side capacitance electrode, the capacitance line, or the data line, and the upper surface of the lower light-shielding film. The possibility of being reflected by can be reduced. As a result, it is possible to effectively prevent the light reflected by the upper surface of the lower light-shielding film from reaching the channel region as inner surface reflected light or multiple reflected light.

In order to solve the above-mentioned problems, the electro-optical device of the present invention has an electro-optical substance sandwiched between the above-mentioned substrate device of the present invention (including its various aspects) and another substrate. Become.

According to the electro-optical device of the present invention, since the substrate device described above is provided, flicker and the like are reduced by the stable operation of the thin film transistor even in a use environment in which strong incident light is incident. Cage,
Furthermore, the relatively large storage capacity enables high-quality image display.

According to the electronic apparatus of the present invention, since it is equipped with the above-described electro-optical device of the present invention, it is possible to display a bright and high-quality image, a projection type display device, a liquid crystal television, a mobile phone, an electronic notebook, a word processor. Various electronic devices such as a viewfinder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized.

The operation and other advantages of the present invention will be apparent from the embodiments described below.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The following embodiments apply the electro-optical device of the present invention to a liquid crystal device.

(First Embodiment) First, the structure of the pixel portion of the electro-optical device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels that are formed in a matrix and form an image display area of an electro-optical device. FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, etc. are formed. FIG. 3 is a sectional view taken along the line AA ′ of FIG. Further, FIG. 4 is a schematic partial perspective view showing a state of light shielding in the contact hole for connecting the pixel potential side capacitance electrode to the pixel electrode and its periphery in the present embodiment, and FIG.
FIG. 6 is a schematic partial perspective view showing a state of light shielding in a contact hole for connecting the pixel potential side capacitance electrode to the pixel electrode and its periphery in a comparative example, and FIG. 6 is an MIM (Metal) of the storage capacitor in the present embodiment. Insulator Me
FIG. 3 is a schematic partial cross-sectional view showing a tal) structure. Incidentally, FIG.
Also, in FIG. 6, in order to make each layer and each member recognizable in the drawing, the scale is different for each layer and each member.

In FIG. 1, a pixel electrode 9a and a TFT 30 for switching control of the pixel electrode 9a are respectively provided in a plurality of pixels formed in a matrix form the image display area of the electro-optical device according to the present embodiment. Are formed, and the data line 6a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2, ..., Sn to be written to the data line 6a may be line-sequentially supplied in this order, or may be supplied to each of a plurality of adjacent data lines 6a in groups. good. In addition, the scanning line 3 is connected to the gate of the TFT 30.
a is electrically connected, and the scanning signals G1, G2, ..., Gm are pulsed to the scanning line 3a at a predetermined timing.
Is applied line-sequentially in this order.
The pixel electrode 9a is electrically connected to the drain of the TFT 30, and by closing the switch of the TFT 30 which is a switching element for a certain period, the data line 6
The image signals S1, S2, ..., Sn supplied from a are written at a predetermined timing. The image signals S1, S2, ..., Sn having a predetermined level written in the liquid crystal as an example of the electro-optical material via the pixel electrode 9a are held for a certain period of time with the counter electrode formed on the counter substrate described later. It The liquid crystal modulates light by changing the orientation and order of the molecular assembly depending on the applied voltage level, and enables gradation display. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in each pixel unit, and in the normally black mode, the incident light is incident according to the voltage applied in each pixel unit. The transmittance for light is increased, and light having a contrast corresponding to the image signal is emitted from the electro-optical device as a whole. Here, in order to prevent the held image signal from leaking, the pixel electrode 9a
A storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the counter electrode and the counter electrode.

In FIG. 2, a plurality of transparent pixel electrodes 9 are arranged in a matrix on the TFT array substrate of the electro-optical device.
a (the outline is shown by the dotted line portion 9a '), and the data line 6a and the scanning line 3a are provided along the vertical and horizontal boundaries of the pixel electrode 9a.

Further, the scanning line 3a is arranged so as to oppose the channel region 1a 'shown by the diagonally-upper right region in the semiconductor layer 1a, and the scanning line 3a functions as a gate electrode. That is, the scanning lines 3a and the data lines 6a intersect with each other at the intersections of the channel regions 1a '.
A TFT 30 for pixel switching is provided in which the main line portion of a is arranged as a gate electrode so as to face each other.

As shown in FIGS. 2 and 3, the storage capacitor 70
Is a relay layer 7 as a pixel potential side capacitance electrode connected to the high-concentration drain region 1e of the TFT 30 and the pixel electrode 9a.
1 and a part of the capacitance line 300 as a fixed potential side capacitance electrode are formed by being opposed to each other with the dielectric film 75 interposed therebetween.

Particularly in this embodiment, the storage capacitor 70 is M
It has an IM structure. The configuration and the effect of this MIM structure relating to the storage capacitor will be described in detail with reference to FIGS. 4 to 6 in addition to FIGS. 2 and 3.

As shown in FIGS. 3, 4 and 6, in the present embodiment, the relay layer 71, which constitutes an example of the pixel potential side capacitive electrode, is made of a conductive film containing metal and has a fixed potential side. The capacitance line 300, which constitutes an example of the capacitance electrode, is made of a conductive film containing a metal, and the MIM structure is constructed on the first interlayer insulating film 41 so that the dielectric film 75 is sandwiched therebetween. There is.

Relay layer 71 for constructing these MIM structures
The capacitance line 300 is made of metal such as Pt, Ru, and T.
The conductive film is made of at least one of iN, TaN, SRO and Al and has a film thickness of about several tens to several thousands nm. Therefore, the relay layer 71 and the capacitance line 300 respectively function as a light-shielding film having excellent light-shielding performance.
Along with the data line 6a made of the Al film or the like shown in FIG. 5, the upper light-shielding film having a grid-like planar shape in the electro-optical device is constructed. More specifically, for example, the relay layer 71
Includes Pt, and the capacitance line 300 includes Al. Alternatively, the relay layer 71 includes TiN and the capacitance line 300 includes Al. With such a combination, it is possible to surely improve the light-shielding performance and stably increase the storage capacity. At this time, the film thickness of each metal film may be set to a value that is individually and specifically sufficient to obtain sufficient light-shielding performance in consideration of the intensity of incident light, device specifications, and the like. in addition,
The capacitance line 300 located on the upper side on the TFT array substrate 10
Is formed from an Al film having an extremely high reflectance, and the relay layer 71 located on the lower side is formed from a Pt film or a TiN film whose reflectance is about a fraction of that of the Al film. By reflecting the incident light incident from the upper side by the upper capacitance line 300, it is possible to reduce the generation of the internal reflection light and the multiple reflection light.

The dielectric film 75 of the storage capacitor 70 is made of TaOx, which is relatively thin and has a film thickness of, for example, about 5 to 200 nm.
BST, PZT, TiO ₂ , ZrO ₂ , HfO ₂ , Si
It is made of an insulating film containing at least one of O ₂ , SiON and SiN. Especially TaOx, BST, PZ
By using a high dielectric constant material such as T, TiO ₂ , ZrO ₂ , or HfO ₂ as the dielectric film 75, the capacitance value can be increased in a limited area on the substrate. Alternatively, SiO ₂ , S
By using a material containing silicon such as iON or SiN for the dielectric film 75, it is possible to reduce stress generation between the semiconductor layer 1a containing silicon and the interlayer insulating film such as the first interlayer insulating film 41. Incidentally, the dielectric film 75
As for HTO (High Temperature Oxide) film, LT
It may be formed from a silicon oxide film such as an O (Low Temperature Oxide) film or a silicon nitride film. In any case, from the viewpoint of increasing the storage capacitance 70, the thinner the dielectric film 75 is, the better, and the higher the dielectric constant is, the better as long as the reliability of the film is sufficiently obtained.

Therefore, according to this embodiment, a relatively large capacitance value can be realized by the storage capacitor 70 of the MIM structure in which two low-resistance capacitance electrodes sandwich a high-dielectric-constant dielectric film. It is possible to improve the light shielding performance according to

That is, as shown in FIG. 4, the incident light L0 perpendicular to the substrate surface and the incident light L1 oblique to the substrate surface are almost equal to the capacitance line 3
The light is blocked by 00. Then, even if the incident light L2 is incident on the cutout portion of the capacitance line 300 provided so as to avoid the contact hole 85 connecting the pixel electrode 9a and the relay layer 71, it is connected to the contact hole 85. The light is shielded by the relay layer 71 made of a light shielding film.

As shown in FIG. 5 (comparative example), if the relay layer 71 ′ is formed of a transparent or semitransparent, for example, conductive polysilicon film, it is provided so as to avoid the contact hole 85. When the incident light L2 is incident on the cutout portion of the capacitance line 300, it is transmitted through the relay layer 71 and finally reaches the channel region 1a ′ of the TFT 30 or a region adjacent to the channel region 1a ′. As a result, the transistor characteristics of the TFT 30 change or deteriorate, and image quality deterioration such as flicker occurs.

As can be seen from FIGS. 4 and 5, the MIM structure of this embodiment exhibits excellent light-shielding performance especially when the contact hole 85 is provided.

In the present embodiment, the capacitance line 300 is above the relay layer 71, but even when the capacitance line is below the relay layer, the contact hole connecting the relay layer and the high-concentration drain region is formed. In order to avoid this, a cutout portion needs to be provided in the capacitance line. Therefore, also in this case, the MIM structure can similarly enhance the light shielding performance in the contact hole and its periphery.

In addition, the capacitance line 300 extends in stripes along the scanning line 3a when seen in a plan view (see FIG. 2), and the portion overlapping the TFT 30 projects vertically in FIG. The data lines 6a extending in the vertical direction in FIG.
2 and the capacitance lines 300 extending in the horizontal direction in FIG. 2 are formed so as to intersect each other, so that the upper light-shielding film (embedded light-shielding film) on the TFT array substrate 10 on the upper side of the TFT 30 in a lattice shape in plan view. Is defined, and defines the opening area of each pixel.

Further, the capacitance line 300 extends from the image display region where the pixel electrode 9a is arranged to the periphery thereof and is electrically connected to the constant potential source to have a fixed potential. As the constant potential source, a scanning line driving circuit described later for supplying a scanning signal for driving the TFT 30 to the scanning line 3a and a data line driving described later for controlling a sampling circuit supplying an image signal to the data line 6a. A constant potential source such as a positive power source or a negative power source supplied to the circuit may be used, or the counter electrode 21 of the counter substrate 20 may be used.
It may be a constant potential supplied to.

On the other hand, the relay layer 71 has the pixel electrode 9a and the high-concentration drain region 1e in addition to the function as the pixel potential side capacitance electrode of the storage capacitor 70 and the light shielding function as described above.
It also has a function of relay connection through the contact holes 83 and 85. Even if the interlayer distance is long, for example, about 2000 nm, the relay connection by the relay layer 71 avoids the technical difficulty of connecting the two via a single contact hole, and two or more series contacts having a relatively small diameter. The holes can be well connected to each other, the pixel aperture ratio can be increased, and it is also useful for preventing the penetration of etching when the contact holes are opened.

Returning to FIGS. 2 and 3, the lower light-shielding film 1 is provided below the TFT 30 on the TFT array substrate 10.
1a are provided in a grid pattern. The lower light-shielding film 11a is
Like the capacitance line 300 or the relay layer 71 described above, it is made of various conductive light-shielding films containing metal. Preferably, it is a film that can withstand a high temperature process when forming the TFT 30 after forming the lower light-shielding film 11a, for example, Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), Mo ( Molybdenum), Pb (lead), etc., at least one of refractory metals, simple metal, alloy,
It is made of metal silicide, polysilicide, or a stack of these.

Therefore, in this embodiment, the lower light-shielding film 11a having a relatively small interlayer distance, the capacitance line 300, as described above,
Since a configuration in which the semiconductor layer 1a is sandwiched between the relay layer 71 and the lattice-shaped upper light-shielding film formed of the data lines 6a is obtained, basically a very high light-shielding performance is obtained against incident light and return light. In addition, as shown in FIGS. 4 and 5, high light shielding performance is obtained also in the contact hole 85 and its periphery.

As for the lower light-shielding film 11a, the potential variation of the TFT 3 is similar to that of the capacitance line 300 described above.
In order to avoid adversely affecting 0, it is preferable to extend from the image display area to its periphery and connect it to a constant potential source.

2 and 3, the electro-optical device is
It is provided with a transparent TFT array substrate 10 and a transparent counter substrate 20 arranged to face it. The TFT array substrate 10 is made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate.

As shown in FIG. 3, the TFT array substrate 10
Is provided with a pixel electrode 9a, and on the upper side thereof,
Alignment film 16 subjected to a predetermined alignment treatment such as rubbing treatment
Is provided. The pixel electrode 9a is formed of, for example, ITO (In
dium Tin Oxide) film or other transparent conductive film. The alignment film 16 is made of, for example, an organic film such as a polyimide film.

On the other hand, the counter substrate 20 is provided with a counter electrode 21 over the entire surface thereof, and an alignment film 22 subjected to a predetermined alignment treatment such as rubbing treatment is provided below the counter electrode 21. There is. The counter electrode 21 is made of, for example, a transparent conductive film such as an ITO film. The alignment film 22 is made of an organic film such as a polyimide film.

The counter substrate 20 may be provided with a lattice-shaped or stripe-shaped light-shielding film. By adopting such a configuration, as described above, the light shielding film on the counter substrate 20 together with the capacitance line 300, the relay layer 71, and the data line 6a forming the lattice-shaped upper light shielding film causes the incident light from the counter substrate 20 side. Light is channel region 1a 'and low concentration source region 1b
In addition, it is possible to more reliably prevent the low concentration drain region 1c from entering. Further, such a light-shielding film on the counter substrate 20 functions to prevent the temperature of the electro-optical device from rising by forming at least the surface irradiated with incident light with a highly reflective film. In this way, the light-shielding film on the counter substrate 20 is preferably formed so as to be located inside the light-shielding layer formed of the capacitance line 300 and the data line 6a in plan view. As a result, the light shielding film on the counter substrate 20 can provide such an effect of light shielding and temperature rise prevention without lowering the aperture ratio of each pixel.

Between the TFT array substrate 10 and the counter substrate 20 arranged in such a manner that the pixel electrode 9a and the counter electrode 21 face each other, a space surrounded by a sealing material described later is provided. A liquid crystal, which is an example of an electro-optical material, is encapsulated to form a liquid crystal layer 50. The liquid crystal layer 50 is formed on the alignment film 1 in a state where the electric field from the pixel electrode 9a is not applied.
A predetermined alignment state is obtained by 6 and 22. Liquid crystal layer 50
Is composed of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed. The sealing material is used for bonding the TFT array substrate 10 and the counter substrate 20 around their periphery,
For example, it is an adhesive made of a photocurable resin or a thermosetting resin, and a gap material such as glass fiber or glass beads for mixing the distance between both substrates to a predetermined value is mixed.

Further, a base insulating film 12 is provided below the pixel switching TFT 30. Base insulating film 1
2 has a function of insulating the TFT 30 from the lower light-shielding film 11a between layers, and is formed on the entire surface of the TFT array substrate 10, so that the surface of the TFT array substrate 10 is roughened during polishing, and remains after cleaning. Pixel switching T
It has a function of preventing deterioration of the characteristics of the FT 30.

In FIG. 3, a pixel switching TFT
Reference numeral 30 denotes an LDD (Lightly Doped Drain) structure, and the scanning line 3a and the channel region 1 of the semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a.
a ′, an insulating film 2 including a gate insulating film that insulates the scanning line 3a from the semiconductor layer 1a, a low-concentration source region 1b and a low-concentration drain region 1c of the semiconductor layer 1a, a high-concentration source region 1d of the semiconductor layer 1a, and a high-concentration source region 1d. It has a concentration drain region 1e.

On the scanning line 3a, the high concentration source region 1d is formed.
A first interlayer insulating film 41 is formed in which a contact hole 81 leading to and a contact hole 83 leading to the high-concentration drain region 1e are opened.

A relay layer 71 and a capacitor line 300 are formed on the first interlayer insulating film 41, and a contact hole 81 and a contact hole 85 which lead to the high-concentration source region 1d and the relay layer 71, respectively, are formed thereon. To form a second interlayer insulating film 42.

In this embodiment, the first interlayer insulating film 41 is used.
On the other hand, by firing at about 1000 ° C., the ions implanted into the polysilicon film forming the semiconductor layer 1a and the scanning line 3a may be activated. On the other hand, the second interlayer insulating film 42 may be subjected to no such firing to reduce the stress generated near the interface of the capacitance line 300.

The data line 6a is formed on the second interlayer insulating film 42, and the third interlayer insulating film 43 in which the contact hole 85 leading to the relay layer 71 is formed thereon.
Are formed. The pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 43 thus configured.

In this embodiment, the data lines 6a on the lower ground of the pixel electrode 9a (that is, the surface of the third interlayer insulating film 43) are formed by stacking a large number of conductive layers having a predetermined pattern as shown in FIG. Also, the occurrence of a step in the region along the scan line 3a is alleviated by the flattening process of the surface of the third interlayer insulating film 43. For example, CMP (Chemical Mec
It is alleviated by polishing by hanical polishing or the like, or by flattening using organic SOG (Spin On Glass). In this way, by mitigating the step difference between the region where the wiring, the element and the like are present and the region where it is not present, the image defect such as the liquid crystal alignment defect due to the step difference can be finally reduced. However, in place of or in addition to performing the flattening process on the third interlayer insulating film 43 as described above, among the TFT array substrate 10, the base insulating film 12, the first interlayer insulating film 41, and the second interlayer insulating film 42. A flattening process may be performed by digging a groove in at least one and embedding the wiring such as the data line 6a, the TFT 30, and the like.

As described above with reference to FIGS. 1 to 6, according to the electro-optical device of the present embodiment, by constructing the storage capacitor 70 having the MIM structure, comparison is made in a limited area on the substrate. A large capacitance value can be obtained and high light-shielding performance can be realized. Finally, an active matrix driving method using a TFT 30 having excellent transistor characteristics while using strong incident light enables high-quality image display. Become.

In the embodiment described above, the pixel switching TFT 30 preferably has the LDD structure as shown in FIG. 3, but the low concentration source region 1b and the low concentration drain region 1c are implanted with impurities. A non-offset structure may be used, or a high-concentration impurity may be implanted using the gate electrode formed of a part of the scanning line 3a as a mask.
It may be a self-aligned TFT that forms the high-concentration source and drain regions in a self-aligned manner. Further, in the present embodiment, the single gate structure in which only one gate electrode of the pixel switching TFT 30 is arranged between the high-concentration source region 1d and the high-concentration drain region 1e has two or more gate electrodes between them. You may arrange. In this way, TF is more than dual gate or triple gate
By configuring T, it is possible to prevent the leak current at the junction between the channel and the source and drain regions, and to reduce the off-time current.

(Second Embodiment) Next, an electro-optical device according to a second embodiment of the present invention will be described with reference to FIG. FIG. 7 is a schematic partial cross-sectional view showing the laminated structure of the storage capacitors in the second embodiment.

As shown in FIG. 7, in the second embodiment, the capacitance line 300 including the fixed potential side capacitance electrode is formed by the Al film 300b.
Is sandwiched by TiN films 300a and 300c from both sides. For other configurations, the above-mentioned first
This is similar to the case of the embodiment.

Therefore, according to the second embodiment, the Al film 30 is used.
0b reduces the resistance of the capacitance line 300, while Ti
The N films 300a and 300c can enhance the light shielding performance. In particular, the TiN film has a reflectance of a fraction of that of the Al film. Therefore, by adopting the configuration of this embodiment, the internal reflection light and the multiple reflection light caused by the incident light and the return light are generated. Can be prevented.

In the second embodiment, the capacitance line 300 is
The capacitor line 300 is composed of a laminated body in which the Al film is sandwiched by the TiN film, but the capacitive line 300 may be composed of a laminated body containing a normal metal, a refractory metal, a silicide, a Si film, a SiGe film, or the like.
Instead of or in addition to the capacitance line 300, the relay layer 71 may be composed of such a laminated body. Of these, particularly, if a laminated body including a SiGe film having a small band gap is used,
This SiGe film provides a relatively strong light absorbing action.

(Third Embodiment) Next, an electro-optical device according to a third embodiment of the present invention will be described with reference to FIG. FIG. 8 is a schematic partial cross-sectional view showing the laminated structure of the storage capacitor in the third embodiment.

As shown in FIG. 8, in the third embodiment, the capacitance line 300 including the capacitance electrode on the fixed potential side has the TiN film 300.
It is composed of a laminated body in which an Al film 300e is laminated on d. Further, the relay layer 71 is made of a laminated body in which the Pt film 71b is laminated on the conductive polysilicon film 71a. Other configurations are similar to those of the above-described first embodiment.

Therefore, according to the third embodiment, the Al film 30 is used.
0e reduces the resistance of the capacitance line 300 and reduces Ti.
The N film 300d can enhance the light blocking performance of the capacitance line 300. In particular, the TiN film has a reflectance of a fraction of that of the Al film. Therefore, by adopting the configuration of the present embodiment, the internal reflection of the returning light or the light traveling upward in the drawing is particularly effective. Generation of light or multiple reflection light can be prevented to some extent. On the other hand, the Pt film 71b makes it possible to reduce the resistance of the relay layer 71 and improve its light shielding performance. Furthermore,
The conductive polysilicon film 71a lowers the resistance of the relay layer 71, and at the same time, due to the light absorbing action of the polysilicon film 71a, the internal reflection light related to the returning light or the light traveling upward in the drawing, Generation of multiple reflected light can be significantly prevented. Incidentally, such a polysilicon film 7
If 1a is made of the same film as the semiconductor layer 1a, the manufacturing process on the substrate and the laminated structure can be simplified.

In the third embodiment, the polysilicon film 71a is used as the light absorption layer forming the laminated body of the relay layer 71, but instead of this, amorphous silicon, single crystal silicon, a SiGe material layer or the like is used as a relay. A laminated body of the layers 71 may be configured, or the light absorption layer may be arranged on the upper side in FIG. 8 of the laminated body of the relay layers 71.

(Fourth Embodiment) Next, an electro-optical device according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a schematic partial cross-sectional view showing the laminated structure of the storage capacitors in the third embodiment. Incidentally, FIG. 9 shows a laminated structure of the storage capacitor particularly in the vicinity of the contact hole 85.

As shown in FIG. 9, in the fourth embodiment, the relay layer 71 is made of a laminated body in which the AlN film 71d is laminated on the Al film 71c. Other configurations are similar to those of the above-described first embodiment.

Therefore, according to the fourth embodiment, good ohmic contact can be obtained between the pixel electrode 9a made of the ITO film and the relay layer 71 made of the AlN film, which are in contact with each other through the contact hole 85. Moreover, like this, Al
Good light-shielding performance can be obtained by the relay layer 71 made of a laminated body including the film 71c and the AlN film 71d.

In the fourth embodiment, the pixel electrode 9a is set to I
AlN that is formed from a TO film and can make ohmic contact with it
Although the pixel potential side capacitance electrode 71 is formed of a film, if the pixel electrode is formed of an IZO (Indium Zinc Oxide) film, A
An ohmic contact with the l-film is obtained.

Particularly in the first to fourth embodiments described above, the non-opening region in each pixel is defined by the upper light-shielding film formed of the capacitance line 300, the relay layer 71, and the data line 6a. Therefore, the channel region 1a ′ can be shielded at a position relatively close to the TF 30, and the shielding performance can be improved and the shielding film can be improved as compared with the case where the shielding film formed on the counter substrate 20 shields light. It is almost unnecessary to widen the non-opening area in consideration of the positional deviation and the dimensional deviation.

In the first to fourth embodiments described above, as shown in FIG.
The grid-shaped upper light-shielding film composed of the data lines 6a, the capacitance lines 300, and the relay layer 71 has a larger contour than the lattice-shaped lower light-shielding film 11a, and the lower light-shielding film 11a is more than the scanning line 3a including the gate electrode. Larger contours are preferred. According to this structure, it is possible to reduce the component of the light incident from above that passes through the side of the upper light-shielding film and is reflected on the upper surface of the lower light-shielding film 11a. The reflected light can be reduced as much as possible. On the other hand, the lower light-shielding film 11a
Has a contour larger than that of the scanning line 3a, so that of the light incident from below, it passes through the side of the lower light-shielding film 11a and scans the scanning line 3a.
The component incident on the can be reduced as much as possible.

As a modification, in the first to fourth embodiments described above, as shown in FIG.
Instead of the lattice-shaped lower light-shielding film 11a, a stripe-shaped lower light-shielding film 11b along the scanning line 3a may be formed. Also in this case, the data line 6a, the capacitance line 300, and the relay layer 7
It is preferable that the lattice-shaped upper light-shielding film made of 1 has a larger contour than the lower light-shielding film 11b, and the lower light-shielding film 11b has a larger contour than the scanning line 3a including the gate electrode. According to this structure, it is possible to reduce the component of the light incident from above that passes through the side of the upper light-shielding film and is reflected on the upper surface of the lower light-shielding film 11a, and of the light incident from below, the lower light-shielding film. The component that passes through the side of 11a and enters the scanning line 3a can be reduced as much as possible.

(Manufacturing Process) Next, a manufacturing process of the electro-optical device according to the first embodiment described above will be described with reference to FIGS. 11 and 12. Here, FIG. 11 and FIG.
4A to 4C are process diagrams sequentially showing the laminated structure of the electro-optical device in each step of the manufacturing process in a portion related to the vicinity of the semiconductor layer 1a in the cross-sectional view of FIG.

First, as shown in step (1) of FIG. 11, a TFT array substrate 10 such as a quartz substrate, a hard glass or a silicon substrate is prepared. Here, preferably N ₂ (nitrogen)
Annealing is performed in an inert gas atmosphere such as the above, and at a high temperature of about 900 to 1300 ° C., and pretreatment is performed so as to reduce strain generated in the TFT array substrate 10 in a high temperature process performed later.

Then, a metal such as Ti, Cr, W, Ta, Mo and Pd or a metal alloy film such as metal silicide is sputtered on the entire surface of the thus processed TFT array substrate 10 by sputtering to a thickness of 100 to 500 nm. A light-shielding film having a thickness of about 200 nm, preferably about 200 nm, is formed. Then, the lower light-shielding film 11a having a grid-like planar shape is formed by photolithography and etching.

Next, in step (2), TEOS is formed on the lower light-shielding film 11a by, for example, a normal pressure or low pressure CVD method.
(Tetra-ethyl-ortho-silicate) gas, TEB
(Tetra-ethyl-borate) gas, TMOP (tetra-methyl-oxy-foslate) gas, etc., made of silicate glass film such as NSG, PSG, BSG, BPSG, silicon nitride film, silicon oxide film, etc. The base insulating film 12 is formed. The thickness of the base insulating film 12 is, eg, about 500-2000 nm.

Then, on the base insulating film 12, about 450-
An amorphous silicon film is formed by a low pressure CVD (for example, a CVD at a pressure of about 20 to 40 Pa) using a monosilane gas or a disilane gas at a flow rate of about 400 to 600 cc / min in a relatively low temperature environment of 550 ° C., preferably about 500 ° C. Form. Then, in a nitrogen atmosphere, about 600
The polysilicon film is annealed at about 700 ° C. for about 1 to 10 hours, preferably 4 to 6 hours, so that the polysilicon film has a grain size of about 50 to 200 nm, preferably about 100 nm.
Solid-phase growth is performed until the particle size becomes. As a method for solid phase growth, annealing treatment using RTA (Rapid Thermal Anneal) or laser annealing using an excimer laser or the like may be performed. At this time, depending on whether the pixel switching TFT 30 is an n-channel type or a p-channel type, a dopant of a V group element or a III group element may be slightly doped by ion implantation or the like. And
The semiconductor layer 1a having a predetermined pattern is formed by photolithography and etching.

Subsequently, the semiconductor layer 1 constituting the TFT 30
a at a temperature of about 900 to 1300 ° C., preferably about 100
The lower gate insulating film is formed by thermal oxidation at a temperature of 0 ° C., and then the upper gate insulating film is formed by a low pressure CVD method or the like, or both are continuously performed. An insulating film 2 (including a gate insulating film) made of a film (HTO film) or a silicon nitride film is formed. As a result, the semiconductor layer 1a has a thickness of about 30 to 150.
The thickness of the insulating film 2 is about 20 to 150 nm, preferably about 30 to 100 nm.

Subsequently, the TFT 30 for pixel switching
In order to control the threshold voltage Vth of the semiconductor layer 1a, the N-channel region or the P-channel region of the semiconductor layer 1a is doped with a predetermined amount of a dopant such as boron by ion implantation or the like.

Next, in step (3), a polysilicon film is deposited by a low pressure CVD method or the like, and phosphorus (P) is further thermally diffused to make the polysilicon film conductive. Alternatively, a doped silicon film in which P ions are introduced simultaneously with the formation of this polysilicon film may be used. The thickness of this polysilicon film is about 100 to 500 nm, preferably about 350 nm.
It is about nm. Then, the scanning line 3a having a predetermined pattern including the gate electrode portion of the TFT 30 is formed by photolithography and etching.

For example, the TFT 30 has an LDD structure n
In the case of a channel type TFT, in order to first form the low-concentration source region 1b and the low-concentration drain region 1c in the semiconductor layer 1a, the scanning line 3a (gate electrode) is used as a mask and a dopant of a group V element such as P is used. Is doped at a low concentration (for example, P ions are doped at a dose amount of 1 to 3 × 10 ¹³ / cm ² ). Thereby, the semiconductor layer 1 below the scanning line 3a
a becomes the channel region 1a '. Further, in order to form the high-concentration source region 1d and the high-concentration drain region 1e which form the pixel switching TFT 30, a resist layer having a plane pattern wider than the scanning line 3a is formed on the scanning line 3a. Thereafter, a group V element dopant such as P is added at a high concentration (for example, P ions are added in an amount of 1 to 3 × 10 ¹⁵
/ Cm ² dose). Note that, for example, a TFT having an offset structure may be used without performing low-concentration doping, and a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, etc., using the scanning line 3a as a mask. The doping of the impurities further reduces the resistance of the scanning line 3a.

Next, in the step (4) of FIG. 12, the scanning line 3a
On top of that, for example, TEOS is formed by atmospheric pressure or low pressure CVD
Gas, TEB gas, TMOP gas, etc.
Silicate glass film such as PSG, BSG, BPSG,
A first interlayer insulating film 41 made of a silicon nitride film, a silicon oxide film, or the like is formed. The film thickness of the first interlayer insulating film 41 is, eg, about 500-2000 nm. Here, preferably, annealing is performed at a high temperature of about 800 ° C.,
The film quality of the first interlayer insulating film 41 is improved.

Subsequently, the contact holes 83 are simultaneously opened by dry etching such as reactive ion etching or reactive ion beam etching on the first interlayer insulating film 41.

Subsequently, a metal film of Pt or the like is sputtered on the first interlayer insulating film 41 by sputtering to a thickness of 100 to 500 n.
It is formed to a film thickness of about m. Then, the relay layer 71 having a predetermined pattern is formed by photolithography and etching.

Subsequently, TaO is formed by plasma CVD or the like.
A dielectric film 75 made of an insulating film such as an x film is formed on the relay layer 71. Similar to the case of the insulating film 2, this dielectric film 75 may be composed of either a single layer film or a multilayer film, and is formed by various known techniques generally used for forming a gate insulating film of a TFT. It is possible. Then, the thinner the dielectric film 75, the larger the storage capacitance 70, so that eventually, on the condition that defects such as film breakage do not occur,
It is advantageous to form the dielectric film 75 so as to form an extremely thin insulating film having a film thickness of 50 nm or less.

Subsequently, a metal film of Al or the like is formed on the dielectric film 75 by sputtering to have a film thickness of about 100 to 500 nm. Then, the capacitance line 300 having a predetermined pattern is formed by photolithography and etching. That is, the storage capacitor 70 is completed.

Next, in the step (5), for example, NSG or PS is formed by using a normal pressure or low pressure CVD method or TEOS gas.
A second interlayer insulating film 42 made of a silicate glass film such as G, BSG, BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The film thickness of the first interlayer insulating film 42 is, for example, about 500 to 1500 nm.

Subsequently, the contact hole 81 is opened by dry etching such as reactive ion etching or reactive ion beam etching on the second interlayer insulating film 42.

Then, on the entire surface of the second interlayer insulating film 42,
By sputtering or the like, a low resistance metal such as Al having a light shielding property, a metal silicide, or the like is used as a metal film to form about 100 to 500.
nm thickness, preferably about 300 nm. Then, the data line 6a having a predetermined pattern is formed by photolithography and etching.

Next, in step (6), a silicate glass film such as NSG, PSG, BSG, BPSG, etc. is formed so as to cover the data lines 6a by using, for example, a normal pressure or low pressure CVD method or TEOS gas. A third interlayer insulating film 43 made of a silicon film, a silicon oxide film or the like is formed. The film thickness of the third interlayer insulating film 43 is, for example, about 500 to 1500 nm.

Subsequently, by dry etching such as reactive ion etching or reactive ion beam etching on the third interlayer insulating film 43, a contact hole 85 (not shown) (see FIGS. 2 to 4) is opened.

Then, a transparent conductive film such as an ITO film is formed on the third interlayer insulating film 43 by a sputtering process or the like to have a thickness of about 50.
Deposit ~ 200 nm thick. Then, the pixel electrode 9a is formed by photolithography and etching. When the liquid crystal device is used for a reflective liquid crystal device, the pixel electrode 9a may be formed of an opaque material having a high reflectance such as Al.

Then, after applying a coating liquid of a polyimide-based alignment film on the pixel electrode 9a, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction. 3) is formed.

On the other hand, for the counter substrate 20 shown in FIG. 3, a glass substrate or the like is first prepared, and a light-shielding film as a frame is formed by photolithography and etching after sputtering metallic chromium, for example. Note that these light-shielding films do not need to be conductive, and may be made of Cr, Ni, Al.
In addition to a metal material such as, a material such as resin black in which carbon or Ti is dispersed in a photoresist may be formed.

After that, a transparent conductive film such as ITO is formed on the entire surface of the counter substrate 20 by sputtering or the like to a thickness of about 50 to 20.
The counter electrode 21 is formed by depositing to a thickness of 0 nm. Furthermore, after applying a coating liquid of a polyimide-based alignment film on the entire surface of the counter electrode 21, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction, so that the alignment film 22 (see FIG. 3) is formed. It is formed.

Finally, the T on which each layer was formed as described above.
The FT array substrate 10 and the counter substrate 20 are attached to each other by a sealing material (see FIGS. 13 and 14) so that the alignment films 16 and 22 face each other, and by vacuum suction or the like, for example, a plurality of types are formed in the space between the substrates. The liquid crystal formed by mixing the nematic liquid crystal is sucked to form the liquid crystal layer 50 having a predetermined thickness.

The electro-optical device according to the first embodiment described above can be manufactured by the manufacturing process described above.

On the other hand, in the case of manufacturing the electro-optical device of the second embodiment shown in FIG. 7, in the step (4) of FIG. 12, the capacitance line 300 is sputtered, vacuum evaporated, CV
Lamination may be performed by repeating the D method or the like. When manufacturing the electro-optical device of the third embodiment shown in FIG. 8, in the step (4) of FIG. 12, the relay layer 71 and the capacitance line 300 are respectively sputtered, vacuum evaporated, and CVD.
The layers may be formed by repeating the method or the like. Figure 9
In the case of manufacturing the electro-optical device according to the fourth embodiment illustrated in FIG. 12, in step (4) of FIG. 12, the relay layer 71 is formed by stacking by repeating sputtering, vacuum deposition, CVD method, and the like. Further, in step (6) of FIG.
An IZO film may be formed instead of the TO film.

(Overall Configuration of Electro-Optical Device) The overall configuration of the electro-optical device in each of the above-described embodiments will be described with reference to FIGS. 13 and 14. Incidentally, FIG.
FIG. 14 is a plan view of the TFT array substrate 10 together with the constituent elements formed thereon as viewed from the counter substrate 20 side, and FIG. 14 is a HH ′ cross-sectional view of FIG. 13.

In FIG. 13, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof, and in parallel with the inside thereof, light shielding as a frame for defining the periphery of the image display area 10a. A membrane 53 is provided. In an area outside the sealing material 52, a data line driving circuit 101 for driving the data line 6a by supplying an image signal to the data line 6a at a predetermined timing and an external circuit connecting terminal 102 are provided along one side of the TFT array substrate 10. The scanning line driving circuit 1 that drives the scanning line 3a by supplying the scanning signal to the scanning line 3a at a predetermined timing.
04 are provided along two sides adjacent to this one side. It goes without saying that the scanning line driving circuit 104 may be provided on only one side if the delay of the scanning signal supplied to the scanning line 3a does not matter. In addition, the data line drive circuit 10
1 may be arranged on both sides along the side of the image display area 10a. Further, on the remaining side of the TFT array substrate 10, the scanning line driving circuit 10 provided on both sides of the image display area 10a.
A plurality of wirings 105 for connecting the four are provided. In addition, at least one corner of the counter substrate 20 is provided with a conductive material 106 for electrically connecting the TFT array substrate 10 and the counter substrate 20. Then, as shown in FIG. 14, the counter substrate 20 having substantially the same contour as the sealing material 52 shown in FIG. 13 is fixed to the TFT array substrate 10 by the sealing material 52.

On the TFT array substrate 10, in addition to the data line driving circuit 101, the scanning line driving circuit 104, etc., a sampling circuit for applying an image signal to a plurality of data lines 6a at a predetermined timing, Data line 6a
In addition, a precharge circuit for supplying a precharge signal of a predetermined voltage level prior to the image signal, an inspection circuit for inspecting the quality, defects, etc. of the electro-optical device during manufacturing or shipping may be formed. Good.

In the embodiments described above with reference to FIGS. 1 to 14, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, a TAB (Tape Automated Bonding) substrate is used. The driving LSI mounted on the TFT array substrate 10 may be electrically and mechanically connected via an anisotropic conductive film provided in the peripheral portion of the TFT array substrate 10. Further, for example, TN (Twisted) is provided on the side on which the projection light of the counter substrate 20 is incident and on the side on which the emission light of the TFT array substrate 10 is emitted.
Depending on the operation mode such as Nematic) mode, VA (Vertically Aligned) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, etc. and normally white mode / normally black mode It is arranged in a predetermined direction.

Since the electro-optical device according to the above-described embodiments is applied to a projector, three electro-optical devices are used as RGB light valves, and each light valve has an RGB color separation dichroic. The light of each color separated through the mirror is incident as projection light. Therefore, in each embodiment, the counter substrate 20 is not provided with a color filter. However, an RGB color filter may be formed on the counter substrate 20 in a predetermined region facing the pixel electrode 9a together with its protective film. With this configuration, the electro-optical device according to each embodiment can be applied to a direct-view type or reflective type color electro-optical device other than the projector. Further, microlenses may be formed on the counter substrate 20 so as to correspond to each pixel. Alternatively, it is also possible to form a color filter layer with a color resist or the like under the pixel electrode 9a facing the RGB on the TFT array substrate 10. By doing so, a bright electro-optical device can be realized by improving the efficiency of collecting incident light. Furthermore, the counter substrate 2
A dichroic filter that creates RGB colors may be formed by stacking interference layers having different refractive indexes on the surface of 0 to utilize light interference. With this counter substrate with a dichroic filter, a brighter color electro-optical device can be realized.

(Embodiment of Electronic Equipment) Next, with respect to an embodiment of a projection type color display device as an example of an electronic equipment using the electro-optical device described in detail above as a light valve, its overall configuration, particularly optical The configuration will be described. FIG. 15 is a schematic sectional view of the projection type color display device.

In FIG. 15, a liquid crystal projector 1100 which is an example of the projection type color display device according to the present embodiment.
Prepares three liquid crystal modules including the liquid crystal device 100 in which the driving circuit is mounted on the TFT array substrate.
It is configured as a projector used as the B light valves 100R, 100G, and 100B. In the liquid crystal projector 1100, when the projection light is emitted from the lamp unit 1102 of the white light source such as a metal halide lamp, the three mirrors 1106 and the two dichroic mirrors 1108 cause the light components R, G corresponding to the three primary colors of RGB, It is divided into B and is led to the light valves 100R, 100G and 100B corresponding to the respective colors. At this time, in particular, the B light is
It is guided through a relay lens system 1121 including an entrance lens 1122, a relay lens 1123, and an exit lens 1124. The light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are recombined by the dichroic prism 1112, and then the screen 11 via the projection lens 1114.
20 is projected as a color image.

The present invention is not limited to the above-described embodiments, but can be appropriately modified within the scope of the gist or concept of the invention which can be read from the claims and the entire specification, and such modifications are accompanied. The substrate device and the electro-optical device are also included in the technical scope of the present invention.

[Brief description of drawings]

FIG. 1 is an equivalent circuit of various elements, wirings, etc. provided in a plurality of pixels in a matrix forming an image display area in an electro-optical device according to a first embodiment of the present invention.

FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed in the electro-optical device according to the first embodiment.

FIG. 3 is a sectional view taken along the line AA ′ of FIG. 2 in the first embodiment.

FIG. 4 is a schematic partial perspective view showing how a light is shielded in and around a contact hole that connects the pixel potential side capacitance electrode to the pixel electrode in the first embodiment.

FIG. 5 is a schematic partial perspective view showing a state of light shielding in a contact hole for connecting a pixel potential side capacitance electrode to a pixel electrode and its periphery in a comparative example.

FIG. 6 is an MIM of a storage capacitor according to the first embodiment.
It is a schematic partial sectional view showing a structure.

FIG. 7 is an MIM included in a storage capacitor according to the second embodiment.
It is a schematic partial sectional view showing a structure.

FIG. 8 is an MIM of a storage capacitor according to the third embodiment.
It is a schematic partial sectional view showing a structure.

FIG. 9 is an MIM included in a storage capacitor according to a fourth embodiment.
It is a schematic partial sectional view showing a structure.

FIG. 10 is a plan view showing a preferable size relationship between the upper light-shielding film, the scanning line, and the lower light-shielding film in each embodiment.

FIG. 11 is a process diagram (part 1) sequentially showing the laminated structure of the electro-optical device in each process of the manufacturing process in the first embodiment in a portion related to the semiconductor layer.

FIG. 12 is a process diagram (No. 2) sequentially showing the laminated structure of the electro-optical device in each process of the manufacturing process in the first embodiment in a portion related to the vicinity of the semiconductor layer.

FIG. 13 is a plan view of the TFT array substrate in the electro-optical device according to the embodiment, together with the respective components formed thereon, as viewed from the counter substrate side.

14 is a cross-sectional view taken along the line H-H ′ of FIG.

FIG. 15 is a schematic sectional view showing a color liquid crystal projector which is an example of a projection type color display device which is an embodiment of an electronic apparatus of the invention.

[Explanation of symbols]

1a ... semiconductor layer 1a '... Channel region 1b ... Low concentration source region 1c ... low concentration drain region 1d ... High-concentration source region 1e ... high-concentration drain region 2 ... Insulating film 3a ... scanning line 6a ... Data line 9a ... Pixel electrode 10 ... TFT array substrate 11a ... lower light-shielding film 12 ... Base insulating film 16 ... Alignment film 20 ... Counter substrate 21 ... Counter electrode 22 ... Alignment film 30 ... TFT 50 ... Liquid crystal layer 70 ... Storage capacity 71 ... Relay layer 75 ... Dielectric film 81, 83, 85 ... Contact holes 300 ... Capacitance line

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/336 H01L 29/78 619B 29/786 612Z F term (reference) 2H092 GA29 JA24 JA46 JB22 JB31 JB51 JB61 KB25 MA27 NA25 PA07 RA05 5C094 AA02 AA16 BA03 BA04 BA43 CA19 DA14 DA15 DB04 EA04 EA07 EB02 FB12 FB15 FB16 5F110 AA30 BB01 CC02 DD02 DD03 DD05 DD12 DD13 DD14 DD17 DD25 HL01 HL01 HL04 GG01 GG01 GG01 GG01 GG01 GG01 GG02 GG01 GG01 NN02 NN03 NN04 NN22 NN23 NN24 NN25 NN26 NN35 NN40 NN44 NN46 NN72 PP02 PP03 PP10 QQ04 QQ11 QQ19

Claims (17)

[Claims] 1. A pixel on a substrate, a thin film transistor connected to the pixel electrode, a scanning line and a data line connected to the thin film transistor, and a pixel connected to the pixel electrode to form a storage capacitor. The pixel potential side capacitance electrode, and the capacitance line including the fixed potential side capacitance electrode which is arranged to face the pixel potential side capacitance electrode via a dielectric film and constitutes the storage capacitance. The substrate device, wherein each of the fixed potential side capacitive electrodes includes a metal. 2. The pixel potential side capacitance electrode is connected to the pixel electrode through a contact hole, and the capacitance line is provided with a cutout portion so as to avoid the contact hole when seen in a plan view. 2. The substrate device according to claim 1, wherein the pixel potential side capacitance electrode and the fixed potential side capacitance electrode each include a light-shielding metal film. 3. The pixel potential side capacitance electrode is connected to the thin film transistor through a contact hole, and the capacitance line is provided with a cutout portion so as to avoid the contact hole when seen in a plan view. The substrate device according to claim 1, wherein the pixel potential side capacitance electrode and the fixed potential side capacitance electrode each include a light-shielding metal film. 4. The fixed potential side capacitance electrode is formed on the pixel potential side capacitance electrode on the substrate via the dielectric film. The substrate device according to 1 above. 5. The fixed potential side capacitance electrode is formed on the substrate below the pixel potential side capacitance electrode via the dielectric film. The substrate device according to 1 above. 6. The dielectric film comprises TaOx (tantalum oxide), BST (strontium barium titanate), P
ZT (lead zirconate titanate), TiO ₂ (titanium oxide), ZrO ₂ (zirconium oxide), HfO ₂ (hafnium oxide), SiO ₂ (silicon oxide), SiON
2. At least one of (silicon oxynitride) and SiN (silicon nitride) is contained.
6. The substrate device according to any one of items 5 to 5. 7. The pixel potential side capacitance electrode and the fixed potential side capacitance electrode are respectively Pt (platinum), Ru (ruthenium), TiN (titanium nitride), TaN (tantalum nitride), SRO (strontium ruthenate) and Al
The substrate device according to claim 1, comprising at least one of (aluminum). 8. The substrate device according to claim 7, wherein the pixel-potential-side capacitance electrode contains Pt, and the fixed-potential-side capacitance electrode contains Al. 9. The substrate device according to claim 7, wherein the pixel potential side capacitance electrode includes TiN, and the fixed potential side capacitance electrode includes Al. 10. The substrate device according to claim 1, wherein at least one of the pixel potential side capacitance electrode and the fixed potential side capacitance electrode is formed of a laminated body. 11. The pixel potential side capacitance electrode is formed of the laminated body, the laminated body includes an Al film and an AlN film, and the pixel electrode is formed of ITO (Indium Tin Oxide).
11. The oxide film) according to claim 10, wherein the pixel electrode on the pixel potential side is connected to the pixel electrode by electrically contacting the AlN film with the pixel electrode. Substrate device. 12. The substrate device according to claim 10, wherein the stacked body includes a light absorbing layer containing silicon and a light shielding layer containing metal. 13. The electro-optical device according to claim 12, wherein the light absorption layer is formed of the same layer as a semiconductor layer forming the thin film transistor. 14. The non-opening region in each pixel is defined by at least one of the pixel potential side capacitance electrode and the capacitance line and the data line. The substrate device according to 1 above. 15. A lower light-shielding film that covers at least a channel region of the thin film transistor from below is further provided on the substrate, and the lower light-shielding film has a contour more planar than that of the non-opening region in plan view. 15. It is small in size.
The substrate device according to. 16. An electro-optical device comprising an electro-optical substance sandwiched between the substrate device according to any one of claims 1 to 15 and another substrate. 17. An electronic apparatus comprising the electro-optical device according to claim 16.