JP2006041999A - System and method for transmitting/receiving data - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide data transfer that does not insert weight until the lock of a PLL though a high-speed clock requiring PLL synchronization is used for this invented serial boot system. <P>SOLUTION: An interface clock, data and a clock switching signal are formed between a processor 1 and a serial ROM 2; the interface clock and a low-speed clock created by dividing the frequency of the interface clock by a frequency division circuit 25 can be switched in the processor 1; two sorts of clocks, i.e. a high-speed clock created from the PLL 26 and the low-speed clock created by the frequency division circuit 25, can be similarly switched in the serial ROM 2; and clocks to be inserted into synchronizing circuits 22, 23 in the serial ROM 2 and clocks to be inserted into synchronizing circuits 12, 13 in the processor 1 are simultaneously switched in accordance with whether the PLL 26 in the serial ROM 2 is locked or not, so that data transfer into which weight is not inserted is provided. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data communication method between nodes, and more particularly to a method in which a processor loads a program or the like using a serial interface.

  When a processor loads a program or data from a memory, there is a method using a serial interface consisting of a clock and data as an interface, and this can reduce the number of signal lines, so it is often used in processors with a large number of signal lines. ing.

  In general, a processor uses a serial interface to exchange programs and data with a low clock frequency and a low transfer speed (see, for example, Patent Document 1).

  However, a recent processor uses a high-speed clock to improve the transfer speed (see, for example, Non-Patent Document 1). In this case, an interface circuit with a built-in PLL is added to connect a general-purpose memory. Alternatively, it is necessary to use a memory having an interface with a built-in PLL. This is because the reading of data is in the opposite direction of the clock and data transfer, and if the clock output from the processor is used as it is, sampling may not be possible on the processor side. In other words, when the clock is high-speed, the influence of the clock fluctuation and the delay on the clock when sending data cannot be ignored, so that it is necessary to use a PLL (see, for example, Patent Document 2).

  The conventional method will be described below.

  FIG. 6 shows a general method for loading a program or the like from a memory with a conventional serial interface using a slow clock. Here, 91 is a processor for reading out programs and data, and 92 is a serial ROM for storing programs and data. Reference numerals 93 and 94 denote clock and data which are interface signals between the processor and the serial ROM, respectively. Reference numerals 92 to 97 denote terminals on the serial ROM side. Here, since the clock of the serial interface is sufficiently slow, there is no need to synchronize the clock using a PLL, and the PLL is not described in the figure.

  FIG. 7 shows an example of specific timing of signals in FIG. A clock waveform, a data input waveform, and a data output waveform respectively indicate waveforms at terminals 95, 96, and 97 in FIG.

  Hereinafter, the operation will be described with reference to FIGS. When its own internal clock is stabilized, the processor 91 outputs the clock 93. Next, in synchronization with the fall of this clock, the processor 91 sequentially outputs a start bit indicating the start of address transmission and a memory address read thereafter to the data line 94. The serial ROM 92 receives this at the input terminal 96 and internally samples it using the rising edge of the clock 93 supplied from 91. This is the waveform 96 in FIG.

  When the serial ROM 92 receives the address, the ACK indicating that the address has been received, the data corresponding to the address, and finally the stop bit indicating the completion of data transmission are synchronized with the falling edge of the clock 93 sequentially supplied to the 96 terminals. Output. The processor 91 samples this using the rising edge of the clock 93 and reads the data. This is the waveform 97 in FIG.

  Next, a conventional method of loading from a memory from a processor in a serial interface using a high-speed clock will be described.

  In FIG. 8, reference numeral 100 denotes a processor for reading out programs and data and has a serial interface. Reference numeral 120 denotes a general-purpose ROM for storing programs and data and does not have a serial interface. Therefore, the interface circuit 110 enters the processor 100 and performs interface conversion. The clock is supplied to the processor 100 by a clock oscillator 130, and this clock is supplied to the internal and serial interfaces by using the PLL 104 in the processor 100 as a faster clock. In the processor 100, there are an address synchronization circuit 102, a data synchronization circuit 103, and a processor core 101 for synchronizing addresses and data. The interface circuit 110 receives an interface clock and generates a transmission timing clock from the PLL 113, a synchronization circuit 112 for synchronizing data to be transmitted with the interface clock, and sampling the received address and sending it to the general-purpose ROM 120. There is an address synchronization circuit 111 and an ACK transmission circuit 114 that returns an NACK response for inserting a weight and an ACK response indicating data return.

  140 in FIG. 9 shows the waveform of the clock of the serial interface between the processor 100 and the interface circuit 110 in FIG. 8, and 150 shows the waveform of the address / data signal. Reference numeral 160 denotes a PLL lock presence / absence signal connected to the ACK transmission circuit 114 from the PLL 113 in the interface circuit 110 of FIG.

  Hereinafter, the operation will be described with reference to FIGS. The processor 100 starts loading programs and data when the internal PLL 104 is stabilized. First, the processor 100 outputs a clock. The waveform of FIG. 9 indicates “boot start” and starts outputting the clock 140.

  Next, the processor 100 adds a start bit to the address output from the processor core 101 and outputs it to the address / data signal line in synchronization with the falling edge of the clock (waveform 140) by the address synchronization circuit 102. This is the location described in the waveform 150 of FIG. 9 as “the processor sends start bit + address”. In the waveform 150, ST is the start bit, and A7, A6, and A0 are the 7th and 6th bits of the address, respectively. Indicates the 0th bit. The address synchronization circuit 111 in the interface circuit 110 samples the start bit and address at the rising edge of the serial interface clock (waveform 140), and outputs the result to the general purpose ROM 120.

  At this time, since the PLL 113 of the interface circuit 110 is not yet locked, data cannot be transmitted at a timing at which the processor 100 can sufficiently sample. Therefore, the interface circuit 110 waits for the processor 100 until the PLL 113 is locked, and therefore continues to send the NACK response created by the ACK sending circuit 114 to the address / data signal. The portion described as “NACK” in the waveform 150 of FIG. 9 corresponds to this.

  When the PLL 113 in the interface circuit 110 receives the clock sufficiently and completes the lock, the data synchronization circuit 112 synchronizes the ACK response generated by the ACK transmission circuit 114 and the data in sequence with the falling edge of the clock (waveform 140). Output to the data signal line. When all of this data is sent, a stop bit is added at the end to indicate to the processor 100 that the transfer is complete. These are the locations described as “Serial ROM sends ACK + data + stop bit” in the waveform 150 of FIG. 9, where ACK is an ACK response on the waveform 150, D7 and D6 are the seventh bit and 6 of the data, respectively. Shows the bit eye. The data synchronization circuit 103 in the processor 10 samples the ACK, data, and stop bit at the rising edge of the serial interface clock (waveform 140), extracts the result, and outputs it to the processor core 101.

In this way, when the PLL must always be locked first using the high-speed clock, for example, at the time of booting immediately after the power is turned on, it is necessary to insert a certain time wait from the clock transmission, and the high-speed clock is used. Nevertheless, the total time reduction is not as effective as expected.
JP 11-328980 A Japanese Patent Laid-Open No. 7-118705 “IBM PowerNP NP4GS3 Network Processor Hardware Reference Manual”, IBM Corp., p. 438

  As described above, it is almost essential to use a PLL in serial data transfer using a high-speed clock. However, since the PLL receives the clock and feeds it back, the PLL output clock cannot be locked unless the clock is received to some extent. In other words, if the PLL used is locked once, high-speed data transfer to the processor can be performed using the clock, but the clock output typified by boot immediately after power-on is started and the program is loaded. In this case, data cannot be transferred from the memory to the processor until the clock is locked.

  This is because the boot sequence immediately after power-on requires a quick program start-up, so a wait is entered until the PLL is locked, despite the attempt to shorten the time using a high-speed serial clock. The result is that the total time reduction is not as effective as expected.

  The present invention is intended to solve such a problem that the conventional configuration has. The data is transferred even when the PLL is not locked, and the total of the program and data storage time in the initial sequence such as boot is obtained. It aims at shortening.

  In order to achieve the above object, the present invention has a configuration of a processor and a memory having a serial interface using a high-speed clock, and the memory has a low-speed clock and a serial that can send data at a timing that can be sufficiently received by the processor without using a PLL. Whether the internal clock has two types of clocks, the high-speed clock created from the interface clock through the PLL, and the processor also has the serial interface high-speed clock and the low-speed clock similar to the memory created from that, and the memory-side PLL is locked By switching the internal clock of the memory and processor from low speed to high speed at the same time with a signal indicating whether or not the transfer has conventionally been waited until the PLL is locked, no data is inserted and efficient data transfer is performed. I can do it.

  Also, when a high-speed clock that requires PLL synchronization is used as the interface clock between the processor and memory connected by the serial interface, both the processor and memory can communicate without using the high-speed clock and PLL from the interface clock internally. Two types of clocks are prepared, and a signal indicating whether the PLL that creates the internal high-speed clock is locked is connected between the processor and the memory, and the internal clock of the processor and memory is simultaneously switched from low to high with this signal. By transmitting and receiving data, data transfer with no weight inserted is performed.

  In addition, the internal clock of the processor and memory is switched from low speed to high speed by adding clock switching information to data exchanged between the processor and memory instead of a signal indicating whether the PLL connected between the processor and memory is locked. The data is transmitted and received, and the data is transferred with no weight inserted.

  A data transmission / reception method in which a data transmission node and a data reception node transmit / receive data via a digital interface, wherein a first high-speed clock generated from an external clock at the data transmission node is synchronized with the external clock. A process of starting, a process of generating a first low-speed clock having a frequency lower than that of the high-speed clock from an external clock, a process of determining whether or not the first high-speed clock is synchronized, and a first high-speed clock If the first high-speed clock is not synchronized with the process of notifying the receiving node whether or not is synchronized, the first low-speed clock is selected and the first high-speed clock is synchronized In this case, the process of selecting the first high-speed clock is synchronized with either the selected first low-speed clock or the first high-speed clock. If the first high-speed clock is not synchronized with the process of transmitting data, the process of generating a second low-speed clock having a frequency lower than that of the high-speed clock at the data receiving node, and the notification from the transmission node, If the first low-speed clock is selected and the first high-speed clock is synchronized, the process of selecting the high-speed clock and the data transmitted from the transmission node can be selected from the selected second low-speed clock or high-speed clock. And a step synchronized with one of the clocks.

  A data transmission / reception method in which a data transmission node and a data reception node transmit / receive data via a digital interface, wherein the first high-speed clock generated from an external clock is synchronized with the external clock at the data transmission node A process of generating a first low-speed clock whose frequency is lower than that of the high-speed clock, a process of determining whether or not the first high-speed clock is synchronized, and a first high-speed clock When the clocks are not synchronized, the first low-speed clock is selected, and when the first high-speed clock is synchronized, the process of selecting the first high-speed clock is synchronized with the first high-speed clock. A process for adding information on whether or not to the data and a process for transmitting the data in synchronization with the selected clock. A step of generating a second low-speed clock having a frequency lower than that of the high-speed clock from an external clock, a step of receiving data and detecting information on whether or not the first high-speed clock is synchronized; According to the information, when the first high-speed clock is not synchronized, the second low-speed clock is selected. When the first high-speed clock is synchronized, the process of selecting the clock and the transmission from the transmission node are transmitted. Synchronizing data to the selected clock.

  A data transmission / reception system in which a data transmission node and a data reception node transmit and receive data via a digital interface, wherein the data transmission node is a first low-speed clock having a frequency lower than that of a high-speed clock from an external clock. A first clock frequency dividing circuit for generating a clock, a phase locked loop for generating a high speed clock in synchronization with an external clock, and a first clock for selecting one of the first low speed clock and the high speed clock. A switching circuit and data transmission means for transmitting data in synchronization with a clock selected by the first clock switching circuit, and the data receiving node is a second having a frequency lower than that of the high-speed clock from the external clock. A second clock dividing circuit for generating a low-speed clock, a high-speed clock and a second low-speed clock A second clock switching circuit for selecting one, receives data transmitted from the data transmission means is synchronized with the clock selected in the second clock switching circuit, and a data receiving means.

  The phase-locked loop transmits a first clock switching signal indicating whether or not the first high-speed clock is synchronized with an external clock to the first clock switching circuit and the second clock switching circuit in the previous period. .

  The phase-locked loop transmits a first clock switching signal indicating whether or not the first high-speed clock is synchronized with the external clock to the first clock switching circuit, and the first node A data switching signal adding circuit that receives a clock switching signal, adds clock switching information to data, and inputs the data to a data transmission means. The second node receives the data and generates a second clock switching signal. And a clock switching signal separation circuit that is input to the first clock switching circuit.

  According to the present invention, it is possible to operate with a low-speed clock until the PLL is locked. As a result, data can be transferred from the memory to the processor even before the PLL is locked, and the program can be loaded more quickly.

  FIG. 1 shows a block diagram of Embodiment 1 of the present invention. FIG. 3 is a flowchart showing an outline of the operation procedure, and FIG. 5 is a waveform diagram showing waveforms of interface signals.

  Reference numeral 1 in FIG. 1 denotes a processor, which has a serial interface for reading programs and data. Reference numeral 2 denotes a serial ROM for storing programs and data. Reference numerals 1 and 2 are connected by three signal lines of a clock, an address / data serial interface signal, and a clock switching signal. A clock oscillator 3 supplies a clock to the processor 1, and the processor 1 uses the internal PLL 16 to convert this clock to a faster clock and supply it to the internal and serial interfaces.

  In the processor 1, a clock frequency dividing circuit 15 for generating a low-speed clock (hereinafter referred to as a low-speed clock) obtained by dividing the clock from the PLL, and the low-speed clock and the high-speed clock that remains the output of the PLL 16 are switched. There are a clock switching circuit 14, an address synchronization circuit 12, a data synchronization circuit 13, and a processor core 11, which synchronize addresses and data with the 16 output clocks.

  The serial ROM 2 receives the interface clock and generates a transmission / reception timing clock from the PLL 26. The clock divider 25 divides the interface clock without passing through the PLL to create a low-speed clock in the same manner as the processor 1. There are a clock switching circuit 24 for switching the low-speed clock and the output clock of the PLL 26, an address synchronization circuit 22, a data synchronization circuit 23, and a memory core 21 for synchronizing addresses and data with the output clock of the 24.

  Reference numeral 80 in FIG. 5 indicates the waveform of the clock of the serial interface between the processor 1 and the serial ROM 2 in FIG. 1, and reference numeral 81 indicates the waveform of the clock supplied to the synchronization circuits 12, 13, 22, 23 in the processor 1 and the serial ROM 2. , 82 are waveforms of address / data signals between the processor 1 and the serial ROM 2, and 83 is a clock switching signal output from the PLL 26 in the serial ROM 2 to the clock switching circuits 14, 24.

Hereinafter, the operation in the first embodiment will be described with reference to FIGS. 1 and 5 along FIG. When the PLL 16 that receives a clock from the clock oscillator 3 and creates an internal clock is locked, the processor 1 starts loading (booting) a program and data, and outputs a clock from the processor 1 to the serial ROM 2. This is a waveform that starts outputting the clock 80 as "boot start" in FIG. At this time, since the PLL 26 in the serial ROM 2 is not yet locked, the clock switching signal (waveform 83 in FIG. 5) is in a state of selecting a low-speed clock. A low-speed clock having the same frequency generated by the peripheral circuit is selected. (Waveform 81 in FIG. 5)
Next, the processor 1 adds a start bit to the address output from the processor core 11, and outputs it to the address / data signal line in synchronization with the falling edge of the low-speed clock (waveform 81 in FIG. 5) by the address synchronization circuit 12. This is the location described in the waveform 81 of FIG. 5 as “the processor sends the start bit + address”. On the waveform 81, ST indicates the start bit, and A7 and A0 indicate the 7th and 0th bits of the address, respectively. ing.

  The serial ROM 2 that has received the start bit and the address samples at the rising edge of the low-speed clock (waveform 81 in FIG. 5) by the internal address synchronization circuit 22, extracts the address, and outputs it to the memory core 21.

  When the data corresponding to the address received by the memory core 21 is output, the data synchronization circuit 23 adds an ACK response and a stop bit before and after the data, and sequentially synchronizes with the falling edge of the clock (waveform 81 in FIG. 5). Output to the data signal line. Here, the ACK response is the start of data transmission, and the stop bit is the bit indicating the end of data transmission. These are the locations described by the serial ROM as “ACK + data + send stop bit” in the waveform 82 of FIG. In the waveform 82, ACK indicates an ACK response, D7 indicates the seventh bit of data, and SP indicates a stop bit.

  The data synchronization circuit 13 in the processor 1 samples this ACK, data, and stop bit at the rising edge of the low-speed clock (waveform 81 in FIG. 5), extracts the data, and outputs it to the processor core 11.

  In this way, one serial ROM reading operation is completed, but as the transfer using the low-speed clock is continued, the PLL 26 in the serial ROM 2 receives a sufficient number of clocks of the serial interface and the lock is completed. The PLL 26 in the serial ROM 2 notifies this to the internal clock switching circuit, and simultaneously notifies the clock switching circuit 14 in the processor 1 through the clock switching signal. This corresponds to the part described as “Serial ROM sends PLL lock signal” in waveform 83 of FIG. Upon completion of the lock, the processor 1 and the serial ROM 2 simultaneously switch the internal clock from the low-speed clock to the high-speed clock having the same frequency as that of the serial interface clock when the transfer using a series of low-speed clocks is completed. The waveform 83 in FIG. 5 explains this as “switching the internal clock to a high-speed clock”.

  Thereafter, the processor 1 and the serial ROM 2 perform the serial ROM read operation using the high-speed clock in the same procedure as the transfer using the low-speed clock, and perform the program (or data) load (boot) operation. Thus, by performing the transfer even when the PLL is not locked, the time required for booting can be reduced.

  FIG. 2 is a block diagram according to the second embodiment of the present invention. FIG. 4 is a flowchart showing the operation procedure at that time.

  Reference numeral 4 in FIG. 2 denotes a processor, which has a serial interface for reading programs and data. A general-purpose ROM 6 stores programs and data and does not have a serial interface. Therefore, the serial interface circuit 5 enters the middle of the processor 4 and interfaces with the processor 4. The processor 4 and the serial interface circuit 5 are connected by a serial interface signal of clock and address / data, and the serial interface circuit 5 and the general purpose ROM 6 are connected by a general parallel interface of address and data. A clock oscillator 7 supplies a clock to the processor 4. The processor 4 uses an internal PLL 47 to make this clock faster and supplies it to the internal and serial interfaces.

  In the processor 4, a clock frequency dividing circuit 46 that generates a low-speed clock (hereinafter referred to as a low-speed clock) obtained by dividing the clock from the PLL, and the low-speed clock and the high-speed clock that is output from the PLL 47 are switched. A clock switching circuit 45, an address synchronization circuit 42 that synchronizes addresses and data with the output clock of the 45, a data synchronization circuit 43, a clock switching detection circuit that detects a clock switching pattern from the extracted data, and a processor core 41 is there.

  The serial interface circuit 5 receives an interface clock and generates a transmission / reception timing clock from the PLL 57, a frequency dividing circuit 56 that divides the interface clock to create a low-speed clock similar to the processor 4, and the low-speed clock. A clock switching circuit 54 that switches the output clock of the PLL 57, an address synchronization circuit 51 that synchronizes addresses and data with the output clock of the 54, a data synchronization circuit 52, a switching pattern generation circuit that generates a clock switching pattern, and a general-purpose ROM There is a data switching circuit 53 for switching and transmitting data and clock switching patterns.

  Hereinafter, the operation in the second embodiment will be described with reference to FIG. In the initial state, both the processor 4 and the serial interface circuit 5 are set to use a low-speed clock generated by dividing the clock. When the PLL 47 that receives the clock from the clock oscillator 7 and generates the interface clock and the internal clock is locked, the processor 4 starts booting.

  First, a clock is output from the processor 4 to the serial interface circuit 5, then a start bit is added to the address output from the processor core 41, and an address / data signal is synchronized with the falling edge of the low-speed clock by the address synchronization circuit 42. Output to line. The serial interface circuit 5 that has received the start bit and the address samples the internal address synchronization circuit 51 using the low-speed clock rise, extracts the address, and outputs it to the general-purpose ROM 6.

  When the data corresponding to the address received by the general-purpose ROM 6 is output, the data synchronization circuit 52 in the interface circuit 5 adds an ACK response and a stop bit before and after the data, and sequentially synchronizes with the falling edge of the low-speed clock. Output to the signal line. Here, the ACK response indicates the start of data transmission, and the stop bit indicates the end of data transmission. The data synchronization circuit 43 in the processor 4 samples the ACK, data, and stop bit at the rising edge of the low-speed clock, extracts the data, and outputs it to the clock switching detection circuit 44. Since the clock switching detection circuit 44 does not detect a specific pattern indicating clock switching, the received data is output to the processor core 41 as it is.

  In this way, one serial ROM read operation using the low-speed clock is completed. As the transfer using the low-speed clock continues, the PLL 57 in the serial interface circuit 5 receives a sufficient number of serial interface clocks and locks them. Is completed. The PLL 57 notifies this to the clock switching circuit 54 and simultaneously notifies the switching pattern creation circuit 55 which creates a clock switching pattern. In response to this notification, the data switching circuit 53 sends a switching pattern instead of data in the current transfer cycle, and the data synchronizing circuit 52 sends it to the processor 4 in synchronization with the low-speed clock.

  When the clock switching detection circuit 44 detects this switching pattern, the processor 4 switches the internal clock from the low-speed clock to the high-speed clock after a predetermined time. At the same timing, the serial interface circuit 5 also switches the internal clock from the low-speed clock to the high-speed clock having the same frequency as that of the serial interface clock.

  Now, the processor 4 and the serial interface circuit 5 can read out the ROM using the high-speed clock, so the address synchronization circuit 42 in the processor 4 sets the start bit again to the address to which the switching pattern has been returned. In addition, the data is transmitted to the serial interface circuit 5 in synchronization with the high-speed clock. The serial interface circuit 5 that has received the start bit and the address samples by using the rising edge of the high-speed clock in the internal address synchronization circuit 51, extracts the address, and outputs it to the general-purpose ROM 6.

  When the data corresponding to the address received by the general-purpose ROM 6 is output, the data synchronization circuit 52 in the interface circuit 5 adds an ACK response and stop bit before and after the data, and sequentially synchronizes with the falling edge of the high-speed clock. Output to the data signal line.

  The data synchronization circuit 43 in the processor 4 samples the ACK, data, and stop bit at the rising edge of the high-speed clock, extracts the data, and outputs it to the processor core 41.

  Thereafter, the processor 4 and the serial interface circuit 5 perform the ROM read operation using the high-speed clock in the same procedure as the transfer using the low-speed clock.

  Thus, in this embodiment, it is possible to reduce the time required for booting or the like by performing transfer even when the PLL is not locked without newly adding a signal line.

It is a block diagram which shows one Example by the processor and serial ROM to which this invention was applied. 1 is a block diagram showing an embodiment of a processor, a serial interface circuit, and a ROM to which the present invention is applied. FIG. It is a flowchart which shows the operation | movement procedure of the serial interface in the Example shown in FIG. It is a flowchart which shows the operation | movement procedure of the serial interface in the Example shown in FIG. It is a wave form diagram which shows the waveform of the serial interface in the Example shown in FIG. It is a block diagram which shows the structural example by the conventional processor and serial ROM. It is a wave form diagram which shows an example of the waveform of the serial interface in the conventional structure shown in FIG. It is a block diagram which shows an example at the time of using a high-speed interface clock by the structure by the conventional processor and serial ROM. It is a wave form diagram which shows an example of the waveform of a serial interface with the structure shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Processor 11 Processor core 12 Address synchronization circuit 13 Data synchronization circuit 14 Clock switching circuit 15 Clock division circuit 16 PLL
2 Serial ROM
21 Memory Core 22 Address Synchronization Circuit 23 Data Synchronization Circuit 24 Clock Switching Circuit 25 Clock Dividing Circuit 26 PLL
3 clock oscillator 4 processor 41 processor core 42 address synchronization circuit 43 data synchronization circuit 44 clock switching signal separation circuit 45 clock switching circuit 46 clock dividing circuit 47 PLL
5 Serial Interface Circuit 51 Address Synchronization Circuit 52 Data Synchronization Circuit 53 Clock Switch Signal Circuit 54 Clock Switch Circuit 55 Clock Divider Circuit 56 PLL
6 General-purpose ROM
7 Clock oscillator 80 Clock signal waveform 81 Address / data synchronous clock waveform 82 Address / data signal waveform 83 Clock switching signal waveform 91 Processor 92 Serial ROM
93 Clock signal 94 Data signal 95 Serial ROM clock input terminal 96 Serial ROM data input terminal 97 Serial ROM data output terminal 100 Processor 101 Processor core 102 Address synchronization circuit 103 Data synchronization circuit 104 PLL
110 Serial interface circuit 111 Address synchronization circuit 112 Data synchronization circuit 113 PLL
114 ACK transmission circuit 120 General-purpose ROM
130 clock oscillator

Claims (7)

When a high-speed clock that requires PLL synchronization is used as the interface clock between the processor and memory connected via the serial interface,
Both processor and memory have two types of clocks: a high-speed clock from the interface clock and a low-speed clock that can communicate without using a PLL.
Connect a signal between the processor and memory to indicate whether the PLL that creates the internal high-speed clock is locked,
A serial interface system characterized in that, by this signal, the internal clocks of the processor and the memory are switched at the same time from low speed to high speed to transmit and receive data, thereby transferring data without inserting a wait. By adding clock switching information to data exchanged between the processor and the memory instead of a signal indicating whether or not the PLL connected between the processor and the memory of claim 1 is locked,
A serial interface system characterized in that the internal clock of the processor and memory is switched from low speed to high speed to transmit and receive data and to transfer data without inserting a wait. A data transmission / reception method in which a data transmission node and a data reception node transmit / receive data via a digital interface,
Starting a synchronization of the first high-speed clock generated from an external clock at the data transmission node with the clock;
Generating a first low-speed clock having a lower frequency than the clock from the clock;
Determining whether the first high-speed clock is synchronized;
A step of notifying the receiving node whether or not the first high-speed clock is synchronized;
Selecting the first low-speed clock when the first high-speed clock is not synchronized; and selecting the first high-speed clock when the first high-speed clock is synchronized;
A step of transmitting data in synchronization with one of the selected first low-speed clock and the first high-speed clock;
Generating a second low-speed clock having a lower frequency than the clock at the data receiving node;
When the first high-speed clock is not synchronized with the notification from the transmission node, the second low-speed clock is selected, and when the first high-speed clock is synchronized, the clock is selected. The process,
A process of synchronizing data transmitted from the transmission node with either the selected second low-speed clock or the clock;
A data transmission / reception method comprising: A data transmission / reception method in which a data transmission node and a data reception node transmit / receive data via a digital interface,
In the data transmission node,
Starting a synchronization of the first high-speed clock generated from the clock with the clock;
Generating a first low-speed clock having a lower frequency than the external clock;
Determining whether the first high-speed clock is synchronized;
Selecting the first low-speed clock when the first high-speed clock is not synchronized; and selecting the first high-speed clock when the first high-speed clock is synchronized;
A step of adding information as to whether or not the first high-speed clock is synchronized to data; and a step of transmitting the data in synchronization with the selected clock.
In the data receiving node,
Generating a second low-speed clock having a lower frequency than the external clock;
Receiving the data and detecting the information as to whether the first high-speed clock is synchronized;
Selecting the second low-speed clock when the first high-speed clock is not synchronized according to the information, and selecting the clock when the first high-speed clock is synchronized;
A step of synchronizing data transmitted from the transmission node with a selected clock;
A data transmission / reception method comprising: A data transmission / reception system in which a data transmission node and a data reception node transmit / receive data via a digital interface,
The data transmission node is:
A first clock frequency dividing circuit for generating a first low-speed clock having a frequency lower than that of the clock from an external clock;
A phase-locked loop that generates a high-speed clock in synchronization with the clock;
A first clock switching circuit that inputs the first low-speed clock and the high-speed clock and selects one of them;
Data transmitting means for transmitting data in synchronization with a clock selected by the first clock switching circuit;
The data receiving node is:
A second clock frequency dividing circuit that generates a second low-speed clock having a frequency lower than that of the clock from the external clock;
A second clock switching circuit for selecting one of the clock and the second low-speed clock;
Data receiving means for receiving data transmitted from the data transmitting means and synchronizing with a clock selected by the second clock switching circuit;
A data transmission / reception system comprising: The phase-locked loop is
The first clock switching signal indicating whether or not the first high-speed clock is synchronized with the clock is transmitted to the first clock switching circuit and the second clock switching circuit in the previous period. 5. The data transmission / reception system according to 5. The phase-locked loop is
Transmitting a first clock switching signal indicating whether or not the first high-speed clock is synchronized with the clock to the first clock switching circuit;
The first node is:
A data switching signal adding circuit that receives the first clock switching signal, adds clock switching information to the data, and inputs the data to the data transmission means;
The second node is
6. The data transmission / reception system according to claim 5, further comprising a clock switching signal separation circuit that receives the data, generates a second clock switching signal, and inputs the second clock switching signal to the first clock switching circuit.

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