JP2002261741A - Lock-switching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock-switching circuit which solves a system trouble by the drift/slip detection, in the event of a frequency failure in an input clock in a transmission system having a redundant structure. SOLUTION: A reception clock switching controller 15 is provided for switching-over clock switching circuits 12a, 12b, having redundant structures. The reception clock switching circuit 12a, 12b switch-over input clocks, when both system detect drift/slip alarms ALM7a, ALM7b of PLL circuits 13a, 13b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock switching circuit,
In particular, the present invention relates to a clock switching circuit that switches from a first clock to a second clock when an abnormality occurs in an input clock frequency.

[0002]

2. Description of the Related Art In a digital circuit such as a digital transmission device, a clock is indispensable as an operation reference of each component in the device. Therefore, if an abnormality occurs in the clock, the operation of the transmission device stops, and a countermeasure is required. As a countermeasure against this, in a conventional digital transmission device, for example, a redundant system is generally used in which a clock input is duplicated. When a trouble occurs in one (operating system) of such a duplicated clock circuit, a clock switching circuit is used to switch to the other (non-operating system).

Conventional examples of the clock switching circuit and related circuits include, for example, a "synchronous signal supply device" in Japanese Patent Application Laid-Open No. 6-141027 and an "abnormality detection circuit of a phase-locked oscillator" in Japanese Patent Application Laid-Open No. 4-165818. It has been disclosed. The configuration of the former prior art is shown in the block diagram of FIG.
This conventional synchronous signal supply device includes a clock receiving circuit 11
a, 11b, reception clock switching circuits 12a, 12b, P
It comprises LL (Phase-Locked Loop) circuits 13a and 13b, distributors 14a and 14b, and a reception clock switching control unit 15.

In the synchronous signal supply device shown in FIG. 4, clock receiving circuits 11a and 11b branch and output two clock inputs CLK1 and CLK2, respectively. The reception clock switching circuits 12a and 12b switch between the two clocks CLK3a and CLK3b output from the clock reception circuits 11a and 11b. PLL circuit 13
a and 13b perform frequency conversion of the clocks CLK4a and 4b selected by the reception clock switching circuits 12a and 12b. The distributors 14a and 14b are provided with a PLL circuit 13a,
The frequency of the output clock CLK5a, 5b of 13b is divided and distributed. As described above, each system has a redundant system, and even if a trouble (failure) occurs in one of the systems, the operation of the system is guaranteed by using the other system.

[0005]

It is common to detect drift / slip in a PLL circuit. However, the conventional drift / slip detection is provided for detecting a failure of a PLL circuit, and is based on the assumption that no abnormality occurs in the frequency of an input clock. By monitoring the phase of the oscillation clock (output clock) of the PLL circuit and the phase of the input clock input to the PLL circuit, the PL
L circuit failure is detected. Therefore, in the conventional circuit, when a frequency abnormality occurs in the selected clock input, the phase relationship between the oscillation clock and the clock input of the PLL circuit becomes abnormal, although the PLL circuit is normal. Drift / slip is detected. Furthermore,
In the redundant system of the PLL circuits, since both select the same clock, both the PLL circuits fail, and the whole system fails even though the unselected clock input side is normal. there were.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to address the above-mentioned problems,
An object of the present invention is to provide a clock switching circuit for preventing a system failure due to a PLL circuit failure.

[0007]

A clock switching circuit according to the present invention includes a pair of clock receiving circuits, a receiving clock switching circuit, a PLL circuit, and a distributor to which respective clocks are input, and further includes a receiving clock switching control circuit. Having a reception clock switching control unit that controls switching of the input clock of
A circuit that outputs an output clock from a distributor, and outputs a switch control signal for switching an input clock of a reception clock switching circuit based on a frequency monitoring result output from a pair of PLL circuits.

Further, according to a preferred embodiment of the clock switching circuit of the present invention, when a drift / slip alarm based on an input / output clock of a pair of PLL circuits is detected together, a switching for switching an input clock of a reception clock switching circuit is performed. Generate control signals. After the generation of the switching control signal, the switching control signal is held for a predetermined period of time. This fixed time is set after the switching of the clock signal.
Choose longer than the time for the L circuit to recover drift / slip. Drift from only one of the pair of PLL circuits /
When a slip alarm is detected, the input clock is held and the clock is not switched.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a preferred embodiment of a clock switching circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a preferred embodiment of a clock switching circuit according to the present invention. In this clock switching circuit, the same reference numerals are used for components corresponding to the components shown in FIG. 4 for convenience of description. This clock switching circuit is similar to the conventional clock switching circuit shown in FIG.
11b, reception clock switching circuits 12a, 12b, PLL
It is composed of circuits 13a and 13b, distributors 14a and 14b, and a reception clock switching control unit 15.

In FIG. 1, a clock receiving circuit 11a,
11b receives input clocks CLK1 and CLK2 from the outside, respectively. Clock receiving circuits 11a, 1
1b indicates the output clocks CLK3a and CLK3b,
Output to the receiving clock switching circuits 12a12b at the subsequent stage. The reception clock switching circuits 12a and 12b
3a and CLK3b are switched, and the clock CLK4
a and CLK4b to PLL circuits 13a and 13
Output to b. The PLL circuits 13a and 13b generate clocks CLK5a and CLK5b synchronized with the clocks CLK4a and CLK4b, and generate the distributors 14a,
14B and generates drift / slip alarms ALM7a and ALM7b and outputs them to the reception clock control circuit 15. These alarms AL
M7a and ALM7b are PLL circuits 13a and 13b
Is a drift / slip alarm signal detected. Further, the reception clock switching control unit 15 is a switching control unit that generates a switching control signal by the ALM 7a and the ALM 7b. The distributors 14a and 14b each have a clock CL
It receives K5a and CLK5b, generates and outputs distributed clocks CLK6a and CLK6b, respectively.

In the clock switching circuit shown in FIG. 1, receiving circuits 11a and 11b and reception clock switching circuits 12a and 12
b, PLL circuits 13a, 13b, distributors 14a, 14b
The reception clock switching control section 15 itself is well known to those skilled in the art, and thus the detailed configuration of each of these circuits is omitted.

Next, the operation of the preferred embodiment of the clock switching circuit shown in FIG. 1 will be described. As shown in FIG. 1, clock receiving circuits 11a and 11b receive two external input clocks CLK1 and CLK2, and generate clocks CLK3a and CLK3b to be distributed to reception clock switching circuits 12a and 12b. Receive clock switching circuit 12
a and 12b receive the clocks CLK3a and CLK3b, switch the clocks CLK3a and CLK3b according to the switching control signal from the reception clock switching control unit 15, and supply the clocks CLK to the PLL circuits 13a and 13b.
4a and CLK4b.

The receiving clock switching controller 15 outputs a switching control signal to the receiving clock switching circuits 12a and 12b based on the frequency drift / slip alarms ALM7a and ALM7b detected by the PLL circuits 13a and 13b. The PLL circuits 13a and 13b provide a clock C synchronized with the reception clocks CLK4a and CLK4b.
LK5a and CLK5b are output. The PLL circuits 13a and 13b detect the frequency drift / slip alarms ALM7a and ALM7b. Frequency drift / slip alarm ALM7a and ALM7b
Is detected, the frequency drift / slip alarm ALM7a is transmitted to the reception clock switching control unit 15.
And ALM7b. Distributors 14a, 14b
Is the clock CLK5 from the PLL circuits 13a and 13b.
output clock CLK obtained by dividing a and CLK5b
6a and CLK6b are distributed and output.

Next, the operation of the reception clock switching control unit 15 will be described with reference to the flowchart of FIG. 2, in the initial state (step S1), it is assumed that the clock CLK3a is selected in the reception clock switching circuit 12. At this time, it is determined whether or not the frequency abnormality of the clock CLK3a has occurred and the frequency drift / slip alarms ALM7a and ALM7b have occurred in both the PLL circuits 13a and 13b (step S).
2). When frequency drift / slip alarms ALM7a and ALM7b occur (step S2: Ye)
In s), since the clock CLK3a is currently selected, switching to the non-selection system clock CLK3b is performed (step S4). However, for example, the PLL circuit 13a breaks down,
If only the frequency drift / slip alarm ALM7a has occurred (Step S2: No), only one of the systems has failed, so the input clock is normal and the PLL circuit 13a
It is considered to be a failure of itself. Therefore, the currently selected (that is, selected) clock CLK3a is selected as it is (step S3). If the switching to another system is performed in step S4 described above, the frequency drift / slip alarms ALM7a and ALM7b are not recovered immediately after the switching, and there is a possibility that extra switching may occur again. Therefore, immediately after the switching in step S4 described above,
The switching control signal to the receiving clock switching circuit 12 in FIG. 1 is held for a preset T1 seconds (step S5). The holding time (T1) is set by obtaining a value having a margin in a time until the PLL circuit 13 recovers from the frequency drift / slip after switching the input clock, for example, by an experiment or the like.

Next, the reception clock switching circuit 1 shown in FIG.
2 will be described with reference to the timing chart of FIG. In the timing chart of FIG.
(A) Alarm ALM7a, (b) Alarm ALM
7b and (c) show the clock 4. In the initial state, the clock CLK4 is in a state where CLK3a is selected. At this time, when the drift / slip alarms ALM7a and ALM7b occur in the PLL circuits 13a and 13b, the clock CLK4 is changed to the clock CL.
Select K3b. These alarms ALM7a and A
LM7b is considered to have occurred for T2 seconds. In order to hold the switching control signal for T1 seconds longer than T2, the receiving clock switching control unit 15
It is not switched to LK3a.

The configuration and operation of the preferred embodiment of the clock switching circuit according to the present invention have been described above in detail. However, such an embodiment is merely an example of the present invention and does not limit the present invention in any way. For example, it goes without saying that the processing in the reception clock switching control unit 15 can be realized by a CPU (central processing unit) equipped with a program.

[0018]

As will be understood from the above description, the clock switching circuit of the present invention has the following practically significant effects. First, when the frequency of the input clock being selected (selection system) becomes abnormal, it is possible to prevent the PLL circuits of both systems from detecting a frequency drift / slip alarm and causing a system failure. The drift / slip alarm of the PLL circuit is used to monitor the failure of the PLL circuit itself.
When a drift / slip alarm occurs in the LL circuit, it is determined that both the PLL circuits have failed, and the system has failed. Drift / slip detection is monitored by comparing the input clock with the output clock of the PLL circuit, and therefore occurs even when the frequency of the input clock becomes abnormal. Therefore, both systems PLL
Since the input clocks of the circuits are the same signal, if the frequency of the input clock becomes abnormal, a drift / slip alarm occurs in both the PLL circuits, resulting in a system failure. However, according to the present invention, only when a drift / slip alarm of both the PLL circuits has occurred, it is determined that the frequency of the input clock is abnormal, and the switching is generated by controlling the input clock switching signal. As a result, even if the frequency of the input clock becomes abnormal, a system failure does not occur.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a preferred embodiment of a clock switching circuit according to the present invention.

FIG. 2 is a flowchart showing an operation of a reception clock switching control unit shown in FIG.

FIG. 3 is a timing chart showing an operation of the reception clock switching circuit shown in FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of a conventional clock switching circuit.

[Explanation of symbols]

 11a, 11b Clock receiving circuit 12a, 12b Receiving clock switching circuit 13a, 13b PLL circuit 14a, 14b Distributor 15 Receiving clock switching control unit ALM7a, ALM7b Drift / slip alarm

Claims (5)

[Claims] 1. A receiving clock switching control, comprising: a pair of clock receiving circuits, receiving clock switching circuits, a PLL circuit, and a distributor to which respective clocks are inputted, and further controlling switching of an input clock of the receiving clock switching circuit. A clock switching circuit that outputs an output clock from the distributor, and outputs a switching control signal that switches an input clock of the reception clock switching circuit based on a frequency monitoring result output from the pair of PLL circuits. A clock switching circuit, characterized in that: 2. A switching control signal for switching an input clock of the reception clock switching circuit when both a drift / slip alarm based on input / output clocks of the pair of PLL circuits are detected. Item 2. The clock switching circuit according to item 1. 3. The clock switching circuit according to claim 1, wherein the switching control signal is held for a predetermined period of time after the generation of the switching control signal. 4. The clock switching circuit according to claim 3, wherein the predetermined time is selected to be longer than a time for the PLL circuit to recover from drift / slip after the switching of the clock signal. 5. The method according to claim 1, wherein when said drift / slip alarm is detected from only one of said pair of PLL circuits, said input clock is held and switching is not performed. The clock switching circuit according to any one of the above.